drivers/net/igb/e1000_defines.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_DEFINES_H_
  29 #define _E1000_DEFINES_H_
  30
  31 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
  32 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
  33 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
  34
  35 /* Definitions for power management and wakeup registers */
  36 /* Wake Up Control */
  37 #define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
  38
  39 /* Wake Up Filter Control */
  40 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  41 #define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  42 #define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  43 #define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
  44 #define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  45
  46 /* Extended Device Control */
  47 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
  48 /* Physical Func Reset Done Indication */
  49 #define E1000_CTRL_EXT_PFRSTD    0x00004000
  50 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
  51 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
  52 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX  0x00400000
  53 #define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
  54 #define E1000_CTRL_EXT_LINK_MODE_GMII   0x00000000
  55 #define E1000_CTRL_EXT_EIAME          0x01000000
  56 #define E1000_CTRL_EXT_IRCA           0x00000001
  57 /* Interrupt delay cancellation */
  58 /* Driver loaded bit for FW */
  59 #define E1000_CTRL_EXT_DRV_LOAD       0x10000000
  60 /* Interrupt acknowledge Auto-mask */
  61 /* Clear Interrupt timers after IMS clear */
  62 /* packet buffer parity error detection enabled */
  63 /* descriptor FIFO parity error detection enable */
  64 #define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
  65 #define E1000_I2CCMD_REG_ADDR_SHIFT   16
  66 #define E1000_I2CCMD_PHY_ADDR_SHIFT   24
  67 #define E1000_I2CCMD_OPCODE_READ      0x08000000
  68 #define E1000_I2CCMD_OPCODE_WRITE     0x00000000
  69 #define E1000_I2CCMD_READY            0x20000000
  70 #define E1000_I2CCMD_ERROR            0x80000000
  71 #define E1000_MAX_SGMII_PHY_REG_ADDR  255
  72 #define E1000_I2CCMD_PHY_TIMEOUT      200
  73 #define E1000_IVAR_VALID              0x80
  74 #define E1000_GPIE_NSICR              0x00000001
  75 #define E1000_GPIE_MSIX_MODE          0x00000010
  76 #define E1000_GPIE_EIAME              0x40000000
  77 #define E1000_GPIE_PBA                0x80000000
  78
  79 /* Receive Descriptor bit definitions */
  80 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
  81 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
  82 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
  83 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
  84 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
  85 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
  86 #define E1000_RXD_STAT_TS       0x10000 /* Pkt was time stamped */
  87
  88 #define E1000_RXDEXT_STATERR_CE    0x01000000
  89 #define E1000_RXDEXT_STATERR_SE    0x02000000
  90 #define E1000_RXDEXT_STATERR_SEQ   0x04000000
  91 #define E1000_RXDEXT_STATERR_CXE   0x10000000
  92 #define E1000_RXDEXT_STATERR_TCPE  0x20000000
  93 #define E1000_RXDEXT_STATERR_IPE   0x40000000
  94 #define E1000_RXDEXT_STATERR_RXE   0x80000000
  95
  96 /* Same mask, but for extended and packet split descriptors */
  97 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
  98     E1000_RXDEXT_STATERR_CE  |            \
  99     E1000_RXDEXT_STATERR_SE  |            \
 100     E1000_RXDEXT_STATERR_SEQ |            \
 101     E1000_RXDEXT_STATERR_CXE |            \
 102     E1000_RXDEXT_STATERR_RXE)
 103
 104 #define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
 105 #define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
 106 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
 107 #define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
 108 #define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
 109
 110
 111 /* Management Control */
 112 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
 113 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
 114 #define E1000_MANC_EN_BMC2OS     0x10000000 /* OSBMC is Enabled or not */
 115 /* Enable Neighbor Discovery Filtering */
 116 #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
 117 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
 118 /* Enable MAC address filtering */
 119 #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
 120
 121 /* Receive Control */
 122 #define E1000_RCTL_EN             0x00000002    /* enable */
 123 #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
 124 #define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
 125 #define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
 126 #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
 127 #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
 128 #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
 129 #define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
 130 #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
 131 #define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
 132 #define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
 133 #define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
 134 #define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
 135 #define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
 136 #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
 137
 138 /*
 139  * Use byte values for the following shift parameters
 140  * Usage:
 141  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
 142  *                  E1000_PSRCTL_BSIZE0_MASK) |
 143  *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
 144  *                  E1000_PSRCTL_BSIZE1_MASK) |
 145  *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
 146  *                  E1000_PSRCTL_BSIZE2_MASK) |
 147  *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
 148  *                  E1000_PSRCTL_BSIZE3_MASK))
 149  * where value0 = [128..16256],  default=256
 150  *       value1 = [1024..64512], default=4096
 151  *       value2 = [0..64512],    default=4096
 152  *       value3 = [0..64512],    default=0
 153  */
 154
 155 #define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
 156 #define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
 157 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
 158 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
 159
 160 #define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
 161 #define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
 162 #define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
 163 #define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
 164
 165 /* SWFW_SYNC Definitions */
 166 #define E1000_SWFW_EEP_SM   0x1
 167 #define E1000_SWFW_PHY0_SM  0x2
 168 #define E1000_SWFW_PHY1_SM  0x4
 169 #define E1000_SWFW_PHY2_SM  0x20
 170 #define E1000_SWFW_PHY3_SM  0x40
 171
 172 /* FACTPS Definitions */
 173 /* Device Control */
 174 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 175 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
 176 #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
 177 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
 178 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
 179 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
 180 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
 181 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
 182 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
 183 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
 184 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
 185 /* Defined polarity of Dock/Undock indication in SDP[0] */
 186 /* Reset both PHY ports, through PHYRST_N pin */
 187 /* enable link status from external LINK_0 and LINK_1 pins */
 188 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 189 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 190 #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
 191 #define E1000_CTRL_RST      0x04000000  /* Global reset */
 192 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 193 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
 194 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 195 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
 196 /* Initiate an interrupt to manageability engine */
 197 #define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
 198
 199 /* Bit definitions for the Management Data IO (MDIO) and Management Data
 200  * Clock (MDC) pins in the Device Control Register.
 201  */
 202
 203 #define E1000_CONNSW_ENRGSRC             0x4
 204 #define E1000_PCS_CFG_PCS_EN             8
 205 #define E1000_PCS_LCTL_FLV_LINK_UP       1
 206 #define E1000_PCS_LCTL_FSV_100           2
 207 #define E1000_PCS_LCTL_FSV_1000          4
 208 #define E1000_PCS_LCTL_FDV_FULL          8
 209 #define E1000_PCS_LCTL_FSD               0x10
 210 #define E1000_PCS_LCTL_FORCE_LINK        0x20
 211 #define E1000_PCS_LCTL_FORCE_FCTRL       0x80
 212 #define E1000_PCS_LCTL_AN_ENABLE         0x10000
 213 #define E1000_PCS_LCTL_AN_RESTART        0x20000
 214 #define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
 215 #define E1000_ENABLE_SERDES_LOOPBACK     0x0410
 216
 217 #define E1000_PCS_LSTS_LINK_OK           1
 218 #define E1000_PCS_LSTS_SPEED_100         2
 219 #define E1000_PCS_LSTS_SPEED_1000        4
 220 #define E1000_PCS_LSTS_DUPLEX_FULL       8
 221 #define E1000_PCS_LSTS_SYNK_OK           0x10
 222
 223 /* Device Status */
 224 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 225 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 226 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 227 #define E1000_STATUS_FUNC_SHIFT 2
 228 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 229 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 230 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 231 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 232 /* Change in Dock/Undock state. Clear on write '0'. */
 233 /* Status of Master requests. */
 234 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
 235 /* BMC external code execution disabled */
 236
 237 /* Constants used to intrepret the masked PCI-X bus speed. */
 238
 239 #define SPEED_10    10
 240 #define SPEED_100   100
 241 #define SPEED_1000  1000
 242 #define HALF_DUPLEX 1
 243 #define FULL_DUPLEX 2
 244
 245
 246 #define ADVERTISE_10_HALF                 0x0001
 247 #define ADVERTISE_10_FULL                 0x0002
 248 #define ADVERTISE_100_HALF                0x0004
 249 #define ADVERTISE_100_FULL                0x0008
 250 #define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
 251 #define ADVERTISE_1000_FULL               0x0020
 252
 253 /* 1000/H is not supported, nor spec-compliant. */
 254 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
 255                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
 256                                                       ADVERTISE_1000_FULL)
 257 #define E1000_ALL_NOT_GIG      (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL | \
 258                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 259 #define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 260 #define E1000_ALL_10_SPEED     (ADVERTISE_10_HALF  |  ADVERTISE_10_FULL)
 261 #define E1000_ALL_FULL_DUPLEX  (ADVERTISE_10_FULL  |  ADVERTISE_100_FULL | \
 262                                                       ADVERTISE_1000_FULL)
 263 #define E1000_ALL_HALF_DUPLEX  (ADVERTISE_10_HALF  |  ADVERTISE_100_HALF)
 264
 265 #define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
 266
 267 /* LED Control */
 268 #define E1000_LEDCTL_LED0_MODE_SHIFT      0
 269 #define E1000_LEDCTL_LED0_BLINK           0x00000080
 270
 271 #define E1000_LEDCTL_MODE_LED_ON        0xE
 272 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 273
 274 /* Transmit Descriptor bit definitions */
 275 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 276 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 277 #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 278 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 279 #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 280 #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 281 #define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 282 /* Extended desc bits for Linksec and timesync */
 283
 284 /* Transmit Control */
 285 #define E1000_TCTL_EN     0x00000002    /* enable tx */
 286 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
 287 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
 288 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
 289 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
 290
 291 /* DMA Coalescing register fields */
 292 #define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coalescing
 293                                                         * Watchdog Timer */
 294 #define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coalescing Receive
 295                                                         * Threshold */
 296 #define E1000_DMACR_DMACTHR_SHIFT       16
 297 #define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe
 298                                                         * transactions */
 299 #define E1000_DMACR_DMAC_LX_SHIFT       28
 300 #define E1000_DMACR_DMAC_EN             0x80000000 /* Enable DMA Coalescing */
 301
 302 #define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coalescing Transmit
 303                                                         * Threshold */
 304
 305 #define E1000_DMCTLX_TTLX_MASK          0x00000FFF /* Time to LX request */
 306
 307 #define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Receive Traffic Rate
 308                                                         * Threshold */
 309 #define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rcv packet rate in
 310                                                         * current window */
 311
 312 #define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rcv Traffic
 313                                                         * Current Cnt */
 314
 315 #define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* Flow ctrl Rcv Threshold
 316                                                         * High val */
 317 #define E1000_FCRTC_RTH_COAL_SHIFT      4
 318 #define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision */
 319
 320 /* SerDes Control */
 321 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
 322
 323 /* Receive Checksum Control */
 324 #define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
 325 #define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
 326 #define E1000_RXCSUM_CRCOFL    0x00000800   /* CRC32 offload enable */
 327 #define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
 328
 329 /* Header split receive */
 330 #define E1000_RFCTL_LEF        0x00040000
 331
 332 /* Collision related configuration parameters */
 333 #define E1000_COLLISION_THRESHOLD       15
 334 #define E1000_CT_SHIFT                  4
 335 #define E1000_COLLISION_DISTANCE        63
 336 #define E1000_COLD_SHIFT                12
 337
 338 /* Ethertype field values */
 339 #define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 340
 341 #define MAX_JUMBO_FRAME_SIZE    0x3F00
 342
 343 /* PBA constants */
 344 #define E1000_PBA_34K 0x0022
 345 #define E1000_PBA_64K 0x0040    /* 64KB */
 346
 347 /* SW Semaphore Register */
 348 #define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
 349 #define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
 350
 351 /* Interrupt Cause Read */
 352 #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
 353 #define E1000_ICR_LSC           0x00000004 /* Link Status Change */
 354 #define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
 355 #define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
 356 #define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
 357 #define E1000_ICR_VMMB          0x00000100 /* VM MB event */
 358 #define E1000_ICR_DRSTA         0x40000000 /* Device Reset Asserted */
 359 /* If this bit asserted, the driver should claim the interrupt */
 360 #define E1000_ICR_INT_ASSERTED  0x80000000
 361 /* LAN connected device generates an interrupt */
 362 #define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
 363
 364 /* Extended Interrupt Cause Read */
 365 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
 366 #define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
 367 #define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
 368 #define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
 369 #define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
 370 #define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
 371 #define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
 372 #define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
 373 #define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
 374 /* TCP Timer */
 375
 376 /*
 377  * This defines the bits that are set in the Interrupt Mask
 378  * Set/Read Register.  Each bit is documented below:
 379  *   o RXT0   = Receiver Timer Interrupt (ring 0)
 380  *   o TXDW   = Transmit Descriptor Written Back
 381  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 382  *   o RXSEQ  = Receive Sequence Error
 383  *   o LSC    = Link Status Change
 384  */
 385 #define IMS_ENABLE_MASK ( \
 386     E1000_IMS_RXT0   |    \
 387     E1000_IMS_TXDW   |    \
 388     E1000_IMS_RXDMT0 |    \
 389     E1000_IMS_RXSEQ  |    \
 390     E1000_IMS_LSC    |    \
 391     E1000_IMS_DOUTSYNC)
 392
 393 /* Interrupt Mask Set */
 394 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
 395 #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
 396 #define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */
 397 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 398 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 399 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
 400 #define E1000_IMS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Asserted */
 401 #define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 402
 403 /* Extended Interrupt Mask Set */
 404 #define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 405
 406 /* Interrupt Cause Set */
 407 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 408 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 409 #define E1000_ICS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Aserted */
 410
 411 /* Extended Interrupt Cause Set */
 412
 413 /* Transmit Descriptor Control */
 414 /* Enable the counting of descriptors still to be processed. */
 415
 416 /* Flow Control Constants */
 417 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
 418 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
 419 #define FLOW_CONTROL_TYPE         0x8808
 420
 421 /* 802.1q VLAN Packet Size */
 422 #define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
 423 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 424
 425 /* Receive Address */
 426 /*
 427  * Number of high/low register pairs in the RAR. The RAR (Receive Address
 428  * Registers) holds the directed and multicast addresses that we monitor.
 429  * Technically, we have 16 spots.  However, we reserve one of these spots
 430  * (RAR[15]) for our directed address used by controllers with
 431  * manageability enabled, allowing us room for 15 multicast addresses.
 432  */
 433 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
 434 #define E1000_RAL_MAC_ADDR_LEN 4
 435 #define E1000_RAH_MAC_ADDR_LEN 2
 436 #define E1000_RAH_POOL_MASK 0x03FC0000
 437 #define E1000_RAH_POOL_1 0x00040000
 438
 439 /* Error Codes */
 440 #define E1000_SUCCESS      0
 441 #define E1000_ERR_NVM      1
 442 #define E1000_ERR_PHY      2
 443 #define E1000_ERR_CONFIG   3
 444 #define E1000_ERR_PARAM    4
 445 #define E1000_ERR_MAC_INIT 5
 446 #define E1000_ERR_RESET   9
 447 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
 448 #define E1000_BLK_PHY_RESET   12
 449 #define E1000_ERR_SWFW_SYNC 13
 450 #define E1000_NOT_IMPLEMENTED 14
 451 #define E1000_ERR_MBX      15
 452 #define E1000_ERR_INVALID_ARGUMENT  16
 453 #define E1000_ERR_NO_SPACE          17
 454 #define E1000_ERR_NVM_PBA_SECTION   18
 455
 456 /* Loop limit on how long we wait for auto-negotiation to complete */
 457 #define COPPER_LINK_UP_LIMIT              10
 458 #define PHY_AUTO_NEG_LIMIT                45
 459 #define PHY_FORCE_LIMIT                   20
 460 /* Number of 100 microseconds we wait for PCI Express master disable */
 461 #define MASTER_DISABLE_TIMEOUT      800
 462 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
 463 #define PHY_CFG_TIMEOUT             100
 464 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
 465 /* Number of milliseconds for NVM auto read done after MAC reset. */
 466 #define AUTO_READ_DONE_TIMEOUT      10
 467
 468 /* Flow Control */
 469 #define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
 470
 471 #define E1000_TSYNCTXCTL_VALID    0x00000001 /* tx timestamp valid */
 472 #define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable tx timestampping */
 473
 474 #define E1000_TSYNCRXCTL_VALID      0x00000001 /* rx timestamp valid */
 475 #define E1000_TSYNCRXCTL_TYPE_MASK  0x0000000E /* rx type mask */
 476 #define E1000_TSYNCRXCTL_TYPE_L2_V2       0x00
 477 #define E1000_TSYNCRXCTL_TYPE_L4_V1       0x02
 478 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2    0x04
 479 #define E1000_TSYNCRXCTL_TYPE_ALL         0x08
 480 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2    0x0A
 481 #define E1000_TSYNCRXCTL_ENABLED    0x00000010 /* enable rx timestampping */
 482
 483 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF
 484 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE       0x00
 485 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE  0x01
 486 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02
 487 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
 488 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
 489
 490 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK               0x00000F00
 491 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE                 0x0000
 492 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE            0x0100
 493 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE       0x0200
 494 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE      0x0300
 495 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE             0x0800
 496 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE           0x0900
 497 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE  0x0A00
 498 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE             0x0B00
 499 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE           0x0C00
 500 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE           0x0D00
 501
 502 #define E1000_TIMINCA_16NS_SHIFT 24
 503
 504 #define E1000_MDICNFG_EXT_MDIO    0x80000000      /* MDI ext/int destination */
 505 #define E1000_MDICNFG_COM_MDIO    0x40000000      /* MDI shared w/ lan 0 */
 506 #define E1000_MDICNFG_PHY_MASK    0x03E00000
 507 #define E1000_MDICNFG_PHY_SHIFT   21
 508
 509 /* PCI Express Control */
 510 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
 511 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
 512 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
 513 #define E1000_GCR_CAP_VER2              0x00040000
 514
 515 /* mPHY Address Control and Data Registers */
 516 #define E1000_MPHY_ADDR_CTL          0x0024 /* mPHY Address Control Register */
 517 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
 518 #define E1000_MPHY_DATA                 0x0E10 /* mPHY Data Register */
 519
 520 /* mPHY PCS CLK Register */
 521 #define E1000_MPHY_PCS_CLK_REG_OFFSET  0x0004 /* mPHY PCS CLK AFE CSR Offset */
 522 /* mPHY Near End Digital Loopback Override Bit */
 523 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
 524
 525 /* PHY Control Register */
 526 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 527 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 528 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
 529 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 530 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
 531 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
 532 #define MII_CR_SPEED_1000       0x0040
 533 #define MII_CR_SPEED_100        0x2000
 534 #define MII_CR_SPEED_10         0x0000
 535
 536 /* PHY Status Register */
 537 #define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
 538 #define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
 539
 540 /* Autoneg Advertisement Register */
 541 #define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
 542 #define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
 543 #define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
 544 #define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
 545 #define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
 546 #define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
 547
 548 /* Link Partner Ability Register (Base Page) */
 549 #define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
 550 #define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
 551
 552 /* Autoneg Expansion Register */
 553
 554 /* 1000BASE-T Control Register */
 555 #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
 556 #define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
 557 #define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
 558                                         /* 0=Configure PHY as Slave */
 559 #define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
 560                                         /* 0=Automatic Master/Slave config */
 561
 562 /* 1000BASE-T Status Register */
 563 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
 564 #define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
 565
 566
 567 /* PHY 1000 MII Register/Bit Definitions */
 568 /* PHY Registers defined by IEEE */
 569 #define PHY_CONTROL      0x00 /* Control Register */
 570 #define PHY_STATUS       0x01 /* Status Register */
 571 #define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
 572 #define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
 573 #define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
 574 #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
 575 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
 576 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
 577
 578 /* NVM Control */
 579 #define E1000_EECD_SK        0x00000001 /* NVM Clock */
 580 #define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
 581 #define E1000_EECD_DI        0x00000004 /* NVM Data In */
 582 #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
 583 #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
 584 #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
 585 #define E1000_EECD_PRES      0x00000100 /* NVM Present */
 586 /* NVM Addressing bits based on type 0=small, 1=large */
 587 #define E1000_EECD_ADDR_BITS 0x00000400
 588 #define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
 589 #define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
 590 #define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
 591 #define E1000_EECD_SIZE_EX_SHIFT     11
 592
 593 /* Offset to data in NVM read/write registers */
 594 #define E1000_NVM_RW_REG_DATA   16
 595 #define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
 596 #define E1000_NVM_RW_REG_START  1    /* Start operation */
 597 #define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
 598 #define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
 599
 600 /* NVM Word Offsets */
 601 #define NVM_COMPAT                 0x0003
 602 #define NVM_ID_LED_SETTINGS        0x0004 /* SERDES output amplitude */
 603 #define NVM_INIT_CONTROL2_REG      0x000F
 604 #define NVM_INIT_CONTROL3_PORT_B   0x0014
 605 #define NVM_INIT_CONTROL3_PORT_A   0x0024
 606 #define NVM_ALT_MAC_ADDR_PTR       0x0037
 607 #define NVM_CHECKSUM_REG           0x003F
 608 #define NVM_COMPATIBILITY_REG_3    0x0003
 609 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
 610
 611 #define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
 612 #define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
 613 #define E1000_NVM_CFG_DONE_PORT_2  0x100000 /* ...for third port */
 614 #define E1000_NVM_CFG_DONE_PORT_3  0x200000 /* ...for fourth port */
 615
 616 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
 617
 618 /* Mask bits for fields in Word 0x24 of the NVM */
 619 #define NVM_WORD24_COM_MDIO         0x0008 /* MDIO interface shared */
 620 #define NVM_WORD24_EXT_MDIO         0x0004 /* MDIO accesses routed external */
 621
 622 /* Mask bits for fields in Word 0x0f of the NVM */
 623 #define NVM_WORD0F_PAUSE_MASK       0x3000
 624 #define NVM_WORD0F_ASM_DIR          0x2000
 625
 626 /* Mask bits for fields in Word 0x1a of the NVM */
 627
 628 /* length of string needed to store part num */
 629 #define E1000_PBANUM_LENGTH         11
 630
 631 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 632 #define NVM_SUM                    0xBABA
 633
 634 #define NVM_PBA_OFFSET_0           8
 635 #define NVM_PBA_OFFSET_1           9
 636 #define NVM_PBA_PTR_GUARD          0xFAFA
 637 #define NVM_WORD_SIZE_BASE_SHIFT   6
 638
 639 /* NVM Commands - Microwire */
 640
 641 /* NVM Commands - SPI */
 642 #define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
 643 #define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
 644 #define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
 645 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
 646 #define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
 647 #define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
 648
 649 /* SPI NVM Status Register */
 650 #define NVM_STATUS_RDY_SPI         0x01
 651
 652 /* Word definitions for ID LED Settings */
 653 #define ID_LED_RESERVED_0000 0x0000
 654 #define ID_LED_RESERVED_FFFF 0xFFFF
 655 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
 656                               (ID_LED_OFF1_OFF2 <<  8) | \
 657                               (ID_LED_DEF1_DEF2 <<  4) | \
 658                               (ID_LED_DEF1_DEF2))
 659 #define ID_LED_DEF1_DEF2     0x1
 660 #define ID_LED_DEF1_ON2      0x2
 661 #define ID_LED_DEF1_OFF2     0x3
 662 #define ID_LED_ON1_DEF2      0x4
 663 #define ID_LED_ON1_ON2       0x5
 664 #define ID_LED_ON1_OFF2      0x6
 665 #define ID_LED_OFF1_DEF2     0x7
 666 #define ID_LED_OFF1_ON2      0x8
 667 #define ID_LED_OFF1_OFF2     0x9
 668
 669 #define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
 670 #define IGP_ACTIVITY_LED_ENABLE 0x0300
 671 #define IGP_LED3_MODE           0x07000000
 672
 673 /* PCI/PCI-X/PCI-EX Config space */
 674 #define PCIE_DEVICE_CONTROL2         0x28
 675 #define PCIE_DEVICE_CONTROL2_16ms    0x0005
 676
 677 #define PHY_REVISION_MASK      0xFFFFFFF0
 678 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
 679 #define MAX_PHY_MULTI_PAGE_REG 0xF
 680
 681 /* Bit definitions for valid PHY IDs. */
 682 /*
 683  * I = Integrated
 684  * E = External
 685  */
 686 #define M88E1111_I_PHY_ID    0x01410CC0
 687 #define M88E1112_E_PHY_ID    0x01410C90
 688 #define I347AT4_E_PHY_ID     0x01410DC0
 689 #define IGP03E1000_E_PHY_ID  0x02A80390
 690 #define I82580_I_PHY_ID      0x015403A0
 691 #define I350_I_PHY_ID        0x015403B0
 692 #define M88_VENDOR           0x0141
 693
 694 /* M88E1000 Specific Registers */
 695 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
 696 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
 697 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
 698
 699 #define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
 700 #define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
 701
 702 /* M88E1000 PHY Specific Control Register */
 703 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
 704 /* 1=CLK125 low, 0=CLK125 toggling */
 705 #define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
 706                                                /* Manual MDI configuration */
 707 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
 708 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
 709 #define M88E1000_PSCR_AUTO_X_1000T     0x0040
 710 /* Auto crossover enabled all speeds */
 711 #define M88E1000_PSCR_AUTO_X_MODE      0x0060
 712 /*
 713  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
 714  * 0=Normal 10BASE-T Rx Threshold
 715  */
 716 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
 717 #define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
 718
 719 /* M88E1000 PHY Specific Status Register */
 720 #define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
 721 #define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
 722 #define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
 723 /*
 724  * 0 = <50M
 725  * 1 = 50-80M
 726  * 2 = 80-110M
 727  * 3 = 110-140M
 728  * 4 = >140M
 729  */
 730 #define M88E1000_PSSR_CABLE_LENGTH       0x0380
 731 #define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
 732 #define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
 733
 734 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 735
 736 /* M88E1000 Extended PHY Specific Control Register */
 737 /*
 738  * 1 = Lost lock detect enabled.
 739  * Will assert lost lock and bring
 740  * link down if idle not seen
 741  * within 1ms in 1000BASE-T
 742  */
 743 /*
 744  * Number of times we will attempt to autonegotiate before downshifting if we
 745  * are the master
 746  */
 747 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
 748 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
 749 /*
 750  * Number of times we will attempt to autonegotiate before downshifting if we
 751  * are the slave
 752  */
 753 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
 754 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 755 #define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
 756
 757 /* Intel i347-AT4 Registers */
 758
 759 #define I347AT4_PCDL                   0x10 /* PHY Cable Diagnostics Length */
 760 #define I347AT4_PCDC                   0x15 /* PHY Cable Diagnostics Control */
 761 #define I347AT4_PAGE_SELECT            0x16
 762
 763 /* i347-AT4 Extended PHY Specific Control Register */
 764
 765 /*
 766  *  Number of times we will attempt to autonegotiate before downshifting if we
 767  *  are the master
 768  */
 769 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
 770 #define I347AT4_PSCR_DOWNSHIFT_MASK   0x7000
 771 #define I347AT4_PSCR_DOWNSHIFT_1X     0x0000
 772 #define I347AT4_PSCR_DOWNSHIFT_2X     0x1000
 773 #define I347AT4_PSCR_DOWNSHIFT_3X     0x2000
 774 #define I347AT4_PSCR_DOWNSHIFT_4X     0x3000
 775 #define I347AT4_PSCR_DOWNSHIFT_5X     0x4000
 776 #define I347AT4_PSCR_DOWNSHIFT_6X     0x5000
 777 #define I347AT4_PSCR_DOWNSHIFT_7X     0x6000
 778 #define I347AT4_PSCR_DOWNSHIFT_8X     0x7000
 779
 780 /* i347-AT4 PHY Cable Diagnostics Control */
 781 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
 782
 783 /* Marvell 1112 only registers */
 784 #define M88E1112_VCT_DSP_DISTANCE       0x001A
 785
 786 /* M88EC018 Rev 2 specific DownShift settings */
 787 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
 788 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
 789
 790 /* MDI Control */
 791 #define E1000_MDIC_DATA_MASK 0x0000FFFF
 792 #define E1000_MDIC_REG_MASK  0x001F0000
 793 #define E1000_MDIC_REG_SHIFT 16
 794 #define E1000_MDIC_PHY_MASK  0x03E00000
 795 #define E1000_MDIC_PHY_SHIFT 21
 796 #define E1000_MDIC_OP_WRITE  0x04000000
 797 #define E1000_MDIC_OP_READ   0x08000000
 798 #define E1000_MDIC_READY     0x10000000
 799 #define E1000_MDIC_INT_EN    0x20000000
 800 #define E1000_MDIC_ERROR     0x40000000
 801 #define E1000_MDIC_DEST      0x80000000
 802
 803 /* Thermal Sensor */
 804 #define E1000_THSTAT_PWR_DOWN       0x00000001 /* Power Down Event */
 805 #define E1000_THSTAT_LINK_THROTTLE  0x00000002 /* Link Speed Throttle Event */
 806
 807 /* Energy Efficient Ethernet */
 808 #define E1000_IPCNFG_EEE_1G_AN       0x00000008  /* EEE Enable 1G AN */
 809 #define E1000_IPCNFG_EEE_100M_AN     0x00000004  /* EEE Enable 100M AN */
 810 #define E1000_EEER_TX_LPI_EN         0x00010000  /* EEE Tx LPI Enable */
 811 #define E1000_EEER_RX_LPI_EN         0x00020000  /* EEE Rx LPI Enable */
 812 #define E1000_EEER_LPI_FC            0x00040000  /* EEE Enable on FC */
 813
 814 /* SerDes Control */
 815 #define E1000_GEN_CTL_READY             0x80000000
 816 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
 817 #define E1000_GEN_POLL_TIMEOUT          640
 818
 819 #define E1000_VFTA_ENTRY_SHIFT               5
 820 #define E1000_VFTA_ENTRY_MASK                0x7F
 821 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
 822
 823 /* DMA Coalescing register fields */
 824 #define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision based
 825                                                       on DMA coal */
 826
 827 /* Tx Rate-Scheduler Config fields */
 828 #define E1000_RTTBCNRC_RS_ENA           0x80000000
 829 #define E1000_RTTBCNRC_RF_DEC_MASK      0x00003FFF
 830 #define E1000_RTTBCNRC_RF_INT_SHIFT     14
 831 #define E1000_RTTBCNRC_RF_INT_MASK      \
 832         (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
 833
 834 #endif