arch/arm/include/asm/pgtable-2level.h

   1 /*
   2  *  arch/arm/include/asm/pgtable-2level.h
   3  *
   4  *  Copyright (C) 1995-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASM_PGTABLE_2LEVEL_H
  11 #define _ASM_PGTABLE_2LEVEL_H
  12
  13 /*
  14  * Hardware-wise, we have a two level page table structure, where the first
  15  * level has 4096 entries, and the second level has 256 entries.  Each entry
  16  * is one 32-bit word.  Most of the bits in the second level entry are used
  17  * by hardware, and there aren't any "accessed" and "dirty" bits.
  18  *
  19  * Linux on the other hand has a three level page table structure, which can
  20  * be wrapped to fit a two level page table structure easily - using the PGD
  21  * and PTE only.  However, Linux also expects one "PTE" table per page, and
  22  * at least a "dirty" bit.
  23  *
  24  * Therefore, we tweak the implementation slightly - we tell Linux that we
  25  * have 2048 entries in the first level, each of which is 8 bytes (iow, two
  26  * hardware pointers to the second level.)  The second level contains two
  27  * hardware PTE tables arranged contiguously, preceded by Linux versions
  28  * which contain the state information Linux needs.  We, therefore, end up
  29  * with 512 entries in the "PTE" level.
  30  *
  31  * This leads to the page tables having the following layout:
  32  *
  33  *    pgd             pte
  34  * |        |
  35  * +--------+
  36  * |        |       +------------+ +0
  37  * +- - - - +       | Linux pt 0 |
  38  * |        |       +------------+ +1024
  39  * +--------+ +0    | Linux pt 1 |
  40  * |        |-----> +------------+ +2048
  41  * +- - - - + +4    |  h/w pt 0  |
  42  * |        |-----> +------------+ +3072
  43  * +--------+ +8    |  h/w pt 1  |
  44  * |        |       +------------+ +4096
  45  *
  46  * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
  47  * PTE_xxx for definitions of bits appearing in the "h/w pt".
  48  *
  49  * PMD_xxx definitions refer to bits in the first level page table.
  50  *
  51  * The "dirty" bit is emulated by only granting hardware write permission
  52  * iff the page is marked "writable" and "dirty" in the Linux PTE.  This
  53  * means that a write to a clean page will cause a permission fault, and
  54  * the Linux MM layer will mark the page dirty via handle_pte_fault().
  55  * For the hardware to notice the permission change, the TLB entry must
  56  * be flushed, and ptep_set_access_flags() does that for us.
  57  *
  58  * The "accessed" or "young" bit is emulated by a similar method; we only
  59  * allow accesses to the page if the "young" bit is set.  Accesses to the
  60  * page will cause a fault, and handle_pte_fault() will set the young bit
  61  * for us as long as the page is marked present in the corresponding Linux
  62  * PTE entry.  Again, ptep_set_access_flags() will ensure that the TLB is
  63  * up to date.
  64  *
  65  * However, when the "young" bit is cleared, we deny access to the page
  66  * by clearing the hardware PTE.  Currently Linux does not flush the TLB
  67  * for us in this case, which means the TLB will retain the transation
  68  * until either the TLB entry is evicted under pressure, or a context
  69  * switch which changes the user space mapping occurs.
  70  */
  71 #define PTRS_PER_PTE            512
  72 #define PTRS_PER_PMD            1
  73 #define PTRS_PER_PGD            2048
  74
  75 #define PTE_HWTABLE_PTRS        (PTRS_PER_PTE)
  76 #define PTE_HWTABLE_OFF         (PTE_HWTABLE_PTRS * sizeof(pte_t))
  77 #define PTE_HWTABLE_SIZE        (PTRS_PER_PTE * sizeof(u32))
  78
  79 /*
  80  * PMD_SHIFT determines the size of the area a second-level page table can map
  81  * PGDIR_SHIFT determines what a third-level page table entry can map
  82  */
  83 #define PMD_SHIFT               21
  84 #define PGDIR_SHIFT             21
  85
  86 #define PMD_SIZE                (1UL << PMD_SHIFT)
  87 #define PMD_MASK                (~(PMD_SIZE-1))
  88 #define PGDIR_SIZE              (1UL << PGDIR_SHIFT)
  89 #define PGDIR_MASK              (~(PGDIR_SIZE-1))
  90
  91 /*
  92  * section address mask and size definitions.
  93  */
  94 #define SECTION_SHIFT           20
  95 #define SECTION_SIZE            (1UL << SECTION_SHIFT)
  96 #define SECTION_MASK            (~(SECTION_SIZE-1))
  97
  98 /*
  99  * ARMv6 supersection address mask and size definitions.
 100  */
 101 #define SUPERSECTION_SHIFT      24
 102 #define SUPERSECTION_SIZE       (1UL << SUPERSECTION_SHIFT)
 103 #define SUPERSECTION_MASK       (~(SUPERSECTION_SIZE-1))
 104
 105 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
 106
 107 /*
 108  * "Linux" PTE definitions.
 109  *
 110  * We keep two sets of PTEs - the hardware and the linux version.
 111  * This allows greater flexibility in the way we map the Linux bits
 112  * onto the hardware tables, and allows us to have YOUNG and DIRTY
 113  * bits.
 114  *
 115  * The PTE table pointer refers to the hardware entries; the "Linux"
 116  * entries are stored 1024 bytes below.
 117  */
 118 #define L_PTE_PRESENT           (_AT(pteval_t, 1) << 0)
 119 #define L_PTE_YOUNG             (_AT(pteval_t, 1) << 1)
 120 #define L_PTE_FILE              (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
 121 #define L_PTE_DIRTY             (_AT(pteval_t, 1) << 6)
 122 #define L_PTE_RDONLY            (_AT(pteval_t, 1) << 7)
 123 #define L_PTE_USER              (_AT(pteval_t, 1) << 8)
 124 #define L_PTE_XN                (_AT(pteval_t, 1) << 9)
 125 #define L_PTE_SHARED            (_AT(pteval_t, 1) << 10)        /* shared(v6), coherent(xsc3) */
 126
 127 /*
 128  * These are the memory types, defined to be compatible with
 129  * pre-ARMv6 CPUs cacheable and bufferable bits:   XXCB
 130  */
 131 #define L_PTE_MT_UNCACHED       (_AT(pteval_t, 0x00) << 2)      /* 0000 */
 132 #define L_PTE_MT_BUFFERABLE     (_AT(pteval_t, 0x01) << 2)      /* 0001 */
 133 #define L_PTE_MT_WRITETHROUGH   (_AT(pteval_t, 0x02) << 2)      /* 0010 */
 134 #define L_PTE_MT_WRITEBACK      (_AT(pteval_t, 0x03) << 2)      /* 0011 */
 135 #define L_PTE_MT_MINICACHE      (_AT(pteval_t, 0x06) << 2)      /* 0110 (sa1100, xscale) */
 136 #define L_PTE_MT_WRITEALLOC     (_AT(pteval_t, 0x07) << 2)      /* 0111 */
 137 #define L_PTE_MT_DEV_SHARED     (_AT(pteval_t, 0x04) << 2)      /* 0100 */
 138 #define L_PTE_MT_DEV_NONSHARED  (_AT(pteval_t, 0x0c) << 2)      /* 1100 */
 139 #define L_PTE_MT_DEV_WC         (_AT(pteval_t, 0x09) << 2)      /* 1001 */
 140 #define L_PTE_MT_DEV_CACHED     (_AT(pteval_t, 0x0b) << 2)      /* 1011 */
 141 #define L_PTE_MT_MASK           (_AT(pteval_t, 0x0f) << 2)
 142
 143 #endif /* _ASM_PGTABLE_2LEVEL_H */