Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / arch / arm / mach-mx5 / mm.c
blobbaea6e5cddd96f782009daaebe72062557cb1b20
1 /*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
11 * Create static mapping between physical to virtual memory.
14 #include <linux/mm.h>
15 #include <linux/init.h>
17 #include <asm/mach/map.h>
19 #include <mach/hardware.h>
20 #include <mach/common.h>
21 #include <mach/devices-common.h>
22 #include <mach/iomux-v3.h>
25 * Define the MX51 memory map.
27 static struct map_desc mx51_io_desc[] __initdata = {
28 imx_map_entry(MX51, IRAM, MT_DEVICE),
29 imx_map_entry(MX51, DEBUG, MT_DEVICE),
30 imx_map_entry(MX51, AIPS1, MT_DEVICE),
31 imx_map_entry(MX51, SPBA0, MT_DEVICE),
32 imx_map_entry(MX51, AIPS2, MT_DEVICE),
36 * Define the MX53 memory map.
38 static struct map_desc mx53_io_desc[] __initdata = {
39 imx_map_entry(MX53, AIPS1, MT_DEVICE),
40 imx_map_entry(MX53, SPBA0, MT_DEVICE),
41 imx_map_entry(MX53, AIPS2, MT_DEVICE),
45 * This function initializes the memory map. It is called during the
46 * system startup to create static physical to virtual memory mappings
47 * for the IO modules.
49 void __init mx51_map_io(void)
51 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
54 void __init imx51_init_early(void)
56 mxc_set_cpu_type(MXC_CPU_MX51);
57 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
58 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
61 void __init mx53_map_io(void)
63 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
66 void __init imx53_init_early(void)
68 mxc_set_cpu_type(MXC_CPU_MX53);
69 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
70 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
73 void __init mx51_init_irq(void)
75 unsigned long tzic_addr;
76 void __iomem *tzic_virt;
78 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
79 tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
80 else
81 tzic_addr = MX51_TZIC_BASE_ADDR;
83 tzic_virt = ioremap(tzic_addr, SZ_16K);
84 if (!tzic_virt)
85 panic("unable to map TZIC interrupt controller\n");
87 tzic_init_irq(tzic_virt);
90 void __init mx53_init_irq(void)
92 unsigned long tzic_addr;
93 void __iomem *tzic_virt;
95 tzic_addr = MX53_TZIC_BASE_ADDR;
97 tzic_virt = ioremap(tzic_addr, SZ_16K);
98 if (!tzic_virt)
99 panic("unable to map TZIC interrupt controller\n");
101 tzic_init_irq(tzic_virt);
104 static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
105 .ap_2_ap_addr = 642,
106 .uart_2_mcu_addr = 817,
107 .mcu_2_app_addr = 747,
108 .mcu_2_shp_addr = 961,
109 .ata_2_mcu_addr = 1473,
110 .mcu_2_ata_addr = 1392,
111 .app_2_per_addr = 1033,
112 .app_2_mcu_addr = 683,
113 .shp_2_per_addr = 1251,
114 .shp_2_mcu_addr = 892,
117 static struct sdma_platform_data imx51_sdma_pdata __initdata = {
118 .fw_name = "sdma-imx51.bin",
119 .script_addrs = &imx51_sdma_script,
122 static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
123 .ap_2_ap_addr = 642,
124 .app_2_mcu_addr = 683,
125 .mcu_2_app_addr = 747,
126 .uart_2_mcu_addr = 817,
127 .shp_2_mcu_addr = 891,
128 .mcu_2_shp_addr = 960,
129 .uartsh_2_mcu_addr = 1032,
130 .spdif_2_mcu_addr = 1100,
131 .mcu_2_spdif_addr = 1134,
132 .firi_2_mcu_addr = 1193,
133 .mcu_2_firi_addr = 1290,
136 static struct sdma_platform_data imx53_sdma_pdata __initdata = {
137 .fw_name = "sdma-imx53.bin",
138 .script_addrs = &imx53_sdma_script,
141 void __init imx51_soc_init(void)
143 /* i.mx51 has the i.mx31 type gpio */
144 mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
145 mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
146 mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
147 mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
149 /* i.mx51 has the i.mx35 type sdma */
150 imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
153 void __init imx53_soc_init(void)
155 /* i.mx53 has the i.mx31 type gpio */
156 mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
157 mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
158 mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
159 mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
160 mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
161 mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
162 mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
164 /* i.mx53 has the i.mx35 type sdma */
165 imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);