| blob | 75d86118b76a2c524cea92c7320d25bb7d4225a5 |
1 /*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
19 #ifndef __MACH_MX28_H__
20 #define __MACH_MX28_H__
22 #include <mach/mxs.h>
24 /*
25 * OCRAM
26 */
27 #define MX28_OCRAM_BASE_ADDR 0x00000000
28 #define MX28_OCRAM_SIZE SZ_128K
30 /*
31 * IO
32 */
33 #define MX28_IO_BASE_ADDR 0x80000000
34 #define MX28_IO_SIZE SZ_1M
36 #define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000)
37 #define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000)
38 #define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000)
39 #define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000)
40 #define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000)
41 #define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000)
42 #define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000)
43 #define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000)
44 #define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000)
45 #define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000)
46 #define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000)
47 #define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000)
48 #define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000)
49 #define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000)
50 #define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000)
51 #define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000)
52 #define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000)
53 #define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000)
54 #define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000)
55 #define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000)
56 #define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000)
57 #define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000)
58 #define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200)
59 #define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300)
60 #define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400)
61 #define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500)
62 #define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700)
63 #define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800)
64 #define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000)
65 #define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000)
66 #define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000)
67 #define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000)
68 #define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000)
69 #define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000)
70 #define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000)
71 #define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000)
72 #define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000)
73 #define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000)
74 #define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000)
75 #define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000)
76 #define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000)
77 #define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000)
78 #define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000)
79 #define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000)
80 #define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000)
81 #define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000)
82 #define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000)
83 #define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000)
84 #define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000)
85 #define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000)
86 #define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000)
87 #define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000)
88 #define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000)
90 #define MX28_IO_P2V(x) MXS_IO_P2V(x)
91 #define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x))
93 /*
94 * IRQ
95 */
96 #define MX28_INT_BATT_BRNOUT 0
97 #define MX28_INT_VDDD_BRNOUT 1
98 #define MX28_INT_VDDIO_BRNOUT 2
99 #define MX28_INT_VDDA_BRNOUT 3
100 #define MX28_INT_VDD5V_DROOP 4
101 #define MX28_INT_DCDC4P2_BRNOUT 5
102 #define MX28_INT_VDD5V 6
103 #define MX28_INT_CAN0 8
104 #define MX28_INT_CAN1 9
105 #define MX28_INT_LRADC_TOUCH 10
106 #define MX28_INT_HSADC 13
107 #define MX28_INT_IRADC_THRESH0 14
108 #define MX28_INT_IRADC_THRESH1 15
109 #define MX28_INT_LRADC_CH0 16
110 #define MX28_INT_LRADC_CH1 17
111 #define MX28_INT_LRADC_CH2 18
112 #define MX28_INT_LRADC_CH3 19
113 #define MX28_INT_LRADC_CH4 20
114 #define MX28_INT_LRADC_CH5 21
115 #define MX28_INT_LRADC_CH6 22
116 #define MX28_INT_LRADC_CH7 23
117 #define MX28_INT_LRADC_BUTTON0 24
118 #define MX28_INT_LRADC_BUTTON1 25
119 #define MX28_INT_PERFMON 27
120 #define MX28_INT_RTC_1MSEC 28
121 #define MX28_INT_RTC_ALARM 29
122 #define MX28_INT_COMMS 31
123 #define MX28_INT_EMI_ERR 32
124 #define MX28_INT_LCDIF 38
125 #define MX28_INT_PXP 39
126 #define MX28_INT_BCH 41
127 #define MX28_INT_GPMI 42
128 #define MX28_INT_SPDIF_ERROR 45
129 #define MX28_INT_DUART 47
130 #define MX28_INT_TIMER0 48
131 #define MX28_INT_TIMER1 49
132 #define MX28_INT_TIMER2 50
133 #define MX28_INT_TIMER3 51
134 #define MX28_INT_DCP_VMI 52
135 #define MX28_INT_DCP 53
136 #define MX28_INT_DCP_SECURE 54
137 #define MX28_INT_SAIF1 58
138 #define MX28_INT_SAIF0 59
139 #define MX28_INT_SPDIF_DMA 66
140 #define MX28_INT_I2C0_DMA 68
141 #define MX28_INT_I2C1_DMA 69
142 #define MX28_INT_AUART0_RX_DMA 70
143 #define MX28_INT_AUART0_TX_DMA 71
144 #define MX28_INT_AUART1_RX_DMA 72
145 #define MX28_INT_AUART1_TX_DMA 73
146 #define MX28_INT_AUART2_RX_DMA 74
147 #define MX28_INT_AUART2_TX_DMA 75
148 #define MX28_INT_AUART3_RX_DMA 76
149 #define MX28_INT_AUART3_TX_DMA 77
150 #define MX28_INT_AUART4_RX_DMA 78
151 #define MX28_INT_AUART4_TX_DMA 79
152 #define MX28_INT_SAIF0_DMA 80
153 #define MX28_INT_SAIF1_DMA 81
154 #define MX28_INT_SSP0_DMA 82
155 #define MX28_INT_SSP1_DMA 83
156 #define MX28_INT_SSP2_DMA 84
157 #define MX28_INT_SSP3_DMA 85
158 #define MX28_INT_LCDIF_DMA 86
159 #define MX28_INT_HSADC_DMA 87
160 #define MX28_INT_GPMI_DMA 88
161 #define MX28_INT_DIGCTL_DEBUG_TRAP 89
162 #define MX28_INT_USB1 92
163 #define MX28_INT_USB0 93
164 #define MX28_INT_USB1_WAKEUP 94
165 #define MX28_INT_USB0_WAKEUP 95
166 #define MX28_INT_SSP0_ERROR 96
167 #define MX28_INT_SSP1_ERROR 97
168 #define MX28_INT_SSP2_ERROR 98
169 #define MX28_INT_SSP3_ERROR 99
170 #define MX28_INT_ENET_SWI 100
171 #define MX28_INT_ENET_MAC0 101
172 #define MX28_INT_ENET_MAC1 102
173 #define MX28_INT_ENET_MAC0_1588 103
174 #define MX28_INT_ENET_MAC1_1588 104
175 #define MX28_INT_I2C1_ERROR 110
176 #define MX28_INT_I2C0_ERROR 111
177 #define MX28_INT_AUART0 112
178 #define MX28_INT_AUART1 113
179 #define MX28_INT_AUART2 114
180 #define MX28_INT_AUART3 115
181 #define MX28_INT_AUART4 116
182 #define MX28_INT_GPIO4 123
183 #define MX28_INT_GPIO3 124
184 #define MX28_INT_GPIO2 125
185 #define MX28_INT_GPIO1 126
186 #define MX28_INT_GPIO0 127
188 /*
189 * APBH DMA
190 */
191 #define MX28_DMA_SSP0 0
192 #define MX28_DMA_SSP1 1
193 #define MX28_DMA_SSP2 2
194 #define MX28_DMA_SSP3 3
195 #define MX28_DMA_GPMI0 4
196 #define MX28_DMA_GPMI1 5
197 #define MX28_DMA_GPMI2 6
198 #define MX28_DMA_GPMI3 7
199 #define MX28_DMA_GPMI4 8
200 #define MX28_DMA_GPMI5 9
201 #define MX28_DMA_GPMI6 10
202 #define MX28_DMA_GPMI7 11
203 #define MX28_DMA_HSADC 12
204 #define MX28_DMA_LCDIF 13
206 /*
207 * APBX DMA
208 */
209 #define MX28_DMA_AUART4_RX 0
210 #define MX28_DMA_AUART4_TX 1
211 #define MX28_DMA_SPDIF_TX 2
212 #define MX28_DMA_SAIF0 4
213 #define MX28_DMA_SAIF1 5
214 #define MX28_DMA_I2C0 6
215 #define MX28_DMA_I2C1 7
216 #define MX28_DMA_AUART0_RX 8
217 #define MX28_DMA_AUART0_TX 9
218 #define MX28_DMA_AUART1_RX 10
219 #define MX28_DMA_AUART1_TX 11
220 #define MX28_DMA_AUART2_RX 12
221 #define MX28_DMA_AUART2_TX 13
222 #define MX28_DMA_AUART3_RX 14
223 #define MX28_DMA_AUART3_TX 15