arch/arm/plat-nomadik/include/plat/ste_dma40.h

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2007-2010
   3  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
   4  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8
   9 #ifndef STE_DMA40_H
  10 #define STE_DMA40_H
  11
  12 #include <linux/dmaengine.h>
  13 #include <linux/scatterlist.h>
  14 #include <linux/workqueue.h>
  15 #include <linux/interrupt.h>
  16
  17 /*
  18  * Maxium size for a single dma descriptor
  19  * Size is limited to 16 bits.
  20  * Size is in the units of addr-widths (1,2,4,8 bytes)
  21  * Larger transfers will be split up to multiple linked desc
  22  */
  23 #define STEDMA40_MAX_SEG_SIZE 0xFFFF
  24
  25 /* dev types for memcpy */
  26 #define STEDMA40_DEV_DST_MEMORY (-1)
  27 #define STEDMA40_DEV_SRC_MEMORY (-1)
  28
  29 enum stedma40_mode {
  30         STEDMA40_MODE_LOGICAL = 0,
  31         STEDMA40_MODE_PHYSICAL,
  32         STEDMA40_MODE_OPERATION,
  33 };
  34
  35 enum stedma40_mode_opt {
  36         STEDMA40_PCHAN_BASIC_MODE = 0,
  37         STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
  38         STEDMA40_PCHAN_MODULO_MODE,
  39         STEDMA40_PCHAN_DOUBLE_DST_MODE,
  40         STEDMA40_LCHAN_SRC_PHY_DST_LOG,
  41         STEDMA40_LCHAN_SRC_LOG_DST_PHY,
  42 };
  43
  44 #define STEDMA40_ESIZE_8_BIT  0x0
  45 #define STEDMA40_ESIZE_16_BIT 0x1
  46 #define STEDMA40_ESIZE_32_BIT 0x2
  47 #define STEDMA40_ESIZE_64_BIT 0x3
  48
  49 /* The value 4 indicates that PEN-reg shall be set to 0 */
  50 #define STEDMA40_PSIZE_PHY_1  0x4
  51 #define STEDMA40_PSIZE_PHY_2  0x0
  52 #define STEDMA40_PSIZE_PHY_4  0x1
  53 #define STEDMA40_PSIZE_PHY_8  0x2
  54 #define STEDMA40_PSIZE_PHY_16 0x3
  55
  56 /*
  57  * The number of elements differ in logical and
  58  * physical mode
  59  */
  60 #define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
  61 #define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
  62 #define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
  63 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
  64
  65 /* Maximum number of possible physical channels */
  66 #define STEDMA40_MAX_PHYS 32
  67
  68 enum stedma40_flow_ctrl {
  69         STEDMA40_NO_FLOW_CTRL,
  70         STEDMA40_FLOW_CTRL,
  71 };
  72
  73 enum stedma40_periph_data_width {
  74         STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
  75         STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
  76         STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
  77         STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
  78 };
  79
  80 enum stedma40_xfer_dir {
  81         STEDMA40_MEM_TO_MEM = 1,
  82         STEDMA40_MEM_TO_PERIPH,
  83         STEDMA40_PERIPH_TO_MEM,
  84         STEDMA40_PERIPH_TO_PERIPH
  85 };
  86
  87
  88 /**
  89  * struct stedma40_chan_cfg - dst/src channel configuration
  90  *
  91  * @big_endian: true if the src/dst should be read as big endian
  92  * @data_width: Data width of the src/dst hardware
  93  * @p_size: Burst size
  94  * @flow_ctrl: Flow control on/off.
  95  */
  96 struct stedma40_half_channel_info {
  97         bool big_endian;
  98         enum stedma40_periph_data_width data_width;
  99         int psize;
 100         enum stedma40_flow_ctrl flow_ctrl;
 101 };
 102
 103 /**
 104  * struct stedma40_chan_cfg - Structure to be filled by client drivers.
 105  *
 106  * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
 107  * @high_priority: true if high-priority
 108  * @realtime: true if realtime mode is to be enabled.  Only available on DMA40
 109  * version 3+, i.e DB8500v2+
 110  * @mode: channel mode: physical, logical, or operation
 111  * @mode_opt: options for the chosen channel mode
 112  * @src_dev_type: Src device type
 113  * @dst_dev_type: Dst device type
 114  * @src_info: Parameters for dst half channel
 115  * @dst_info: Parameters for dst half channel
 116  *
 117  *
 118  * This structure has to be filled by the client drivers.
 119  * It is recommended to do all dma configurations for clients in the machine.
 120  *
 121  */
 122 struct stedma40_chan_cfg {
 123         enum stedma40_xfer_dir                   dir;
 124         bool                                     high_priority;
 125         bool                                     realtime;
 126         enum stedma40_mode                       mode;
 127         enum stedma40_mode_opt                   mode_opt;
 128         int                                      src_dev_type;
 129         int                                      dst_dev_type;
 130         struct stedma40_half_channel_info        src_info;
 131         struct stedma40_half_channel_info        dst_info;
 132 };
 133
 134 /**
 135  * struct stedma40_platform_data - Configuration struct for the dma device.
 136  *
 137  * @dev_len: length of dev_tx and dev_rx
 138  * @dev_tx: mapping between destination event line and io address
 139  * @dev_rx: mapping between source event line and io address
 140  * @memcpy: list of memcpy event lines
 141  * @memcpy_len: length of memcpy
 142  * @memcpy_conf_phy: default configuration of physical channel memcpy
 143  * @memcpy_conf_log: default configuration of logical channel memcpy
 144  * @disabled_channels: A vector, ending with -1, that marks physical channels
 145  * that are for different reasons not available for the driver.
 146  */
 147 struct stedma40_platform_data {
 148         u32                              dev_len;
 149         const dma_addr_t                *dev_tx;
 150         const dma_addr_t                *dev_rx;
 151         int                             *memcpy;
 152         u32                              memcpy_len;
 153         struct stedma40_chan_cfg        *memcpy_conf_phy;
 154         struct stedma40_chan_cfg        *memcpy_conf_log;
 155         int                              disabled_channels[STEDMA40_MAX_PHYS];
 156 };
 157
 158 #ifdef CONFIG_STE_DMA40
 159
 160 /**
 161  * stedma40_filter() - Provides stedma40_chan_cfg to the
 162  * ste_dma40 dma driver via the dmaengine framework.
 163  * does some checking of what's provided.
 164  *
 165  * Never directly called by client. It used by dmaengine.
 166  * @chan: dmaengine handle.
 167  * @data: Must be of type: struct stedma40_chan_cfg and is
 168  * the configuration of the framework.
 169  *
 170  *
 171  */
 172
 173 bool stedma40_filter(struct dma_chan *chan, void *data);
 174
 175 /**
 176  * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
 177  * (=device)
 178  *
 179  * @chan: dmaengine handle
 180  * @addr: source or destination physicall address.
 181  * @size: bytes to transfer
 182  * @direction: direction of transfer
 183  * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 184  */
 185
 186 static inline struct
 187 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
 188                                             dma_addr_t addr,
 189                                             unsigned int size,
 190                                             enum dma_data_direction direction,
 191                                             unsigned long flags)
 192 {
 193         struct scatterlist sg;
 194         sg_init_table(&sg, 1);
 195         sg.dma_address = addr;
 196         sg.length = size;
 197
 198         return chan->device->device_prep_slave_sg(chan, &sg, 1,
 199                                                   direction, flags);
 200 }
 201
 202 #else
 203 static inline bool stedma40_filter(struct dma_chan *chan, void *data)
 204 {
 205         return false;
 206 }
 207
 208 static inline struct
 209 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
 210                                             dma_addr_t addr,
 211                                             unsigned int size,
 212                                             enum dma_data_direction direction,
 213                                             unsigned long flags)
 214 {
 215         return NULL;
 216 }
 217 #endif
 218
 219 #endif