arch/arm/plat-omap/include/plat/dma.h

   1 /*
   2  *  arch/arm/plat-omap/include/mach/dma.h
   3  *
   4  *  Copyright (C) 2003 Nokia Corporation
   5  *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20  */
  21 #ifndef __ASM_ARCH_DMA_H
  22 #define __ASM_ARCH_DMA_H
  23
  24 #include <linux/platform_device.h>
  25
  26 /*
  27  * TODO: These dma channel defines should go away once all
  28  * the omap drivers hwmod adapted.
  29  */
  30
  31 /* Move omap4 specific defines to dma-44xx.h */
  32 #include "dma-44xx.h"
  33
  34 /* DMA channels for omap1 */
  35 #define OMAP_DMA_NO_DEVICE              0
  36 #define OMAP_DMA_MCSI1_TX               1
  37 #define OMAP_DMA_MCSI1_RX               2
  38 #define OMAP_DMA_I2C_RX                 3
  39 #define OMAP_DMA_I2C_TX                 4
  40 #define OMAP_DMA_EXT_NDMA_REQ           5
  41 #define OMAP_DMA_EXT_NDMA_REQ2          6
  42 #define OMAP_DMA_UWIRE_TX               7
  43 #define OMAP_DMA_MCBSP1_TX              8
  44 #define OMAP_DMA_MCBSP1_RX              9
  45 #define OMAP_DMA_MCBSP3_TX              10
  46 #define OMAP_DMA_MCBSP3_RX              11
  47 #define OMAP_DMA_UART1_TX               12
  48 #define OMAP_DMA_UART1_RX               13
  49 #define OMAP_DMA_UART2_TX               14
  50 #define OMAP_DMA_UART2_RX               15
  51 #define OMAP_DMA_MCBSP2_TX              16
  52 #define OMAP_DMA_MCBSP2_RX              17
  53 #define OMAP_DMA_UART3_TX               18
  54 #define OMAP_DMA_UART3_RX               19
  55 #define OMAP_DMA_CAMERA_IF_RX           20
  56 #define OMAP_DMA_MMC_TX                 21
  57 #define OMAP_DMA_MMC_RX                 22
  58 #define OMAP_DMA_NAND                   23
  59 #define OMAP_DMA_IRQ_LCD_LINE           24
  60 #define OMAP_DMA_MEMORY_STICK           25
  61 #define OMAP_DMA_USB_W2FC_RX0           26
  62 #define OMAP_DMA_USB_W2FC_RX1           27
  63 #define OMAP_DMA_USB_W2FC_RX2           28
  64 #define OMAP_DMA_USB_W2FC_TX0           29
  65 #define OMAP_DMA_USB_W2FC_TX1           30
  66 #define OMAP_DMA_USB_W2FC_TX2           31
  67
  68 /* These are only for 1610 */
  69 #define OMAP_DMA_CRYPTO_DES_IN          32
  70 #define OMAP_DMA_SPI_TX                 33
  71 #define OMAP_DMA_SPI_RX                 34
  72 #define OMAP_DMA_CRYPTO_HASH            35
  73 #define OMAP_DMA_CCP_ATTN               36
  74 #define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
  75 #define OMAP_DMA_CMT_APE_TX_CHAN_0      38
  76 #define OMAP_DMA_CMT_APE_RV_CHAN_0      39
  77 #define OMAP_DMA_CMT_APE_TX_CHAN_1      40
  78 #define OMAP_DMA_CMT_APE_RV_CHAN_1      41
  79 #define OMAP_DMA_CMT_APE_TX_CHAN_2      42
  80 #define OMAP_DMA_CMT_APE_RV_CHAN_2      43
  81 #define OMAP_DMA_CMT_APE_TX_CHAN_3      44
  82 #define OMAP_DMA_CMT_APE_RV_CHAN_3      45
  83 #define OMAP_DMA_CMT_APE_TX_CHAN_4      46
  84 #define OMAP_DMA_CMT_APE_RV_CHAN_4      47
  85 #define OMAP_DMA_CMT_APE_TX_CHAN_5      48
  86 #define OMAP_DMA_CMT_APE_RV_CHAN_5      49
  87 #define OMAP_DMA_CMT_APE_TX_CHAN_6      50
  88 #define OMAP_DMA_CMT_APE_RV_CHAN_6      51
  89 #define OMAP_DMA_CMT_APE_TX_CHAN_7      52
  90 #define OMAP_DMA_CMT_APE_RV_CHAN_7      53
  91 #define OMAP_DMA_MMC2_TX                54
  92 #define OMAP_DMA_MMC2_RX                55
  93 #define OMAP_DMA_CRYPTO_DES_OUT         56
  94
  95 /* DMA channels for 24xx */
  96 #define OMAP24XX_DMA_NO_DEVICE          0
  97 #define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
  98 #define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
  99 #define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
 100 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
 101 #define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
 102 #define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
 103 #define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
 104 #define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
 105 #define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
 106 #define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
 107 #define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
 108 #define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
 109 #define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
 110 #define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
 111 #define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
 112 #define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
 113 #define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
 114 #define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
 115 #define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
 116 #define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
 117 #define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
 118 #define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
 119 #define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
 120 #define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
 121 #define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
 122 #define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
 123 #define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
 124 #define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
 125 #define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
 126 #define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
 127 #define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
 128 #define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
 129 #define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
 130 #define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
 131 #define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
 132 #define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
 133 #define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
 134 #define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
 135 #define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
 136 #define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
 137 #define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
 138 #define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
 139 #define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
 140 #define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 141 #define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 142 #define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 143 #define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
 144 #define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
 145 #define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
 146 #define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
 147 #define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
 148 #define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
 149 #define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
 150 #define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
 151 #define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
 152 #define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
 153 #define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
 154 #define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
 155 #define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
 156 #define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
 157 #define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
 158 #define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
 159 #define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
 160 #define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
 161 #define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
 162 #define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
 163 #define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
 164 #define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
 165 #define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
 166 #define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
 167 #define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
 168 #define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
 169 #define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
 170 #define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
 171 #define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
 172 #define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
 173 #define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
 174 #define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
 175 #define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
 176 #define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
 177 #define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
 178 #define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
 179 #define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
 180 #define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
 181 #define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
 182 #define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
 183 #define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
 184 #define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
 185 #define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
 186 #define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
 187 #define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
 188 #define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
 189 #define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
 190 #define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
 191 #define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
 192 #define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
 193 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 194 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 195
 196 #define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
 197 #define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
 198
 199 /* Only for AM35xx */
 200 #define AM35XX_DMA_UART4_TX             54
 201 #define AM35XX_DMA_UART4_RX             55
 202
 203 /*----------------------------------------------------------------------------*/
 204
 205 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 206 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 207 #define OMAP_DMA_HALF_IRQ               (1 << 2)
 208 #define OMAP_DMA_FRAME_IRQ              (1 << 3)
 209 #define OMAP_DMA_LAST_IRQ               (1 << 4)
 210 #define OMAP_DMA_BLOCK_IRQ              (1 << 5)
 211 #define OMAP1_DMA_SYNC_IRQ              (1 << 6)
 212 #define OMAP2_DMA_PKT_IRQ               (1 << 7)
 213 #define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
 214 #define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
 215 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
 216 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 217
 218 #define OMAP_DMA_CCR_EN                 (1 << 7)
 219 #define OMAP_DMA_CCR_RD_ACTIVE          (1 << 9)
 220 #define OMAP_DMA_CCR_WR_ACTIVE          (1 << 10)
 221 #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC   (1 << 24)
 222 #define OMAP_DMA_CCR_BUFFERING_DISABLE  (1 << 25)
 223
 224 #define OMAP_DMA_DATA_TYPE_S8           0x00
 225 #define OMAP_DMA_DATA_TYPE_S16          0x01
 226 #define OMAP_DMA_DATA_TYPE_S32          0x02
 227
 228 #define OMAP_DMA_SYNC_ELEMENT           0x00
 229 #define OMAP_DMA_SYNC_FRAME             0x01
 230 #define OMAP_DMA_SYNC_BLOCK             0x02
 231 #define OMAP_DMA_SYNC_PACKET            0x03
 232
 233 #define OMAP_DMA_DST_SYNC_PREFETCH      0x02
 234 #define OMAP_DMA_SRC_SYNC               0x01
 235 #define OMAP_DMA_DST_SYNC               0x00
 236
 237 #define OMAP_DMA_PORT_EMIFF             0x00
 238 #define OMAP_DMA_PORT_EMIFS             0x01
 239 #define OMAP_DMA_PORT_OCP_T1            0x02
 240 #define OMAP_DMA_PORT_TIPB              0x03
 241 #define OMAP_DMA_PORT_OCP_T2            0x04
 242 #define OMAP_DMA_PORT_MPUI              0x05
 243
 244 #define OMAP_DMA_AMODE_CONSTANT         0x00
 245 #define OMAP_DMA_AMODE_POST_INC         0x01
 246 #define OMAP_DMA_AMODE_SINGLE_IDX       0x02
 247 #define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
 248
 249 #define DMA_DEFAULT_FIFO_DEPTH          0x10
 250 #define DMA_DEFAULT_ARB_RATE            0x01
 251 /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
 252 #define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
 253 #define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
 254 #define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
 255 #define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
 256 #define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
 257 #define DMA_THREAD_FIFO_75              (0x01 << 14)
 258 #define DMA_THREAD_FIFO_25              (0x02 << 14)
 259 #define DMA_THREAD_FIFO_50              (0x03 << 14)
 260
 261 /* DMA4_OCP_SYSCONFIG bits */
 262 #define DMA_SYSCONFIG_MIDLEMODE_MASK            (3 << 12)
 263 #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK        (3 << 8)
 264 #define DMA_SYSCONFIG_EMUFREE                   (1 << 5)
 265 #define DMA_SYSCONFIG_SIDLEMODE_MASK            (3 << 3)
 266 #define DMA_SYSCONFIG_SOFTRESET                 (1 << 2)
 267 #define DMA_SYSCONFIG_AUTOIDLE                  (1 << 0)
 268
 269 #define DMA_SYSCONFIG_MIDLEMODE(n)              ((n) << 12)
 270 #define DMA_SYSCONFIG_SIDLEMODE(n)              ((n) << 3)
 271
 272 #define DMA_IDLEMODE_SMARTIDLE                  0x2
 273 #define DMA_IDLEMODE_NO_IDLE                    0x1
 274 #define DMA_IDLEMODE_FORCE_IDLE                 0x0
 275
 276 /* Chaining modes*/
 277 #ifndef CONFIG_ARCH_OMAP1
 278 #define OMAP_DMA_STATIC_CHAIN           0x1
 279 #define OMAP_DMA_DYNAMIC_CHAIN          0x2
 280 #define OMAP_DMA_CHAIN_ACTIVE           0x1
 281 #define OMAP_DMA_CHAIN_INACTIVE         0x0
 282 #endif
 283
 284 #define DMA_CH_PRIO_HIGH                0x1
 285 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
 286
 287 /* Errata handling */
 288 #define IS_DMA_ERRATA(id)               (errata & (id))
 289 #define SET_DMA_ERRATA(id)              (errata |= (id))
 290
 291 #define DMA_ERRATA_IFRAME_BUFFERING     BIT(0x0)
 292 #define DMA_ERRATA_PARALLEL_CHANNELS    BIT(0x1)
 293 #define DMA_ERRATA_i378                 BIT(0x2)
 294 #define DMA_ERRATA_i541                 BIT(0x3)
 295 #define DMA_ERRATA_i88                  BIT(0x4)
 296 #define DMA_ERRATA_3_3                  BIT(0x5)
 297 #define DMA_ROMCODE_BUG                 BIT(0x6)
 298
 299 /* Attributes for OMAP DMA Contrller */
 300 #define DMA_LINKED_LCH                  BIT(0x0)
 301 #define GLOBAL_PRIORITY                 BIT(0x1)
 302 #define RESERVE_CHANNEL                 BIT(0x2)
 303 #define IS_CSSA_32                      BIT(0x3)
 304 #define IS_CDSA_32                      BIT(0x4)
 305 #define IS_RW_PRIORITY                  BIT(0x5)
 306 #define ENABLE_1510_MODE                BIT(0x6)
 307 #define SRC_PORT                        BIT(0x7)
 308 #define DST_PORT                        BIT(0x8)
 309 #define SRC_INDEX                       BIT(0x9)
 310 #define DST_INDEX                       BIT(0xA)
 311 #define IS_BURST_ONLY4                  BIT(0xB)
 312 #define CLEAR_CSR_ON_READ               BIT(0xC)
 313 #define IS_WORD_16                      BIT(0xD)
 314
 315 enum omap_reg_offsets {
 316
 317 GCR,            GSCR,           GRST1,          HW_ID,
 318 PCH2_ID,        PCH0_ID,        PCH1_ID,        PCHG_ID,
 319 PCHD_ID,        CAPS_0,         CAPS_1,         CAPS_2,
 320 CAPS_3,         CAPS_4,         PCH2_SR,        PCH0_SR,
 321 PCH1_SR,        PCHD_SR,        REVISION,       IRQSTATUS_L0,
 322 IRQSTATUS_L1,   IRQSTATUS_L2,   IRQSTATUS_L3,   IRQENABLE_L0,
 323 IRQENABLE_L1,   IRQENABLE_L2,   IRQENABLE_L3,   SYSSTATUS,
 324 OCP_SYSCONFIG,
 325
 326 /* omap1+ specific */
 327 CPC, CCR2, LCH_CTRL,
 328
 329 /* Common registers for all omap's */
 330 CSDP,           CCR,            CICR,           CSR,
 331 CEN,            CFN,            CSFI,           CSEI,
 332 CSAC,           CDAC,           CDEI,
 333 CDFI,           CLNK_CTRL,
 334
 335 /* Channel specific registers */
 336 CSSA,           CDSA,           COLOR,
 337 CCEN,           CCFN,
 338
 339 /* omap3630 and omap4 specific */
 340 CDP,            CNDP,           CCDN,
 341
 342 };
 343
 344 enum omap_dma_burst_mode {
 345         OMAP_DMA_DATA_BURST_DIS = 0,
 346         OMAP_DMA_DATA_BURST_4,
 347         OMAP_DMA_DATA_BURST_8,
 348         OMAP_DMA_DATA_BURST_16,
 349 };
 350
 351 enum end_type {
 352         OMAP_DMA_LITTLE_ENDIAN = 0,
 353         OMAP_DMA_BIG_ENDIAN
 354 };
 355
 356 enum omap_dma_color_mode {
 357         OMAP_DMA_COLOR_DIS = 0,
 358         OMAP_DMA_CONSTANT_FILL,
 359         OMAP_DMA_TRANSPARENT_COPY
 360 };
 361
 362 enum omap_dma_write_mode {
 363         OMAP_DMA_WRITE_NON_POSTED = 0,
 364         OMAP_DMA_WRITE_POSTED,
 365         OMAP_DMA_WRITE_LAST_NON_POSTED
 366 };
 367
 368 enum omap_dma_channel_mode {
 369         OMAP_DMA_LCH_2D = 0,
 370         OMAP_DMA_LCH_G,
 371         OMAP_DMA_LCH_P,
 372         OMAP_DMA_LCH_PD
 373 };
 374
 375 struct omap_dma_channel_params {
 376         int data_type;          /* data type 8,16,32 */
 377         int elem_count;         /* number of elements in a frame */
 378         int frame_count;        /* number of frames in a element */
 379
 380         int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 381         int src_amode;          /* constant, post increment, indexed,
 382                                         double indexed */
 383         unsigned long src_start;        /* source address : physical */
 384         int src_ei;             /* source element index */
 385         int src_fi;             /* source frame index */
 386
 387         int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 388         int dst_amode;          /* constant, post increment, indexed,
 389                                         double indexed */
 390         unsigned long dst_start;        /* source address : physical */
 391         int dst_ei;             /* source element index */
 392         int dst_fi;             /* source frame index */
 393
 394         int trigger;            /* trigger attached if the channel is
 395                                         synchronized */
 396         int sync_mode;          /* sycn on element, frame , block or packet */
 397         int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
 398
 399         int ie;                 /* interrupt enabled */
 400
 401         unsigned char read_prio;/* read priority */
 402         unsigned char write_prio;/* write priority */
 403
 404 #ifndef CONFIG_ARCH_OMAP1
 405         enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
 406 #endif
 407 };
 408
 409 struct omap_dma_lch {
 410         int next_lch;
 411         int dev_id;
 412         u16 saved_csr;
 413         u16 enabled_irqs;
 414         const char *dev_name;
 415         void (*callback)(int lch, u16 ch_status, void *data);
 416         void *data;
 417         long flags;
 418         /* required for Dynamic chaining */
 419         int prev_linked_ch;
 420         int next_linked_ch;
 421         int state;
 422         int chain_id;
 423         int status;
 424 };
 425
 426 struct omap_dma_dev_attr {
 427         u32 dev_caps;
 428         u16 lch_count;
 429         u16 chan_count;
 430         struct omap_dma_lch *chan;
 431 };
 432
 433 /* System DMA platform data structure */
 434 struct omap_system_dma_plat_info {
 435         struct omap_dma_dev_attr *dma_attr;
 436         u32 errata;
 437         void (*disable_irq_lch)(int lch);
 438         void (*show_dma_caps)(void);
 439         void (*clear_lch_regs)(int lch);
 440         void (*clear_dma)(int lch);
 441         void (*dma_write)(u32 val, int reg, int lch);
 442         u32 (*dma_read)(int reg, int lch);
 443 };
 444
 445 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 446 extern int omap_request_dma(int dev_id, const char *dev_name,
 447                         void (*callback)(int lch, u16 ch_status, void *data),
 448                         void *data, int *dma_ch);
 449 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
 450 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
 451 extern void omap_free_dma(int ch);
 452 extern void omap_start_dma(int lch);
 453 extern void omap_stop_dma(int lch);
 454 extern void omap_set_dma_transfer_params(int lch, int data_type,
 455                                          int elem_count, int frame_count,
 456                                          int sync_mode,
 457                                          int dma_trigger, int src_or_dst_synch);
 458 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
 459                                     u32 color);
 460 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
 461 extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
 462
 463 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 464                                     unsigned long src_start,
 465                                     int src_ei, int src_fi);
 466 extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
 467 extern void omap_set_dma_src_data_pack(int lch, int enable);
 468 extern void omap_set_dma_src_burst_mode(int lch,
 469                                         enum omap_dma_burst_mode burst_mode);
 470
 471 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 472                                      unsigned long dest_start,
 473                                      int dst_ei, int dst_fi);
 474 extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
 475 extern void omap_set_dma_dest_data_pack(int lch, int enable);
 476 extern void omap_set_dma_dest_burst_mode(int lch,
 477                                          enum omap_dma_burst_mode burst_mode);
 478
 479 extern void omap_set_dma_params(int lch,
 480                                 struct omap_dma_channel_params *params);
 481
 482 extern void omap_dma_link_lch(int lch_head, int lch_queue);
 483 extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
 484
 485 extern int omap_set_dma_callback(int lch,
 486                         void (*callback)(int lch, u16 ch_status, void *data),
 487                         void *data);
 488 extern dma_addr_t omap_get_dma_src_pos(int lch);
 489 extern dma_addr_t omap_get_dma_dst_pos(int lch);
 490 extern void omap_clear_dma(int lch);
 491 extern int omap_get_dma_active_status(int lch);
 492 extern int omap_dma_running(void);
 493 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
 494                                        int tparams);
 495 extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 496                                  unsigned char write_prio);
 497 extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
 498 extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
 499 extern int omap_get_dma_index(int lch, int *ei, int *fi);
 500
 501 void omap_dma_global_context_save(void);
 502 void omap_dma_global_context_restore(void);
 503
 504 extern void omap_dma_disable_irq(int lch);
 505
 506 /* Chaining APIs */
 507 #ifndef CONFIG_ARCH_OMAP1
 508 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
 509                                   void (*callback) (int lch, u16 ch_status,
 510                                                     void *data),
 511                                   int *chain_id, int no_of_chans,
 512                                   int chain_mode,
 513                                   struct omap_dma_channel_params params);
 514 extern int omap_free_dma_chain(int chain_id);
 515 extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
 516                                      int dest_start, int elem_count,
 517                                      int frame_count, void *callbk_data);
 518 extern int omap_start_dma_chain_transfers(int chain_id);
 519 extern int omap_stop_dma_chain_transfers(int chain_id);
 520 extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
 521 extern int omap_get_dma_chain_dst_pos(int chain_id);
 522 extern int omap_get_dma_chain_src_pos(int chain_id);
 523
 524 extern int omap_modify_dma_chain_params(int chain_id,
 525                                         struct omap_dma_channel_params params);
 526 extern int omap_dma_chain_status(int chain_id);
 527 #endif
 528
 529 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
 530 #include <mach/lcd_dma.h>
 531 #else
 532 static inline int omap_lcd_dma_running(void)
 533 {
 534         return 0;
 535 }
 536 #endif
 537
 538 #endif /* __ASM_ARCH_DMA_H */