| blob | 97510e55b802a587ad547c9f36005540ae2c8fc5 |
1 /* arch/m68knommu/platform/68360/head-rom.S
2 *
3 * Startup code for Motorola 68360
4 *
5 * Copyright (C) SED Systems, a Division of Calian Ltd.
6 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
7 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
8 * uClinux Kernel
9 * Copyright (C) Michael Leslie <mleslie@lineo.com>
10 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
11 * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>,
12 *
13 */
15 .global _stext
16 .global _sbss
17 .global _start
19 .global _rambase
20 .global _ramvec
21 .global _ramstart
22 .global _ramend
24 .global _quicc_base
25 .global _periph_base
27 #define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
29 #define REGB 0x1000
30 #define PEPAR (_dprbase + REGB + 0x0016)
31 #define GMR (_dprbase + REGB + 0x0040)
32 #define OR0 (_dprbase + REGB + 0x0054)
33 #define BR0 (_dprbase + REGB + 0x0050)
35 #define OR1 (_dprbase + REGB + 0x0064)
36 #define BR1 (_dprbase + REGB + 0x0060)
38 #define OR2 (_dprbase + REGB + 0x0074)
39 #define BR2 (_dprbase + REGB + 0x0070)
41 #define OR3 (_dprbase + REGB + 0x0084)
42 #define BR3 (_dprbase + REGB + 0x0080)
44 #define OR4 (_dprbase + REGB + 0x0094)
45 #define BR4 (_dprbase + REGB + 0x0090)
47 #define OR5 (_dprbase + REGB + 0x00A4)
48 #define BR5 (_dprbase + REGB + 0x00A0)
50 #define OR6 (_dprbase + REGB + 0x00b4)
51 #define BR6 (_dprbase + REGB + 0x00b0)
53 #define OR7 (_dprbase + REGB + 0x00c4)
54 #define BR7 (_dprbase + REGB + 0x00c0)
56 #define MCR (_dprbase + REGB + 0x0000)
57 #define AVR (_dprbase + REGB + 0x0008)
59 #define SYPCR (_dprbase + REGB + 0x0022)
61 #define PLLCR (_dprbase + REGB + 0x0010)
62 #define CLKOCR (_dprbase + REGB + 0x000C)
63 #define CDVCR (_dprbase + REGB + 0x0014)
65 #define BKAR (_dprbase + REGB + 0x0030)
66 #define BKCR (_dprbase + REGB + 0x0034)
67 #define SWIV (_dprbase + REGB + 0x0023)
68 #define PICR (_dprbase + REGB + 0x0026)
69 #define PITR (_dprbase + REGB + 0x002A)
71 /* Define for all memory configuration */
72 #define MCU_SIM_GMR 0x00000000
73 #define SIM_OR_MASK 0x0fffffff
75 /* Defines for chip select zero - the flash */
76 #define SIM_OR0_MASK 0x20000000
77 #define SIM_BR0_MASK 0x00000001
79 /* Defines for chip select one - the RAM */
80 #define SIM_OR1_MASK 0x10000000
81 #define SIM_BR1_MASK 0x00000001
83 #define MCU_SIM_MBAR_ADRS 0x0003ff00
84 #define MCU_SIM_MBAR_BA_MASK 0xfffff000
85 #define MCU_SIM_MBAR_AS_MASK 0x00000001
87 #define MCU_SIM_PEPAR 0x00B4
89 #define MCU_DISABLE_INTRPTS 0x2700
90 #define MCU_SIM_AVR 0x00
92 #define MCU_SIM_MCR 0x00005cff
94 #define MCU_SIM_CLKOCR 0x00
95 #define MCU_SIM_PLLCR 0x8000
96 #define MCU_SIM_CDVCR 0x0000
98 #define MCU_SIM_SYPCR 0x0000
99 #define MCU_SIM_SWIV 0x00
100 #define MCU_SIM_PICR 0x0000
101 #define MCU_SIM_PITR 0x0000
104 #include <asm/m68360_regs.h>
107 /*
108 * By the time this RAM specific code begins to execute, DPRAM
109 * and DRAM should already be mapped and accessible.
110 */
112 .text
113 _start:
114 _stext:
115 nop
116 ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */
117 /* We should not need to setup the boot stack the reset should do it. */
118 movea.l #RAMEND, %sp /* set up stack at the end of DRAM:*/
121 set_mbar_register:
122 moveq.l #0x07, %d1 /* Setup MBAR */
123 movec %d1, %dfc
125 lea.l MCU_SIM_MBAR_ADRS, %a0
126 move.l #_dprbase, %d0
127 andi.l #MCU_SIM_MBAR_BA_MASK, %d0
128 ori.l #MCU_SIM_MBAR_AS_MASK, %d0
129 moves.l %d0, %a0@
131 moveq.l #0x05, %d1
132 movec.l %d1, %dfc
134 /* Now we can begin to access registers in DPRAM */
136 set_sim_mcr:
137 /* Set Module Configuration Register */
138 move.l #MCU_SIM_MCR, MCR
140 /* to do: Determine cause of reset */
142 /*
143 * configure system clock MC68360 p. 6-40
144 * (value +1)*osc/128 = system clock
145 * or
146 * (value + 1)*osc = system clock
147 * You do not need to divide the oscillator by 128 unless you want to.
148 */
149 set_sim_clock:
150 move.w #MCU_SIM_PLLCR, PLLCR
151 move.b #MCU_SIM_CLKOCR, CLKOCR
152 move.w #MCU_SIM_CDVCR, CDVCR
154 /* Wait for the PLL to settle */
155 move.w #16384, %d0
156 pll_settle_wait:
157 subi.w #1, %d0
158 bne pll_settle_wait
160 /* Setup the system protection register, and watchdog timer register */
161 move.b #MCU_SIM_SWIV, SWIV
162 move.w #MCU_SIM_PICR, PICR
163 move.w #MCU_SIM_PITR, PITR
164 move.w #MCU_SIM_SYPCR, SYPCR
166 /* Clear DPRAM - system + parameter */
167 movea.l #_dprbase, %a0
168 movea.l #_dprbase+0x2000, %a1
170 /* Copy 0 to %a0 until %a0 == %a1 */
171 clear_dpram:
172 movel #0, %a0@+
173 cmpal %a0, %a1
174 bhi clear_dpram
176 configure_memory_controller:
177 /* Set up Global Memory Register (GMR) */
178 move.l #MCU_SIM_GMR, %d0
179 move.l %d0, GMR
181 configure_chip_select_0:
182 move.l #0x00400000, %d0
183 subq.l #0x01, %d0
184 eori.l #SIM_OR_MASK, %d0
185 ori.l #SIM_OR0_MASK, %d0
186 move.l %d0, OR0
188 move.l #__rom_start, %d0
189 ori.l #SIM_BR0_MASK, %d0
190 move.l %d0, BR0
192 move.l #0x0, BR1
193 move.l #0x0, BR2
194 move.l #0x0, BR3
195 move.l #0x0, BR4
196 move.l #0x0, BR5
197 move.l #0x0, BR6
198 move.l #0x0, BR7
200 move.w #MCU_SIM_PEPAR, PEPAR
202 /* point to vector table: */
203 move.l #_romvec, %a0
204 move.l #_ramvec, %a1
205 copy_vectors:
206 move.l %a0@, %d0
207 move.l %d0, %a1@
208 move.l %a0@, %a1@
209 addq.l #0x04, %a0
210 addq.l #0x04, %a1
211 cmp.l #_start, %a0
212 blt copy_vectors
214 move.l #_ramvec, %a1
215 movec %a1, %vbr
218 /* Copy data segment from ROM to RAM */
219 moveal #_etext, %a0
220 moveal #_sdata, %a1
221 moveal #_edata, %a2
223 /* Copy %a0 to %a1 until %a1 == %a2 */
224 LD1:
225 move.l %a0@, %d0
226 addq.l #0x04, %a0
227 move.l %d0, %a1@
228 addq.l #0x04, %a1
229 cmp.l #_edata, %a1
230 blt LD1
232 moveal #_sbss, %a0
233 moveal #_ebss, %a1
235 /* Copy 0 to %a0 until %a0 == %a1 */
236 L1:
237 movel #0, %a0@+
238 cmpal %a0, %a1
239 bhi L1
241 load_quicc:
242 move.l #_dprbase, _quicc_base
244 store_ram_size:
245 /* Set ram size information */
246 move.l #_sdata, _rambase
247 move.l #_ebss, _ramstart
248 move.l #RAMEND, %d0
249 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/
250 move.l %d0, _ramend /* Different from RAMEND.*/
252 pea 0
253 pea env
254 pea %sp@(4)
255 pea 0
257 lea init_thread_union, %a2
258 lea 0x2000(%a2), %sp
260 lp:
261 jsr start_kernel
263 _exit:
264 jmp _exit
267 .data
268 .align 4
269 env:
270 .long 0
271 _quicc_base:
272 .long 0
273 _periph_base:
274 .long 0
275 _ramvec:
276 .long 0
277 _rambase:
278 .long 0
279 _ramstart:
280 .long 0
281 _ramend:
282 .long 0
283 _dprbase:
284 .long 0xffffe000
287 .text
289 /*
290 * These are the exception vectors at boot up, they are copied into RAM
291 * and then overwritten as needed.
292 */
294 .section ".data..initvect","awx"
295 .long RAMEND /* Reset: Initial Stack Pointer - 0. */
296 .long _start /* Reset: Initial Program Counter - 1. */
297 .long buserr /* Bus Error - 2. */
298 .long trap /* Address Error - 3. */
299 .long trap /* Illegal Instruction - 4. */
300 .long trap /* Divide by zero - 5. */
301 .long trap /* CHK, CHK2 Instructions - 6. */
302 .long trap /* TRAPcc, TRAPV Instructions - 7. */
303 .long trap /* Privilege Violation - 8. */
304 .long trap /* Trace - 9. */
305 .long trap /* Line 1010 Emulator - 10. */
306 .long trap /* Line 1111 Emualtor - 11. */
307 .long trap /* Harware Breakpoint - 12. */
308 .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */
309 .long trap /* Format Error - 14. */
310 .long trap /* Uninitialized Interrupt - 15. */
311 .long trap /* (Unassigned, Reserver) - 16. */
312 .long trap /* (Unassigned, Reserver) - 17. */
313 .long trap /* (Unassigned, Reserver) - 18. */
314 .long trap /* (Unassigned, Reserver) - 19. */
315 .long trap /* (Unassigned, Reserver) - 20. */
316 .long trap /* (Unassigned, Reserver) - 21. */
317 .long trap /* (Unassigned, Reserver) - 22. */
318 .long trap /* (Unassigned, Reserver) - 23. */
319 .long trap /* Spurious Interrupt - 24. */
320 .long trap /* Level 1 Interrupt Autovector - 25. */
321 .long trap /* Level 2 Interrupt Autovector - 26. */
322 .long trap /* Level 3 Interrupt Autovector - 27. */
323 .long trap /* Level 4 Interrupt Autovector - 28. */
324 .long trap /* Level 5 Interrupt Autovector - 29. */
325 .long trap /* Level 6 Interrupt Autovector - 30. */
326 .long trap /* Level 7 Interrupt Autovector - 31. */
327 .long system_call /* Trap Instruction Vectors 0 - 32. */
328 .long trap /* Trap Instruction Vectors 1 - 33. */
329 .long trap /* Trap Instruction Vectors 2 - 34. */
330 .long trap /* Trap Instruction Vectors 3 - 35. */
331 .long trap /* Trap Instruction Vectors 4 - 36. */
332 .long trap /* Trap Instruction Vectors 5 - 37. */
333 .long trap /* Trap Instruction Vectors 6 - 38. */
334 .long trap /* Trap Instruction Vectors 7 - 39. */
335 .long trap /* Trap Instruction Vectors 8 - 40. */
336 .long trap /* Trap Instruction Vectors 9 - 41. */
337 .long trap /* Trap Instruction Vectors 10 - 42. */
338 .long trap /* Trap Instruction Vectors 11 - 43. */
339 .long trap /* Trap Instruction Vectors 12 - 44. */
340 .long trap /* Trap Instruction Vectors 13 - 45. */
341 .long trap /* Trap Instruction Vectors 14 - 46. */
342 .long trap /* Trap Instruction Vectors 15 - 47. */
343 .long 0 /* (Reserved for Coprocessor) - 48. */
344 .long 0 /* (Reserved for Coprocessor) - 49. */
345 .long 0 /* (Reserved for Coprocessor) - 50. */
346 .long 0 /* (Reserved for Coprocessor) - 51. */
347 .long 0 /* (Reserved for Coprocessor) - 52. */
348 .long 0 /* (Reserved for Coprocessor) - 53. */
349 .long 0 /* (Reserved for Coprocessor) - 54. */
350 .long 0 /* (Reserved for Coprocessor) - 55. */
351 .long 0 /* (Reserved for Coprocessor) - 56. */
352 .long 0 /* (Reserved for Coprocessor) - 57. */
353 .long 0 /* (Reserved for Coprocessor) - 58. */
354 .long 0 /* (Unassigned, Reserved) - 59. */
355 .long 0 /* (Unassigned, Reserved) - 60. */
356 .long 0 /* (Unassigned, Reserved) - 61. */
357 .long 0 /* (Unassigned, Reserved) - 62. */
358 .long 0 /* (Unassigned, Reserved) - 63. */
359 /* The assignment of these vectors to the CPM is */
360 /* dependent on the configuration of the CPM vba */
361 /* fields. */
362 .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */
363 .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
364 .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
365 .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */
366 .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */
367 .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */
368 .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
369 .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */
370 .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */
371 .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
372 .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
373 .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
374 .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */
375 .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */
376 .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
377 .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
378 .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */
379 .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
380 .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */
381 .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */
382 .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */
383 .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */
384 .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */
385 .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
386 .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
387 .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */
388 .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
389 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
390 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
391 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
392 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
393 .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
394 /* I don't think anything uses the vectors after here. */
395 .long 0 /* (User-Defined Vectors 34) - 96. */
396 .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */
397 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */
398 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */
399 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */
400 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */
401 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */
402 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */
403 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */
404 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */
405 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */
406 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */
407 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */
408 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */
409 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */
410 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */
411 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */
412 .long 0,0,0 /* (User-Defined Vectors 190 - 192). */
413 .text
414 ignore: rte