| blob | 50845924b7d9472ad88b1b5031468ab2493d560a |
1 /*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 */
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
36 #include <asm/page.h>
37 #include <asm/mmu.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include <asm/ptrace.h>
45 #include "head_booke.h"
47 /* As with the other PowerPC ports, it is expected that when code
48 * execution begins here, the following registers contain valid, yet
49 * optional, information:
50 *
51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
52 * r4 - Starting address of the init RAM disk
53 * r5 - Ending address of the init RAM disk
54 * r6 - Start of kernel command line string (e.g. "mem=128")
55 * r7 - End of kernel command line string
56 *
57 */
58 __HEAD
59 _ENTRY(_stext);
60 _ENTRY(_start);
61 /*
62 * Reserve a word at a fixed location to store the address
63 * of abatron_pteptrs
64 */
65 nop
66 /*
67 * Save parameters we are passed
68 */
69 mr r31,r3
70 mr r30,r4
71 mr r29,r5
72 mr r28,r6
73 mr r27,r7
74 li r25,0 /* phys kernel start (low) */
75 li r24,0 /* CPU number */
76 li r23,0 /* phys kernel start (high) */
78 /* We try to not make any assumptions about how the boot loader
79 * setup or used the TLBs. We invalidate all mappings from the
80 * boot loader and load a single entry in TLB1[0] to map the
81 * first 64M of kernel memory. Any boot info passed from the
82 * bootloader needs to live in this first 64M.
83 *
84 * Requirement on bootloader:
85 * - The page we're executing in needs to reside in TLB1 and
86 * have IPROT=1. If not an invalidate broadcast could
87 * evict the entry we're currently executing in.
88 *
89 * r3 = Index of TLB1 were executing in
90 * r4 = Current MSR[IS]
91 * r5 = Index of TLB1 temp mapping
92 *
93 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
94 * if needed
95 */
97 _ENTRY(__early_start)
99 #define ENTRY_MAPPING_BOOT_SETUP
100 #include "fsl_booke_entry_mapping.S"
101 #undef ENTRY_MAPPING_BOOT_SETUP
103 /* Establish the interrupt vector offsets */
104 SET_IVOR(0, CriticalInput);
105 SET_IVOR(1, MachineCheck);
106 SET_IVOR(2, DataStorage);
107 SET_IVOR(3, InstructionStorage);
108 SET_IVOR(4, ExternalInput);
109 SET_IVOR(5, Alignment);
110 SET_IVOR(6, Program);
111 SET_IVOR(7, FloatingPointUnavailable);
112 SET_IVOR(8, SystemCall);
113 SET_IVOR(9, AuxillaryProcessorUnavailable);
114 SET_IVOR(10, Decrementer);
115 SET_IVOR(11, FixedIntervalTimer);
116 SET_IVOR(12, WatchdogTimer);
117 SET_IVOR(13, DataTLBError);
118 SET_IVOR(14, InstructionTLBError);
119 SET_IVOR(15, DebugCrit);
121 /* Establish the interrupt vector base */
122 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
123 mtspr SPRN_IVPR,r4
125 /* Setup the defaults for TLB entries */
126 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
127 #ifdef CONFIG_E200
128 oris r2,r2,MAS4_TLBSELD(1)@h
129 #endif
130 mtspr SPRN_MAS4, r2
132 #if 0
133 /* Enable DOZE */
134 mfspr r2,SPRN_HID0
135 oris r2,r2,HID0_DOZE@h
136 mtspr SPRN_HID0, r2
137 #endif
139 #if !defined(CONFIG_BDI_SWITCH)
140 /*
141 * The Abatron BDI JTAG debugger does not tolerate others
142 * mucking with the debug registers.
143 */
144 lis r2,DBCR0_IDM@h
145 mtspr SPRN_DBCR0,r2
146 isync
147 /* clear any residual debug events */
148 li r2,-1
149 mtspr SPRN_DBSR,r2
150 #endif
152 #ifdef CONFIG_SMP
153 /* Check to see if we're the second processor, and jump
154 * to the secondary_start code if so
155 */
156 lis r24, boot_cpuid@h
157 ori r24, r24, boot_cpuid@l
158 lwz r24, 0(r24)
159 cmpwi r24, -1
160 mfspr r24,SPRN_PIR
161 bne __secondary_start
162 #endif
164 /*
165 * This is where the main kernel code starts.
166 */
168 /* ptr to current */
169 lis r2,init_task@h
170 ori r2,r2,init_task@l
172 /* ptr to current thread */
173 addi r4,r2,THREAD /* init task's THREAD */
174 mtspr SPRN_SPRG_THREAD,r4
176 /* stack */
177 lis r1,init_thread_union@h
178 ori r1,r1,init_thread_union@l
179 li r0,0
180 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
182 rlwinm r22,r1,0,0,31-THREAD_SHIFT /* current thread_info */
183 stw r24, TI_CPU(r22)
185 bl early_init
187 #ifdef CONFIG_RELOCATABLE
188 lis r3,kernstart_addr@ha
189 la r3,kernstart_addr@l(r3)
190 #ifdef CONFIG_PHYS_64BIT
191 stw r23,0(r3)
192 stw r25,4(r3)
193 #else
194 stw r25,0(r3)
195 #endif
196 #endif
198 /*
199 * Decide what sort of machine this is and initialize the MMU.
200 */
201 mr r3,r31
202 mr r4,r30
203 mr r5,r29
204 mr r6,r28
205 mr r7,r27
206 bl machine_init
207 bl MMU_init
209 /* Setup PTE pointers for the Abatron bdiGDB */
210 lis r6, swapper_pg_dir@h
211 ori r6, r6, swapper_pg_dir@l
212 lis r5, abatron_pteptrs@h
213 ori r5, r5, abatron_pteptrs@l
214 lis r4, KERNELBASE@h
215 ori r4, r4, KERNELBASE@l
216 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
217 stw r6, 0(r5)
219 /* Let's move on */
220 lis r4,start_kernel@h
221 ori r4,r4,start_kernel@l
222 lis r3,MSR_KERNEL@h
223 ori r3,r3,MSR_KERNEL@l
224 mtspr SPRN_SRR0,r4
225 mtspr SPRN_SRR1,r3
226 rfi /* change context and jump to start_kernel */
228 /* Macros to hide the PTE size differences
229 *
230 * FIND_PTE -- walks the page tables given EA & pgdir pointer
231 * r10 -- EA of fault
232 * r11 -- PGDIR pointer
233 * r12 -- free
234 * label 2: is the bailout case
235 *
236 * if we find the pte (fall through):
237 * r11 is low pte word
238 * r12 is pointer to the pte
239 */
240 #ifdef CONFIG_PTE_64BIT
241 #define FIND_PTE \
242 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
243 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
244 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
245 beq 2f; /* Bail if no table */ \
246 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
247 lwz r11, 4(r12); /* Get pte entry */
248 #else
249 #define FIND_PTE \
250 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
251 lwz r11, 0(r11); /* Get L1 entry */ \
252 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
253 beq 2f; /* Bail if no table */ \
254 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
255 lwz r11, 0(r12); /* Get Linux PTE */
256 #endif
258 /*
259 * Interrupt vector entry code
260 *
261 * The Book E MMUs are always on so we don't need to handle
262 * interrupts in real mode as with previous PPC processors. In
263 * this case we handle interrupts in the kernel virtual address
264 * space.
265 *
266 * Interrupt vectors are dynamically placed relative to the
267 * interrupt prefix as determined by the address of interrupt_base.
268 * The interrupt vectors offsets are programmed using the labels
269 * for each interrupt vector entry.
270 *
271 * Interrupt vectors must be aligned on a 16 byte boundary.
272 * We align on a 32 byte cache line boundary for good measure.
273 */
275 interrupt_base:
276 /* Critical Input Interrupt */
277 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
279 /* Machine Check Interrupt */
280 #ifdef CONFIG_E200
281 /* no RFMCI, MCSRRs on E200 */
282 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
283 #else
284 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
285 #endif
287 /* Data Storage Interrupt */
288 START_EXCEPTION(DataStorage)
289 NORMAL_EXCEPTION_PROLOG
290 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
291 stw r5,_ESR(r11)
292 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
293 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
294 bne 1f
295 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
296 1:
297 addi r3,r1,STACK_FRAME_OVERHEAD
298 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
300 /* Instruction Storage Interrupt */
301 INSTRUCTION_STORAGE_EXCEPTION
303 /* External Input Interrupt */
304 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
306 /* Alignment Interrupt */
307 ALIGNMENT_EXCEPTION
309 /* Program Interrupt */
310 PROGRAM_EXCEPTION
312 /* Floating Point Unavailable Interrupt */
313 #ifdef CONFIG_PPC_FPU
314 FP_UNAVAILABLE_EXCEPTION
315 #else
316 #ifdef CONFIG_E200
317 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
318 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
319 #else
320 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
321 #endif
322 #endif
324 /* System Call Interrupt */
325 START_EXCEPTION(SystemCall)
326 NORMAL_EXCEPTION_PROLOG
327 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
329 /* Auxiliary Processor Unavailable Interrupt */
330 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
332 /* Decrementer Interrupt */
333 DECREMENTER_EXCEPTION
335 /* Fixed Internal Timer Interrupt */
336 /* TODO: Add FIT support */
337 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
339 /* Watchdog Timer Interrupt */
340 #ifdef CONFIG_BOOKE_WDT
341 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
342 #else
343 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
344 #endif
346 /* Data TLB Error Interrupt */
347 START_EXCEPTION(DataTLBError)
348 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
349 mfspr r10, SPRN_SPRG_THREAD
350 stw r11, THREAD_NORMSAVE(0)(r10)
351 stw r12, THREAD_NORMSAVE(1)(r10)
352 stw r13, THREAD_NORMSAVE(2)(r10)
353 mfcr r13
354 stw r13, THREAD_NORMSAVE(3)(r10)
355 mfspr r10, SPRN_DEAR /* Get faulting address */
357 /* If we are faulting a kernel address, we have to use the
358 * kernel page tables.
359 */
360 lis r11, PAGE_OFFSET@h
361 cmplw 5, r10, r11
362 blt 5, 3f
363 lis r11, swapper_pg_dir@h
364 ori r11, r11, swapper_pg_dir@l
366 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
367 rlwinm r12,r12,0,16,1
368 mtspr SPRN_MAS1,r12
370 b 4f
372 /* Get the PGD for the current thread */
373 3:
374 mfspr r11,SPRN_SPRG_THREAD
375 lwz r11,PGDIR(r11)
377 4:
378 /* Mask of required permission bits. Note that while we
379 * do copy ESR:ST to _PAGE_RW position as trying to write
380 * to an RO page is pretty common, we don't do it with
381 * _PAGE_DIRTY. We could do it, but it's a fairly rare
382 * event so I'd rather take the overhead when it happens
383 * rather than adding an instruction here. We should measure
384 * whether the whole thing is worth it in the first place
385 * as we could avoid loading SPRN_ESR completely in the first
386 * place...
387 *
388 * TODO: Is it worth doing that mfspr & rlwimi in the first
389 * place or can we save a couple of instructions here ?
390 */
391 mfspr r12,SPRN_ESR
392 #ifdef CONFIG_PTE_64BIT
393 li r13,_PAGE_PRESENT
394 oris r13,r13,_PAGE_ACCESSED@h
395 #else
396 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
397 #endif
398 rlwimi r13,r12,11,29,29
400 FIND_PTE
401 andc. r13,r13,r11 /* Check permission */
403 #ifdef CONFIG_PTE_64BIT
404 #ifdef CONFIG_SMP
405 subf r10,r11,r12 /* create false data dep */
406 lwzx r13,r11,r10 /* Get upper pte bits */
407 #else
408 lwz r13,0(r12) /* Get upper pte bits */
409 #endif
410 #endif
412 bne 2f /* Bail if permission/valid mismach */
414 /* Jump to common tlb load */
415 b finish_tlb_load
416 2:
417 /* The bailout. Restore registers to pre-exception conditions
418 * and call the heavyweights to help us out.
419 */
420 mfspr r10, SPRN_SPRG_THREAD
421 lwz r11, THREAD_NORMSAVE(3)(r10)
422 mtcr r11
423 lwz r13, THREAD_NORMSAVE(2)(r10)
424 lwz r12, THREAD_NORMSAVE(1)(r10)
425 lwz r11, THREAD_NORMSAVE(0)(r10)
426 mfspr r10, SPRN_SPRG_RSCRATCH0
427 b DataStorage
429 /* Instruction TLB Error Interrupt */
430 /*
431 * Nearly the same as above, except we get our
432 * information from different registers and bailout
433 * to a different point.
434 */
435 START_EXCEPTION(InstructionTLBError)
436 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
437 mfspr r10, SPRN_SPRG_THREAD
438 stw r11, THREAD_NORMSAVE(0)(r10)
439 stw r12, THREAD_NORMSAVE(1)(r10)
440 stw r13, THREAD_NORMSAVE(2)(r10)
441 mfcr r13
442 stw r13, THREAD_NORMSAVE(3)(r10)
443 mfspr r10, SPRN_SRR0 /* Get faulting address */
445 /* If we are faulting a kernel address, we have to use the
446 * kernel page tables.
447 */
448 lis r11, PAGE_OFFSET@h
449 cmplw 5, r10, r11
450 blt 5, 3f
451 lis r11, swapper_pg_dir@h
452 ori r11, r11, swapper_pg_dir@l
454 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
455 rlwinm r12,r12,0,16,1
456 mtspr SPRN_MAS1,r12
458 /* Make up the required permissions for kernel code */
459 #ifdef CONFIG_PTE_64BIT
460 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
461 oris r13,r13,_PAGE_ACCESSED@h
462 #else
463 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
464 #endif
465 b 4f
467 /* Get the PGD for the current thread */
468 3:
469 mfspr r11,SPRN_SPRG_THREAD
470 lwz r11,PGDIR(r11)
472 /* Make up the required permissions for user code */
473 #ifdef CONFIG_PTE_64BIT
474 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
475 oris r13,r13,_PAGE_ACCESSED@h
476 #else
477 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
478 #endif
480 4:
481 FIND_PTE
482 andc. r13,r13,r11 /* Check permission */
484 #ifdef CONFIG_PTE_64BIT
485 #ifdef CONFIG_SMP
486 subf r10,r11,r12 /* create false data dep */
487 lwzx r13,r11,r10 /* Get upper pte bits */
488 #else
489 lwz r13,0(r12) /* Get upper pte bits */
490 #endif
491 #endif
493 bne 2f /* Bail if permission mismach */
495 /* Jump to common TLB load point */
496 b finish_tlb_load
498 2:
499 /* The bailout. Restore registers to pre-exception conditions
500 * and call the heavyweights to help us out.
501 */
502 mfspr r10, SPRN_SPRG_THREAD
503 lwz r11, THREAD_NORMSAVE(3)(r10)
504 mtcr r11
505 lwz r13, THREAD_NORMSAVE(2)(r10)
506 lwz r12, THREAD_NORMSAVE(1)(r10)
507 lwz r11, THREAD_NORMSAVE(0)(r10)
508 mfspr r10, SPRN_SPRG_RSCRATCH0
509 b InstructionStorage
511 #ifdef CONFIG_SPE
512 /* SPE Unavailable */
513 START_EXCEPTION(SPEUnavailable)
514 NORMAL_EXCEPTION_PROLOG
515 bne load_up_spe
516 addi r3,r1,STACK_FRAME_OVERHEAD
517 EXC_XFER_EE_LITE(0x2010, KernelSPE)
518 #else
519 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
520 #endif /* CONFIG_SPE */
522 /* SPE Floating Point Data */
523 #ifdef CONFIG_SPE
524 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
526 /* SPE Floating Point Round */
527 EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
528 #else
529 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
530 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
531 #endif /* CONFIG_SPE */
533 /* Performance Monitor */
534 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
536 EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
538 CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
540 /* Debug Interrupt */
541 DEBUG_DEBUG_EXCEPTION
542 DEBUG_CRIT_EXCEPTION
544 /*
545 * Local functions
546 */
548 /*
549 * Both the instruction and data TLB miss get to this
550 * point to load the TLB.
551 * r10 - available to use
552 * r11 - TLB (info from Linux PTE)
553 * r12 - available to use
554 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
555 * CR5 - results of addr >= PAGE_OFFSET
556 * MAS0, MAS1 - loaded with proper value when we get here
557 * MAS2, MAS3 - will need additional info from Linux PTE
558 * Upon exit, we reload everything and RFI.
559 */
560 finish_tlb_load:
561 /*
562 * We set execute, because we don't have the granularity to
563 * properly set this at the page level (Linux problem).
564 * Many of these bits are software only. Bits we don't set
565 * here we (properly should) assume have the appropriate value.
566 */
568 mfspr r12, SPRN_MAS2
569 #ifdef CONFIG_PTE_64BIT
570 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
571 #else
572 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
573 #endif
574 mtspr SPRN_MAS2, r12
576 #ifdef CONFIG_PTE_64BIT
577 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
578 andi. r10, r11, _PAGE_DIRTY
579 bne 1f
580 li r10, MAS3_SW | MAS3_UW
581 andc r12, r12, r10
582 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
583 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
584 mtspr SPRN_MAS3, r12
585 BEGIN_MMU_FTR_SECTION
586 srwi r10, r13, 12 /* grab RPN[12:31] */
587 mtspr SPRN_MAS7, r10
588 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
589 #else
590 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
591 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
592 and r12, r11, r10
593 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
594 slwi r10, r12, 1
595 or r10, r10, r12
596 iseleq r12, r12, r10
597 rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
598 mtspr SPRN_MAS3, r11
599 #endif
600 #ifdef CONFIG_E200
601 /* Round robin TLB1 entries assignment */
602 mfspr r12, SPRN_MAS0
604 /* Extract TLB1CFG(NENTRY) */
605 mfspr r11, SPRN_TLB1CFG
606 andi. r11, r11, 0xfff
608 /* Extract MAS0(NV) */
609 andi. r13, r12, 0xfff
610 addi r13, r13, 1
611 cmpw 0, r13, r11
612 addi r12, r12, 1
614 /* check if we need to wrap */
615 blt 7f
617 /* wrap back to first free tlbcam entry */
618 lis r13, tlbcam_index@ha
619 lwz r13, tlbcam_index@l(r13)
620 rlwimi r12, r13, 0, 20, 31
621 7:
622 mtspr SPRN_MAS0,r12
623 #endif /* CONFIG_E200 */
625 tlbwe
627 /* Done...restore registers and get out of here. */
628 mfspr r10, SPRN_SPRG_THREAD
629 lwz r11, THREAD_NORMSAVE(3)(r10)
630 mtcr r11
631 lwz r13, THREAD_NORMSAVE(2)(r10)
632 lwz r12, THREAD_NORMSAVE(1)(r10)
633 lwz r11, THREAD_NORMSAVE(0)(r10)
634 mfspr r10, SPRN_SPRG_RSCRATCH0
635 rfi /* Force context change */
637 #ifdef CONFIG_SPE
638 /* Note that the SPE support is closely modeled after the AltiVec
639 * support. Changes to one are likely to be applicable to the
640 * other! */
641 load_up_spe:
642 /*
643 * Disable SPE for the task which had SPE previously,
644 * and save its SPE registers in its thread_struct.
645 * Enables SPE for use in the kernel on return.
646 * On SMP we know the SPE units are free, since we give it up every
647 * switch. -- Kumar
648 */
649 mfmsr r5
650 oris r5,r5,MSR_SPE@h
651 mtmsr r5 /* enable use of SPE now */
652 isync
653 /*
654 * For SMP, we don't do lazy SPE switching because it just gets too
655 * horrendously complex, especially when a task switches from one CPU
656 * to another. Instead we call giveup_spe in switch_to.
657 */
658 #ifndef CONFIG_SMP
659 lis r3,last_task_used_spe@ha
660 lwz r4,last_task_used_spe@l(r3)
661 cmpi 0,r4,0
662 beq 1f
663 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
664 SAVE_32EVRS(0,r10,r4,THREAD_EVR0)
665 evxor evr10, evr10, evr10 /* clear out evr10 */
666 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
667 li r5,THREAD_ACC
668 evstddx evr10, r4, r5 /* save off accumulator */
669 lwz r5,PT_REGS(r4)
670 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
671 lis r10,MSR_SPE@h
672 andc r4,r4,r10 /* disable SPE for previous task */
673 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
674 1:
675 #endif /* !CONFIG_SMP */
676 /* enable use of SPE after return */
677 oris r9,r9,MSR_SPE@h
678 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
679 li r4,1
680 li r10,THREAD_ACC
681 stw r4,THREAD_USED_SPE(r5)
682 evlddx evr4,r10,r5
683 evmra evr4,evr4
684 REST_32EVRS(0,r10,r5,THREAD_EVR0)
685 #ifndef CONFIG_SMP
686 subi r4,r5,THREAD
687 stw r4,last_task_used_spe@l(r3)
688 #endif /* !CONFIG_SMP */
689 /* restore registers and return */
690 2: REST_4GPRS(3, r11)
691 lwz r10,_CCR(r11)
692 REST_GPR(1, r11)
693 mtcr r10
694 lwz r10,_LINK(r11)
695 mtlr r10
696 REST_GPR(10, r11)
697 mtspr SPRN_SRR1,r9
698 mtspr SPRN_SRR0,r12
699 REST_GPR(9, r11)
700 REST_GPR(12, r11)
701 lwz r11,GPR11(r11)
702 rfi
704 /*
705 * SPE unavailable trap from kernel - print a message, but let
706 * the task use SPE in the kernel until it returns to user mode.
707 */
708 KernelSPE:
709 lwz r3,_MSR(r1)
710 oris r3,r3,MSR_SPE@h
711 stw r3,_MSR(r1) /* enable use of SPE after return */
712 #ifdef CONFIG_PRINTK
713 lis r3,87f@h
714 ori r3,r3,87f@l
715 mr r4,r2 /* current */
716 lwz r5,_NIP(r1)
717 bl printk
718 #endif
719 b ret_from_except
720 #ifdef CONFIG_PRINTK
721 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
722 #endif
723 .align 4,0
725 #endif /* CONFIG_SPE */
727 /*
728 * Global functions
729 */
731 /* Adjust or setup IVORs for e200 */
732 _GLOBAL(__setup_e200_ivors)
733 li r3,DebugDebug@l
734 mtspr SPRN_IVOR15,r3
735 li r3,SPEUnavailable@l
736 mtspr SPRN_IVOR32,r3
737 li r3,SPEFloatingPointData@l
738 mtspr SPRN_IVOR33,r3
739 li r3,SPEFloatingPointRound@l
740 mtspr SPRN_IVOR34,r3
741 sync
742 blr
744 /* Adjust or setup IVORs for e500v1/v2 */
745 _GLOBAL(__setup_e500_ivors)
746 li r3,DebugCrit@l
747 mtspr SPRN_IVOR15,r3
748 li r3,SPEUnavailable@l
749 mtspr SPRN_IVOR32,r3
750 li r3,SPEFloatingPointData@l
751 mtspr SPRN_IVOR33,r3
752 li r3,SPEFloatingPointRound@l
753 mtspr SPRN_IVOR34,r3
754 li r3,PerformanceMonitor@l
755 mtspr SPRN_IVOR35,r3
756 sync
757 blr
759 /* Adjust or setup IVORs for e500mc */
760 _GLOBAL(__setup_e500mc_ivors)
761 li r3,DebugDebug@l
762 mtspr SPRN_IVOR15,r3
763 li r3,PerformanceMonitor@l
764 mtspr SPRN_IVOR35,r3
765 li r3,Doorbell@l
766 mtspr SPRN_IVOR36,r3
767 li r3,CriticalDoorbell@l
768 mtspr SPRN_IVOR37,r3
769 sync
770 blr
772 /*
773 * extern void giveup_altivec(struct task_struct *prev)
774 *
775 * The e500 core does not have an AltiVec unit.
776 */
777 _GLOBAL(giveup_altivec)
778 blr
780 #ifdef CONFIG_SPE
781 /*
782 * extern void giveup_spe(struct task_struct *prev)
783 *
784 */
785 _GLOBAL(giveup_spe)
786 mfmsr r5
787 oris r5,r5,MSR_SPE@h
788 mtmsr r5 /* enable use of SPE now */
789 isync
790 cmpi 0,r3,0
791 beqlr- /* if no previous owner, done */
792 addi r3,r3,THREAD /* want THREAD of task */
793 lwz r5,PT_REGS(r3)
794 cmpi 0,r5,0
795 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
796 evxor evr6, evr6, evr6 /* clear out evr6 */
797 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
798 li r4,THREAD_ACC
799 evstddx evr6, r4, r3 /* save off accumulator */
800 beq 1f
801 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
802 lis r3,MSR_SPE@h
803 andc r4,r4,r3 /* disable SPE for previous task */
804 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
805 1:
806 #ifndef CONFIG_SMP
807 li r5,0
808 lis r4,last_task_used_spe@ha
809 stw r5,last_task_used_spe@l(r4)
810 #endif /* !CONFIG_SMP */
811 blr
812 #endif /* CONFIG_SPE */
814 /*
815 * extern void giveup_fpu(struct task_struct *prev)
816 *
817 * Not all FSL Book-E cores have an FPU
818 */
819 #ifndef CONFIG_PPC_FPU
820 _GLOBAL(giveup_fpu)
821 blr
822 #endif
824 /*
825 * extern void abort(void)
826 *
827 * At present, this routine just applies a system reset.
828 */
829 _GLOBAL(abort)
830 li r13,0
831 mtspr SPRN_DBCR0,r13 /* disable all debug events */
832 isync
833 mfmsr r13
834 ori r13,r13,MSR_DE@l /* Enable Debug Events */
835 mtmsr r13
836 isync
837 mfspr r13,SPRN_DBCR0
838 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
839 mtspr SPRN_DBCR0,r13
840 isync
842 _GLOBAL(set_context)
844 #ifdef CONFIG_BDI_SWITCH
845 /* Context switch the PTE pointer for the Abatron BDI2000.
846 * The PGDIR is the second parameter.
847 */
848 lis r5, abatron_pteptrs@h
849 ori r5, r5, abatron_pteptrs@l
850 stw r4, 0x4(r5)
851 #endif
852 mtspr SPRN_PID,r3
853 isync /* Force context change */
854 blr
856 _GLOBAL(flush_dcache_L1)
857 mfspr r3,SPRN_L1CFG0
859 rlwinm r5,r3,9,3 /* Extract cache block size */
860 twlgti r5,1 /* Only 32 and 64 byte cache blocks
861 * are currently defined.
862 */
863 li r4,32
864 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
865 * log2(number of ways)
866 */
867 slw r5,r4,r5 /* r5 = cache block size */
869 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
870 mulli r7,r7,13 /* An 8-way cache will require 13
871 * loads per set.
872 */
873 slw r7,r7,r6
875 /* save off HID0 and set DCFA */
876 mfspr r8,SPRN_HID0
877 ori r9,r8,HID0_DCFA@l
878 mtspr SPRN_HID0,r9
879 isync
881 lis r4,KERNELBASE@h
882 mtctr r7
884 1: lwz r3,0(r4) /* Load... */
885 add r4,r4,r5
886 bdnz 1b
888 msync
889 lis r4,KERNELBASE@h
890 mtctr r7
892 1: dcbf 0,r4 /* ...and flush. */
893 add r4,r4,r5
894 bdnz 1b
896 /* restore HID0 */
897 mtspr SPRN_HID0,r8
898 isync
900 blr
902 #ifdef CONFIG_SMP
903 /* When we get here, r24 needs to hold the CPU # */
904 .globl __secondary_start
905 __secondary_start:
906 lis r3,__secondary_hold_acknowledge@h
907 ori r3,r3,__secondary_hold_acknowledge@l
908 stw r24,0(r3)
910 li r3,0
911 mr r4,r24 /* Why? */
912 bl call_setup_cpu
914 lis r3,tlbcam_index@ha
915 lwz r3,tlbcam_index@l(r3)
916 mtctr r3
917 li r26,0 /* r26 safe? */
919 /* Load each CAM entry */
920 1: mr r3,r26
921 bl loadcam_entry
922 addi r26,r26,1
923 bdnz 1b
925 /* get current_thread_info and current */
926 lis r1,secondary_ti@ha
927 lwz r1,secondary_ti@l(r1)
928 lwz r2,TI_TASK(r1)
930 /* stack */
931 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
932 li r0,0
933 stw r0,0(r1)
935 /* ptr to current thread */
936 addi r4,r2,THREAD /* address of our thread_struct */
937 mtspr SPRN_SPRG_THREAD,r4
939 /* Setup the defaults for TLB entries */
940 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
941 mtspr SPRN_MAS4,r4
943 /* Jump to start_secondary */
944 lis r4,MSR_KERNEL@h
945 ori r4,r4,MSR_KERNEL@l
946 lis r3,start_secondary@h
947 ori r3,r3,start_secondary@l
948 mtspr SPRN_SRR0,r3
949 mtspr SPRN_SRR1,r4
950 sync
951 rfi
952 sync
954 .globl __secondary_hold_acknowledge
955 __secondary_hold_acknowledge:
956 .long -1
957 #endif
959 /*
960 * We put a few things here that have to be page-aligned. This stuff
961 * goes at the beginning of the data segment, which is page-aligned.
962 */
963 .data
964 .align 12
965 .globl sdata
966 sdata:
967 .globl empty_zero_page
968 empty_zero_page:
969 .space 4096
970 .globl swapper_pg_dir
971 swapper_pg_dir:
972 .space PGD_TABLE_SIZE
974 /*
975 * Room for two PTE pointers, usually the kernel and current user pointers
976 * to their respective root page table.
977 */
978 abatron_pteptrs:
979 .space 8