1 #include <linux/seq_file.h>
2 #include <linux/kernel.h>
3 #include <linux/module.h>
4 #include <asm/machvec.h>
5 #include <asm/processor.h>
7 static const char *cpu_name
[] = {
8 [CPU_SH7201
] = "SH7201",
9 [CPU_SH7203
] = "SH7203", [CPU_SH7263
] = "SH7263",
10 [CPU_SH7206
] = "SH7206", [CPU_SH7619
] = "SH7619",
11 [CPU_SH7705
] = "SH7705", [CPU_SH7706
] = "SH7706",
12 [CPU_SH7707
] = "SH7707", [CPU_SH7708
] = "SH7708",
13 [CPU_SH7709
] = "SH7709", [CPU_SH7710
] = "SH7710",
14 [CPU_SH7712
] = "SH7712", [CPU_SH7720
] = "SH7720",
15 [CPU_SH7721
] = "SH7721", [CPU_SH7729
] = "SH7729",
16 [CPU_SH7750
] = "SH7750", [CPU_SH7750S
] = "SH7750S",
17 [CPU_SH7750R
] = "SH7750R", [CPU_SH7751
] = "SH7751",
18 [CPU_SH7751R
] = "SH7751R", [CPU_SH7760
] = "SH7760",
19 [CPU_SH4_202
] = "SH4-202", [CPU_SH4_501
] = "SH4-501",
20 [CPU_SH7763
] = "SH7763", [CPU_SH7770
] = "SH7770",
21 [CPU_SH7780
] = "SH7780", [CPU_SH7781
] = "SH7781",
22 [CPU_SH7343
] = "SH7343", [CPU_SH7785
] = "SH7785",
23 [CPU_SH7786
] = "SH7786", [CPU_SH7757
] = "SH7757",
24 [CPU_SH7722
] = "SH7722", [CPU_SHX3
] = "SH-X3",
25 [CPU_SH5_101
] = "SH5-101", [CPU_SH5_103
] = "SH5-103",
26 [CPU_MXG
] = "MX-G", [CPU_SH7723
] = "SH7723",
27 [CPU_SH7366
] = "SH7366", [CPU_SH7724
] = "SH7724",
28 [CPU_SH7372
] = "SH7372", [CPU_SH_NONE
] = "Unknown"
31 const char *get_cpu_subtype(struct sh_cpuinfo
*c
)
33 return cpu_name
[c
->type
];
35 EXPORT_SYMBOL(get_cpu_subtype
);
38 /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
39 static const char *cpu_flags
[] = {
40 "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
41 "ptea", "llsc", "l2", "op32", "pteaex", NULL
44 static void show_cpuflags(struct seq_file
*m
, struct sh_cpuinfo
*c
)
48 seq_printf(m
, "cpu flags\t:");
51 seq_printf(m
, " %s\n", cpu_flags
[0]);
55 for (i
= 0; cpu_flags
[i
]; i
++)
56 if ((c
->flags
& (1 << i
)))
57 seq_printf(m
, " %s", cpu_flags
[i
+1]);
62 static void show_cacheinfo(struct seq_file
*m
, const char *type
,
63 struct cache_info info
)
65 unsigned int cache_size
;
67 cache_size
= info
.ways
* info
.sets
* info
.linesz
;
69 seq_printf(m
, "%s size\t: %2dKiB (%d-way)\n",
70 type
, cache_size
>> 10, info
.ways
);
74 * Get CPU information for use by the procfs.
76 static int show_cpuinfo(struct seq_file
*m
, void *v
)
78 struct sh_cpuinfo
*c
= v
;
79 unsigned int cpu
= c
- cpu_data
;
85 seq_printf(m
, "machine\t\t: %s\n", get_system_type());
89 seq_printf(m
, "processor\t: %d\n", cpu
);
90 seq_printf(m
, "cpu family\t: %s\n", init_utsname()->machine
);
91 seq_printf(m
, "cpu type\t: %s\n", get_cpu_subtype(c
));
92 if (c
->cut_major
== -1)
93 seq_printf(m
, "cut\t\t: unknown\n");
94 else if (c
->cut_minor
== -1)
95 seq_printf(m
, "cut\t\t: %d.x\n", c
->cut_major
);
97 seq_printf(m
, "cut\t\t: %d.%d\n", c
->cut_major
, c
->cut_minor
);
101 seq_printf(m
, "cache type\t: ");
104 * Check for what type of cache we have, we support both the
105 * unified cache on the SH-2 and SH-3, as well as the harvard
106 * style cache on the SH-4.
108 if (c
->icache
.flags
& SH_CACHE_COMBINED
) {
109 seq_printf(m
, "unified\n");
110 show_cacheinfo(m
, "cache", c
->icache
);
112 seq_printf(m
, "split (harvard)\n");
113 show_cacheinfo(m
, "icache", c
->icache
);
114 show_cacheinfo(m
, "dcache", c
->dcache
);
117 /* Optional secondary cache */
118 if (c
->flags
& CPU_HAS_L2_CACHE
)
119 show_cacheinfo(m
, "scache", c
->scache
);
121 seq_printf(m
, "address sizes\t: %u bits physical\n", c
->phys_bits
);
123 seq_printf(m
, "bogomips\t: %lu.%02lu\n",
124 c
->loops_per_jiffy
/(500000/HZ
),
125 (c
->loops_per_jiffy
/(5000/HZ
)) % 100);
130 static void *c_start(struct seq_file
*m
, loff_t
*pos
)
132 return *pos
< NR_CPUS
? cpu_data
+ *pos
: NULL
;
134 static void *c_next(struct seq_file
*m
, void *v
, loff_t
*pos
)
137 return c_start(m
, pos
);
139 static void c_stop(struct seq_file
*m
, void *v
)
142 const struct seq_operations cpuinfo_op
= {
146 .show
= show_cpuinfo
,
148 #endif /* CONFIG_PROC_FS */