2 * SH3 Setup code for SH7710, SH7712
4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
16 #include <linux/sh_timer.h>
22 /* interrupt sources */
23 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
,
24 DMAC1
, SCIF0
, SCIF1
, DMAC2
, IPSEC
,
25 EDMAC0
, EDMAC1
, EDMAC2
,
32 static struct intc_vect vectors
[] __initdata
= {
33 /* IRQ0->5 are handled in setup-sh3.c */
34 INTC_VECT(DMAC1
, 0x800), INTC_VECT(DMAC1
, 0x820),
35 INTC_VECT(DMAC1
, 0x840), INTC_VECT(DMAC1
, 0x860),
36 INTC_VECT(SCIF0
, 0x880), INTC_VECT(SCIF0
, 0x8a0),
37 INTC_VECT(SCIF0
, 0x8c0), INTC_VECT(SCIF0
, 0x8e0),
38 INTC_VECT(SCIF1
, 0x900), INTC_VECT(SCIF1
, 0x920),
39 INTC_VECT(SCIF1
, 0x940), INTC_VECT(SCIF1
, 0x960),
40 INTC_VECT(DMAC2
, 0xb80), INTC_VECT(DMAC2
, 0xba0),
41 #ifdef CONFIG_CPU_SUBTYPE_SH7710
42 INTC_VECT(IPSEC
, 0xbe0),
44 INTC_VECT(EDMAC0
, 0xc00), INTC_VECT(EDMAC1
, 0xc20),
45 INTC_VECT(EDMAC2
, 0xc40),
46 INTC_VECT(SIOF0
, 0xe00), INTC_VECT(SIOF0
, 0xe20),
47 INTC_VECT(SIOF0
, 0xe40), INTC_VECT(SIOF0
, 0xe60),
48 INTC_VECT(SIOF1
, 0xe80), INTC_VECT(SIOF1
, 0xea0),
49 INTC_VECT(SIOF1
, 0xec0), INTC_VECT(SIOF1
, 0xee0),
50 INTC_VECT(TMU0
, 0x400), INTC_VECT(TMU1
, 0x420),
51 INTC_VECT(TMU2
, 0x440),
52 INTC_VECT(RTC
, 0x480), INTC_VECT(RTC
, 0x4a0),
53 INTC_VECT(RTC
, 0x4c0),
54 INTC_VECT(WDT
, 0x560),
55 INTC_VECT(REF
, 0x580),
58 static struct intc_prio_reg prio_registers
[] __initdata
= {
59 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0
, TMU1
, TMU2
, RTC
} },
60 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT
, REF
, 0, 0 } },
61 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3
, IRQ2
, IRQ1
, IRQ0
} },
62 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5
, IRQ4
} },
63 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1
, SCIF0
, SCIF1
} },
64 { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC
, DMAC2
} },
65 { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0
, EDMAC1
, EDMAC2
} },
66 { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0
} },
67 { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1
} },
70 static DECLARE_INTC_DESC(intc_desc
, "sh7710", vectors
, NULL
,
71 NULL
, prio_registers
, NULL
);
73 static struct resource rtc_resources
[] = {
76 .end
= 0xa413fec0 + 0x1e,
77 .flags
= IORESOURCE_IO
,
81 .flags
= IORESOURCE_IRQ
,
85 static struct sh_rtc_platform_info rtc_info
= {
86 .capabilities
= RTC_CAP_4_DIGIT_YEAR
,
89 static struct platform_device rtc_device
= {
92 .num_resources
= ARRAY_SIZE(rtc_resources
),
93 .resource
= rtc_resources
,
95 .platform_data
= &rtc_info
,
99 static struct plat_sci_port scif0_platform_data
= {
100 .mapbase
= 0xa4400000,
101 .flags
= UPF_BOOT_AUTOCONF
,
102 .scscr
= SCSCR_TE
| SCSCR_RE
| SCSCR_REIE
|
103 SCSCR_CKE1
| SCSCR_CKE0
,
104 .scbrr_algo_id
= SCBRR_ALGO_2
,
106 .irqs
= { 52, 52, 52, 52 },
109 static struct platform_device scif0_device
= {
113 .platform_data
= &scif0_platform_data
,
117 static struct plat_sci_port scif1_platform_data
= {
118 .mapbase
= 0xa4410000,
119 .flags
= UPF_BOOT_AUTOCONF
,
120 .scscr
= SCSCR_TE
| SCSCR_RE
| SCSCR_REIE
|
121 SCSCR_CKE1
| SCSCR_CKE0
,
122 .scbrr_algo_id
= SCBRR_ALGO_2
,
124 .irqs
= { 56, 56, 56, 56 },
127 static struct platform_device scif1_device
= {
131 .platform_data
= &scif1_platform_data
,
135 static struct sh_timer_config tmu0_platform_data
= {
136 .channel_offset
= 0x02,
138 .clockevent_rating
= 200,
141 static struct resource tmu0_resources
[] = {
145 .flags
= IORESOURCE_MEM
,
149 .flags
= IORESOURCE_IRQ
,
153 static struct platform_device tmu0_device
= {
157 .platform_data
= &tmu0_platform_data
,
159 .resource
= tmu0_resources
,
160 .num_resources
= ARRAY_SIZE(tmu0_resources
),
163 static struct sh_timer_config tmu1_platform_data
= {
164 .channel_offset
= 0xe,
166 .clocksource_rating
= 200,
169 static struct resource tmu1_resources
[] = {
173 .flags
= IORESOURCE_MEM
,
177 .flags
= IORESOURCE_IRQ
,
181 static struct platform_device tmu1_device
= {
185 .platform_data
= &tmu1_platform_data
,
187 .resource
= tmu1_resources
,
188 .num_resources
= ARRAY_SIZE(tmu1_resources
),
191 static struct sh_timer_config tmu2_platform_data
= {
192 .channel_offset
= 0x1a,
196 static struct resource tmu2_resources
[] = {
200 .flags
= IORESOURCE_MEM
,
204 .flags
= IORESOURCE_IRQ
,
208 static struct platform_device tmu2_device
= {
212 .platform_data
= &tmu2_platform_data
,
214 .resource
= tmu2_resources
,
215 .num_resources
= ARRAY_SIZE(tmu2_resources
),
218 static struct platform_device
*sh7710_devices
[] __initdata
= {
227 static int __init
sh7710_devices_setup(void)
229 return platform_add_devices(sh7710_devices
,
230 ARRAY_SIZE(sh7710_devices
));
232 arch_initcall(sh7710_devices_setup
);
234 static struct platform_device
*sh7710_early_devices
[] __initdata
= {
242 void __init
plat_early_device_setup(void)
244 early_platform_add_devices(sh7710_early_devices
,
245 ARRAY_SIZE(sh7710_early_devices
));
248 void __init
plat_irq_setup(void)
250 register_intc_controller(&intc_desc
);
251 plat_irq_setup_sh3();