Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / arch / sh / kernel / cpu / sh4a / clock-sh7723.c
blob3cc3827380e3251c1d053c1a8ea8431d49a831b3
1 /*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7723.c
4 * SH7723 clock framework support
6 * Copyright (C) 2009 Magnus Damm
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/clkdev.h>
26 #include <asm/clock.h>
27 #include <asm/hwblk.h>
28 #include <cpu/sh7723.h>
30 /* SH7723 registers */
31 #define FRQCR 0xa4150000
32 #define VCLKCR 0xa4150004
33 #define SCLKACR 0xa4150008
34 #define SCLKBCR 0xa415000c
35 #define IRDACLKCR 0xa4150018
36 #define PLLCR 0xa4150024
37 #define DLLFRQ 0xa4150050
39 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
40 static struct clk r_clk = {
41 .rate = 32768,
45 * Default rate for the root input clock, reset this with clk_set_rate()
46 * from the platform code.
48 struct clk extal_clk = {
49 .rate = 33333333,
52 /* The dll multiplies the 32khz r_clk, may be used instead of extal */
53 static unsigned long dll_recalc(struct clk *clk)
55 unsigned long mult;
57 if (__raw_readl(PLLCR) & 0x1000)
58 mult = __raw_readl(DLLFRQ);
59 else
60 mult = 0;
62 return clk->parent->rate * mult;
65 static struct clk_ops dll_clk_ops = {
66 .recalc = dll_recalc,
69 static struct clk dll_clk = {
70 .ops = &dll_clk_ops,
71 .parent = &r_clk,
72 .flags = CLK_ENABLE_ON_INIT,
75 static unsigned long pll_recalc(struct clk *clk)
77 unsigned long mult = 1;
78 unsigned long div = 1;
80 if (__raw_readl(PLLCR) & 0x4000)
81 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
82 else
83 div = 2;
85 return (clk->parent->rate * mult) / div;
88 static struct clk_ops pll_clk_ops = {
89 .recalc = pll_recalc,
92 static struct clk pll_clk = {
93 .ops = &pll_clk_ops,
94 .flags = CLK_ENABLE_ON_INIT,
97 struct clk *main_clks[] = {
98 &r_clk,
99 &extal_clk,
100 &dll_clk,
101 &pll_clk,
104 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
105 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
107 static struct clk_div_mult_table div4_div_mult_table = {
108 .divisors = divisors,
109 .nr_divisors = ARRAY_SIZE(divisors),
110 .multipliers = multipliers,
111 .nr_multipliers = ARRAY_SIZE(multipliers),
114 static struct clk_div4_table div4_table = {
115 .div_mult_table = &div4_div_mult_table,
118 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
120 #define DIV4(_reg, _bit, _mask, _flags) \
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
123 struct clk div4_clks[DIV4_NR] = {
124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
129 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
132 enum { DIV4_IRDA, DIV4_ENABLE_NR };
134 struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
135 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
138 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
140 struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
141 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
142 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
144 enum { DIV6_V, DIV6_NR };
146 struct clk div6_clks[DIV6_NR] = {
147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
150 static struct clk mstp_clks[] = {
151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
203 static struct clk_lookup lookups[] = {
204 /* main clocks */
205 CLKDEV_CON_ID("rclk", &r_clk),
206 CLKDEV_CON_ID("extal", &extal_clk),
207 CLKDEV_CON_ID("dll_clk", &dll_clk),
208 CLKDEV_CON_ID("pll_clk", &pll_clk),
210 /* DIV4 clocks */
211 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
212 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
213 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
214 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
215 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
216 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
217 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
218 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
219 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
221 /* DIV6 clocks */
222 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
224 /* MSTP clocks */
225 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
226 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
227 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
228 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
229 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
230 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
231 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
232 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
233 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
234 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
235 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
237 /* TMU0 */
238 .dev_id = "sh_tmu.0",
239 .con_id = "tmu_fck",
240 .clk = &mstp_clks[HWBLK_TMU0],
241 }, {
242 /* TMU1 */
243 .dev_id = "sh_tmu.1",
244 .con_id = "tmu_fck",
245 .clk = &mstp_clks[HWBLK_TMU0],
246 }, {
247 /* TMU2 */
248 .dev_id = "sh_tmu.2",
249 .con_id = "tmu_fck",
250 .clk = &mstp_clks[HWBLK_TMU0],
252 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
253 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
254 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
256 /* TMU3 */
257 .dev_id = "sh_tmu.3",
258 .con_id = "tmu_fck",
259 .clk = &mstp_clks[HWBLK_TMU1],
260 }, {
261 /* TMU4 */
262 .dev_id = "sh_tmu.4",
263 .con_id = "tmu_fck",
264 .clk = &mstp_clks[HWBLK_TMU1],
265 }, {
266 /* TMU5 */
267 .dev_id = "sh_tmu.5",
268 .con_id = "tmu_fck",
269 .clk = &mstp_clks[HWBLK_TMU1],
271 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
273 /* SCIF0 */
274 .dev_id = "sh-sci.0",
275 .con_id = "sci_fck",
276 .clk = &mstp_clks[HWBLK_SCIF0],
277 }, {
278 /* SCIF1 */
279 .dev_id = "sh-sci.1",
280 .con_id = "sci_fck",
281 .clk = &mstp_clks[HWBLK_SCIF1],
282 }, {
283 /* SCIF2 */
284 .dev_id = "sh-sci.2",
285 .con_id = "sci_fck",
286 .clk = &mstp_clks[HWBLK_SCIF2],
287 }, {
288 /* SCIF3 */
289 .dev_id = "sh-sci.3",
290 .con_id = "sci_fck",
291 .clk = &mstp_clks[HWBLK_SCIF3],
292 }, {
293 /* SCIF4 */
294 .dev_id = "sh-sci.4",
295 .con_id = "sci_fck",
296 .clk = &mstp_clks[HWBLK_SCIF4],
297 }, {
298 /* SCIF5 */
299 .dev_id = "sh-sci.5",
300 .con_id = "sci_fck",
301 .clk = &mstp_clks[HWBLK_SCIF5],
303 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
304 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
305 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
306 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
307 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
308 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
309 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
310 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
311 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
312 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
313 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
314 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
315 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
316 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
317 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
318 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
319 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
320 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
321 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
322 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
323 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
324 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
325 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
326 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
329 int __init arch_clk_init(void)
331 int k, ret = 0;
333 /* autodetect extal or dll configuration */
334 if (__raw_readl(PLLCR) & 0x1000)
335 pll_clk.parent = &dll_clk;
336 else
337 pll_clk.parent = &extal_clk;
339 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
340 ret |= clk_register(main_clks[k]);
342 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
344 if (!ret)
345 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
347 if (!ret)
348 ret = sh_clk_div4_enable_register(div4_enable_clks,
349 DIV4_ENABLE_NR, &div4_table);
351 if (!ret)
352 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
353 DIV4_REPARENT_NR, &div4_table);
355 if (!ret)
356 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
358 if (!ret)
359 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
361 return ret;