arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
   3  *
   4  * SH7724 hardware block support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <asm/suspend.h>
  25 #include <asm/hwblk.h>
  26 #include <cpu/sh7724.h>
  27
  28 /* SH7724 registers */
  29 #define MSTPCR0         0xa4150030
  30 #define MSTPCR1         0xa4150034
  31 #define MSTPCR2         0xa4150038
  32
  33 /* SH7724 Power Domains */
  34 enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
  35 static struct hwblk_area sh7724_hwblk_area[] = {
  36         [CORE_AREA] = HWBLK_AREA(0, 0),
  37         [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
  38         [SUB_AREA] = HWBLK_AREA(0, 0),
  39 };
  40
  41 /* Table mapping HWBLK to Module Stop Bit and Power Domain */
  42 static struct hwblk sh7724_hwblk[HWBLK_NR] = {
  43         [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
  44         [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
  45         [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
  46         [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
  47         [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
  48         [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
  49         [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
  50         [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
  51         [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
  52         [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
  53         [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
  54         [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
  55         [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
  56         [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
  57         [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
  58         [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
  59         [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
  60         [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
  61         [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
  62         [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
  63         [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
  64         [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
  65         [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
  66         [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
  67         [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
  68         [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
  69
  70         [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
  71         [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
  72         [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
  73         [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
  74
  75         [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
  76         [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
  77         [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
  78         [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
  79         [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
  80         [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
  81         [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
  82         [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
  83         [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
  84         [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
  85         [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
  86         [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
  87         [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
  88         [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
  89         [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
  90         [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
  91         [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
  92         [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
  93         [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
  94         [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
  95         [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
  96         [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
  97         [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
  98 };
  99
 100 static struct hwblk_info sh7724_hwblk_info = {
 101         .areas = sh7724_hwblk_area,
 102         .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
 103         .hwblks = sh7724_hwblk,
 104         .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
 105 };
 106
 107 int arch_hwblk_sleep_mode(void)
 108 {
 109         if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
 110                 return SUSP_SH_STANDBY | SUSP_SH_SF;
 111
 112         if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
 113                 return SUSP_SH_SLEEP | SUSP_SH_SF;
 114
 115         return SUSP_SH_SLEEP;
 116 }
 117
 118 int __init arch_hwblk_init(void)
 119 {
 120         return hwblk_register(&sh7724_hwblk_info);
 121 }