Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / arch / sh / kernel / cpu / sh4a / setup-sh7780.c
blob3d4d2075c19ad334ac40b8803b8e7ecffced0a96
1 /*
2 * SH7780 Setup
4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/io.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_dma.h>
16 #include <linux/sh_timer.h>
17 #include <cpu/dma-register.h>
19 static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe00000,
21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
23 .scbrr_algo_id = SCBRR_ALGO_1,
24 .type = PORT_SCIF,
25 .irqs = { 40, 40, 40, 40 },
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
29 static struct platform_device scif0_device = {
30 .name = "sh-sci",
31 .id = 0,
32 .dev = {
33 .platform_data = &scif0_platform_data,
37 static struct plat_sci_port scif1_platform_data = {
38 .mapbase = 0xffe10000,
39 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_1,
42 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 },
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47 static struct platform_device scif1_device = {
48 .name = "sh-sci",
49 .id = 1,
50 .dev = {
51 .platform_data = &scif1_platform_data,
55 static struct sh_timer_config tmu0_platform_data = {
56 .channel_offset = 0x04,
57 .timer_bit = 0,
58 .clockevent_rating = 200,
61 static struct resource tmu0_resources[] = {
62 [0] = {
63 .start = 0xffd80008,
64 .end = 0xffd80013,
65 .flags = IORESOURCE_MEM,
67 [1] = {
68 .start = 28,
69 .flags = IORESOURCE_IRQ,
73 static struct platform_device tmu0_device = {
74 .name = "sh_tmu",
75 .id = 0,
76 .dev = {
77 .platform_data = &tmu0_platform_data,
79 .resource = tmu0_resources,
80 .num_resources = ARRAY_SIZE(tmu0_resources),
83 static struct sh_timer_config tmu1_platform_data = {
84 .channel_offset = 0x10,
85 .timer_bit = 1,
86 .clocksource_rating = 200,
89 static struct resource tmu1_resources[] = {
90 [0] = {
91 .start = 0xffd80014,
92 .end = 0xffd8001f,
93 .flags = IORESOURCE_MEM,
95 [1] = {
96 .start = 29,
97 .flags = IORESOURCE_IRQ,
101 static struct platform_device tmu1_device = {
102 .name = "sh_tmu",
103 .id = 1,
104 .dev = {
105 .platform_data = &tmu1_platform_data,
107 .resource = tmu1_resources,
108 .num_resources = ARRAY_SIZE(tmu1_resources),
111 static struct sh_timer_config tmu2_platform_data = {
112 .channel_offset = 0x1c,
113 .timer_bit = 2,
116 static struct resource tmu2_resources[] = {
117 [0] = {
118 .start = 0xffd80020,
119 .end = 0xffd8002f,
120 .flags = IORESOURCE_MEM,
122 [1] = {
123 .start = 30,
124 .flags = IORESOURCE_IRQ,
128 static struct platform_device tmu2_device = {
129 .name = "sh_tmu",
130 .id = 2,
131 .dev = {
132 .platform_data = &tmu2_platform_data,
134 .resource = tmu2_resources,
135 .num_resources = ARRAY_SIZE(tmu2_resources),
138 static struct sh_timer_config tmu3_platform_data = {
139 .channel_offset = 0x04,
140 .timer_bit = 0,
143 static struct resource tmu3_resources[] = {
144 [0] = {
145 .start = 0xffdc0008,
146 .end = 0xffdc0013,
147 .flags = IORESOURCE_MEM,
149 [1] = {
150 .start = 96,
151 .flags = IORESOURCE_IRQ,
155 static struct platform_device tmu3_device = {
156 .name = "sh_tmu",
157 .id = 3,
158 .dev = {
159 .platform_data = &tmu3_platform_data,
161 .resource = tmu3_resources,
162 .num_resources = ARRAY_SIZE(tmu3_resources),
165 static struct sh_timer_config tmu4_platform_data = {
166 .channel_offset = 0x10,
167 .timer_bit = 1,
170 static struct resource tmu4_resources[] = {
171 [0] = {
172 .start = 0xffdc0014,
173 .end = 0xffdc001f,
174 .flags = IORESOURCE_MEM,
176 [1] = {
177 .start = 97,
178 .flags = IORESOURCE_IRQ,
182 static struct platform_device tmu4_device = {
183 .name = "sh_tmu",
184 .id = 4,
185 .dev = {
186 .platform_data = &tmu4_platform_data,
188 .resource = tmu4_resources,
189 .num_resources = ARRAY_SIZE(tmu4_resources),
192 static struct sh_timer_config tmu5_platform_data = {
193 .channel_offset = 0x1c,
194 .timer_bit = 2,
197 static struct resource tmu5_resources[] = {
198 [0] = {
199 .start = 0xffdc0020,
200 .end = 0xffdc002b,
201 .flags = IORESOURCE_MEM,
203 [1] = {
204 .start = 98,
205 .flags = IORESOURCE_IRQ,
209 static struct platform_device tmu5_device = {
210 .name = "sh_tmu",
211 .id = 5,
212 .dev = {
213 .platform_data = &tmu5_platform_data,
215 .resource = tmu5_resources,
216 .num_resources = ARRAY_SIZE(tmu5_resources),
219 static struct resource rtc_resources[] = {
220 [0] = {
221 .start = 0xffe80000,
222 .end = 0xffe80000 + 0x58 - 1,
223 .flags = IORESOURCE_IO,
225 [1] = {
226 /* Shared Period/Carry/Alarm IRQ */
227 .start = 20,
228 .flags = IORESOURCE_IRQ,
232 static struct platform_device rtc_device = {
233 .name = "sh-rtc",
234 .id = -1,
235 .num_resources = ARRAY_SIZE(rtc_resources),
236 .resource = rtc_resources,
239 /* DMA */
240 static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
242 .offset = 0,
243 .dmars = 0,
244 .dmars_bit = 0,
245 }, {
246 .offset = 0x10,
247 .dmars = 0,
248 .dmars_bit = 8,
249 }, {
250 .offset = 0x20,
251 .dmars = 4,
252 .dmars_bit = 0,
253 }, {
254 .offset = 0x30,
255 .dmars = 4,
256 .dmars_bit = 8,
257 }, {
258 .offset = 0x50,
259 .dmars = 8,
260 .dmars_bit = 0,
261 }, {
262 .offset = 0x60,
263 .dmars = 8,
264 .dmars_bit = 8,
268 static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
270 .offset = 0,
271 }, {
272 .offset = 0x10,
273 }, {
274 .offset = 0x20,
275 }, {
276 .offset = 0x30,
277 }, {
278 .offset = 0x50,
279 }, {
280 .offset = 0x60,
284 static const unsigned int ts_shift[] = TS_SHIFT;
286 static struct sh_dmae_pdata dma0_platform_data = {
287 .channel = sh7780_dmae0_channels,
288 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
289 .ts_low_shift = CHCR_TS_LOW_SHIFT,
290 .ts_low_mask = CHCR_TS_LOW_MASK,
291 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
292 .ts_high_mask = CHCR_TS_HIGH_MASK,
293 .ts_shift = ts_shift,
294 .ts_shift_num = ARRAY_SIZE(ts_shift),
295 .dmaor_init = DMAOR_INIT,
298 static struct sh_dmae_pdata dma1_platform_data = {
299 .channel = sh7780_dmae1_channels,
300 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
301 .ts_low_shift = CHCR_TS_LOW_SHIFT,
302 .ts_low_mask = CHCR_TS_LOW_MASK,
303 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
304 .ts_high_mask = CHCR_TS_HIGH_MASK,
305 .ts_shift = ts_shift,
306 .ts_shift_num = ARRAY_SIZE(ts_shift),
307 .dmaor_init = DMAOR_INIT,
310 static struct resource sh7780_dmae0_resources[] = {
311 [0] = {
312 /* Channel registers and DMAOR */
313 .start = 0xfc808020,
314 .end = 0xfc80808f,
315 .flags = IORESOURCE_MEM,
317 [1] = {
318 /* DMARSx */
319 .start = 0xfc809000,
320 .end = 0xfc80900b,
321 .flags = IORESOURCE_MEM,
324 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
325 .start = 34,
326 .end = 34,
327 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
331 static struct resource sh7780_dmae1_resources[] = {
332 [0] = {
333 /* Channel registers and DMAOR */
334 .start = 0xfc818020,
335 .end = 0xfc81808f,
336 .flags = IORESOURCE_MEM,
338 /* DMAC1 has no DMARS */
340 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
341 .start = 46,
342 .end = 46,
343 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
347 static struct platform_device dma0_device = {
348 .name = "sh-dma-engine",
349 .id = 0,
350 .resource = sh7780_dmae0_resources,
351 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
352 .dev = {
353 .platform_data = &dma0_platform_data,
357 static struct platform_device dma1_device = {
358 .name = "sh-dma-engine",
359 .id = 1,
360 .resource = sh7780_dmae1_resources,
361 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
362 .dev = {
363 .platform_data = &dma1_platform_data,
367 static struct platform_device *sh7780_devices[] __initdata = {
368 &scif0_device,
369 &scif1_device,
370 &tmu0_device,
371 &tmu1_device,
372 &tmu2_device,
373 &tmu3_device,
374 &tmu4_device,
375 &tmu5_device,
376 &rtc_device,
377 &dma0_device,
378 &dma1_device,
381 static int __init sh7780_devices_setup(void)
383 return platform_add_devices(sh7780_devices,
384 ARRAY_SIZE(sh7780_devices));
386 arch_initcall(sh7780_devices_setup);
388 static struct platform_device *sh7780_early_devices[] __initdata = {
389 &scif0_device,
390 &scif1_device,
391 &tmu0_device,
392 &tmu1_device,
393 &tmu2_device,
394 &tmu3_device,
395 &tmu4_device,
396 &tmu5_device,
399 void __init plat_early_device_setup(void)
401 if (mach_is_sh2007()) {
402 scif0_platform_data.scscr &= ~SCSCR_CKE1;
403 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
404 scif1_platform_data.scscr &= ~SCSCR_CKE1;
405 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
408 early_platform_add_devices(sh7780_early_devices,
409 ARRAY_SIZE(sh7780_early_devices));
412 enum {
413 UNUSED = 0,
415 /* interrupt sources */
417 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
418 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
419 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
420 IRL_HHLL, IRL_HHLH, IRL_HHHL,
422 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
423 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
424 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
425 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
426 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
428 /* interrupt groups */
430 TMU012, TMU345,
433 static struct intc_vect vectors[] __initdata = {
434 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
435 INTC_VECT(RTC, 0x4c0),
436 INTC_VECT(WDT, 0x560),
437 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
438 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
439 INTC_VECT(HUDI, 0x600),
440 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
441 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
442 INTC_VECT(DMAC0, 0x6c0),
443 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
444 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
445 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
446 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
447 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
448 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
449 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
450 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
451 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
452 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
453 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
454 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
455 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
456 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
457 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
458 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
459 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
460 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
461 INTC_VECT(TMU5, 0xe40),
462 INTC_VECT(SSI, 0xe80),
463 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
464 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
465 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
466 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
469 static struct intc_group groups[] __initdata = {
470 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
471 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
474 static struct intc_mask_reg mask_registers[] __initdata = {
475 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
476 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
477 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
478 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
479 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
482 static struct intc_prio_reg prio_registers[] __initdata = {
483 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
484 TMU2, TMU2_TICPI } },
485 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
486 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
487 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
488 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
489 PCISERR, PCIINTA, } },
490 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
491 PCIINTD, PCIC5 } },
492 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
493 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
496 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
497 mask_registers, prio_registers, NULL);
499 /* Support for external interrupt pins in IRQ mode */
501 static struct intc_vect irq_vectors[] __initdata = {
502 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
503 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
504 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
505 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
508 static struct intc_mask_reg irq_mask_registers[] __initdata = {
509 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
510 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
513 static struct intc_prio_reg irq_prio_registers[] __initdata = {
514 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
515 IRQ4, IRQ5, IRQ6, IRQ7 } },
518 static struct intc_sense_reg irq_sense_registers[] __initdata = {
519 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
520 IRQ4, IRQ5, IRQ6, IRQ7 } },
523 static struct intc_mask_reg irq_ack_registers[] __initdata = {
524 { 0xffd00024, 0, 32, /* INTREQ */
525 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
528 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
529 NULL, irq_mask_registers, irq_prio_registers,
530 irq_sense_registers, irq_ack_registers);
532 /* External interrupt pins in IRL mode */
534 static struct intc_vect irl_vectors[] __initdata = {
535 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
536 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
537 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
538 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
539 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
540 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
541 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
542 INTC_VECT(IRL_HHHL, 0x3c0),
545 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
546 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
547 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
548 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
549 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
550 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
553 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
554 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
555 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
556 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
557 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
558 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
559 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
562 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
563 NULL, irl7654_mask_registers, NULL, NULL);
565 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
566 NULL, irl3210_mask_registers, NULL, NULL);
568 #define INTC_ICR0 0xffd00000
569 #define INTC_INTMSK0 0xffd00044
570 #define INTC_INTMSK1 0xffd00048
571 #define INTC_INTMSK2 0xffd40080
572 #define INTC_INTMSKCLR1 0xffd00068
573 #define INTC_INTMSKCLR2 0xffd40084
575 void __init plat_irq_setup(void)
577 /* disable IRQ7-0 */
578 __raw_writel(0xff000000, INTC_INTMSK0);
580 /* disable IRL3-0 + IRL7-4 */
581 __raw_writel(0xc0000000, INTC_INTMSK1);
582 __raw_writel(0xfffefffe, INTC_INTMSK2);
584 /* select IRL mode for IRL3-0 + IRL7-4 */
585 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
587 /* disable holding function, ie enable "SH-4 Mode" */
588 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
590 register_intc_controller(&intc_desc);
593 void __init plat_irq_setup_pins(int mode)
595 switch (mode) {
596 case IRQ_MODE_IRQ:
597 /* select IRQ mode for IRL3-0 + IRL7-4 */
598 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
599 register_intc_controller(&intc_irq_desc);
600 break;
601 case IRQ_MODE_IRL7654:
602 /* enable IRL7-4 but don't provide any masking */
603 __raw_writel(0x40000000, INTC_INTMSKCLR1);
604 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
605 break;
606 case IRQ_MODE_IRL3210:
607 /* enable IRL0-3 but don't provide any masking */
608 __raw_writel(0x80000000, INTC_INTMSKCLR1);
609 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
610 break;
611 case IRQ_MODE_IRL7654_MASK:
612 /* enable IRL7-4 and mask using cpu intc controller */
613 __raw_writel(0x40000000, INTC_INTMSKCLR1);
614 register_intc_controller(&intc_irl7654_desc);
615 break;
616 case IRQ_MODE_IRL3210_MASK:
617 /* enable IRL0-3 and mask using cpu intc controller */
618 __raw_writel(0x80000000, INTC_INTMSKCLR1);
619 register_intc_controller(&intc_irl3210_desc);
620 break;
621 default:
622 BUG();