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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / arch / x86 / include / asm / uv / uv_mmrs.h
blob10474fb1185df7e30f52101cea4e358a18e39458
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2011 Silicon Graphics, Inc. All rights reserved.
9 */
10
11 #ifndef _ASM_X86_UV_UV_MMRS_H
12 #define _ASM_X86_UV_UV_MMRS_H
13
14 /*
15 * This file contains MMR definitions for both UV1 & UV2 hubs.
16 *
17 * In general, MMR addresses and structures are identical on both hubs.
18 * These MMRs are identified as:
19 * #define UVH_xxx <address>
20 * union uvh_xxx {
21 * unsigned long v;
22 * struct uvh_int_cmpd_s {
23 * } s;
24 * };
25 *
26 * If the MMR exists on both hub type but has different addresses or
27 * contents, the MMR definition is similar to:
28 * #define UV1H_xxx <uv1 address>
29 * #define UV2H_xxx <uv2address>
30 * #define UVH_xxx (is_uv1_hub() ? UV1H_xxx : UV2H_xxx)
31 * union uvh_xxx {
32 * unsigned long v;
33 * struct uv1h_int_cmpd_s { (Common fields only)
34 * } s;
35 * struct uv1h_int_cmpd_s { (Full UV1 definition)
36 * } s1;
37 * struct uv2h_int_cmpd_s { (Full UV2 definition)
38 * } s2;
39 * };
40 *
41 * Only essential difference are enumerated. For example, if the address is
42 * the same for both UV1 & UV2, only a single #define is generated. Likewise,
43 * if the contents is the same for both hubs, only the "s" structure is
44 * generated.
45 *
46 * If the MMR exists on ONLY 1 type of hub, no generic definition is
47 * generated:
48 * #define UVnH_xxx <uvn address>
49 * union uvnh_xxx {
50 * unsigned long v;
51 * struct uvh_int_cmpd_s {
52 * } sn;
53 * };
54 */
55
56 #define UV_MMR_ENABLE (1UL << 63)
57
58 #define UV1_HUB_PART_NUMBER 0x88a5
59 #define UV2_HUB_PART_NUMBER 0x8eb8
60
61 /* Compat: if this #define is present, UV headers support UV2 */
62 #define UV2_HUB_IS_SUPPORTED 1
63
64 /* ========================================================================= */
65 /* UVH_BAU_DATA_BROADCAST */
66 /* ========================================================================= */
67 #define UVH_BAU_DATA_BROADCAST 0x61688UL
68 #define UVH_BAU_DATA_BROADCAST_32 0x440
69
70 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
71 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
72
73 union uvh_bau_data_broadcast_u {
74 unsigned long v;
75 struct uvh_bau_data_broadcast_s {
76 unsigned long enable:1; /* RW */
77 unsigned long rsvd_1_63:63;
78 } s;
79 };
80
81 /* ========================================================================= */
82 /* UVH_BAU_DATA_CONFIG */
83 /* ========================================================================= */
84 #define UVH_BAU_DATA_CONFIG 0x61680UL
85 #define UVH_BAU_DATA_CONFIG_32 0x438
86
87 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
88 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8
89 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
90 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
91 #define UVH_BAU_DATA_CONFIG_P_SHFT 13
92 #define UVH_BAU_DATA_CONFIG_T_SHFT 15
93 #define UVH_BAU_DATA_CONFIG_M_SHFT 16
94 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
95 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
96 #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
97 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
98 #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
99 #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
100 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
101 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
102 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
103
104 union uvh_bau_data_config_u {
105 unsigned long v;
106 struct uvh_bau_data_config_s {
107 unsigned long vector_:8; /* RW */
108 unsigned long dm:3; /* RW */
109 unsigned long destmode:1; /* RW */
110 unsigned long status:1; /* RO */
111 unsigned long p:1; /* RO */
112 unsigned long rsvd_14:1;
113 unsigned long t:1; /* RO */
114 unsigned long m:1; /* RW */
115 unsigned long rsvd_17_31:15;
116 unsigned long apic_id:32; /* RW */
117 } s;
118 };
119
120 /* ========================================================================= */
121 /* UVH_EVENT_OCCURRED0 */
122 /* ========================================================================= */
123 #define UVH_EVENT_OCCURRED0 0x70000UL
124 #define UVH_EVENT_OCCURRED0_32 0x5e8
125
126 #define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
127 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
128 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
129 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
130 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4
131 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5
132 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6
133 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
134 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
135 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
136 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
137 #define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
138 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
139 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
140 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
141 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
142 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
143 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
144 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
145 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
146 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
147 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
148 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
149 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
150 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
151 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
152 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
153 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
154 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
155 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
156 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
157 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
158 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
159 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
160 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
161 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
162 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
163 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
164 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
165 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
166 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
167 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
168 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
169 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43
170 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
171 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45
172 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
173 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
174 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
175 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
176 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
177 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51
178 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52
179 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53
180 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
181 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
182 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
183 #define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
184 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
185 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
186 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
187 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
188 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
189 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
190 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
191 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
192 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
193 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
194 #define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
195 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
196 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
197 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
198 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
199 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
200 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
201 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
202 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
203 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
204 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
205 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
206 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
207 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
208 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
209 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
210 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
211 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
212 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
213 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
214 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
215 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
216 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
217 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
218 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
219 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
220 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
221 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
222 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
223 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
224 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
225 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
226 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
227 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
228 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
229 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
230 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
231 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
232 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
233 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
234 #define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
235 #define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
236 #define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
237 #define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
238 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
239 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
240
241 #define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
242 #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
243 #define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
244 #define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
245 #define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
246 #define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
247 #define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
248 #define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
249 #define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
250 #define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
251 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
252 #define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
253 #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
254 #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
255 #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
256 #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
257 #define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
258 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
259 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
260 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
261 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
262 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
263 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
264 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
265 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
266 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
267 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
268 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
269 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
270 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
271 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
272 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
273 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
274 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
275 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
276 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
277 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
278 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
279 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
280 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
281 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
282 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
283 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
284 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
285 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
286 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
287 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
288 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
289 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
290 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
291 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
292 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
293 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
294 #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
295 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
296 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
297 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
298 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
299 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
300 #define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
301 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
302 #define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
303 #define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
304 #define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
305 #define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
306 #define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
307 #define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
308 #define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
309 #define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
310 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
311 #define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
312 #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
313 #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
314 #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
315 #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
316 #define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
317 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
318 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
319 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
320 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
321 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
322 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
323 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
324 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
325 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
326 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
327 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
328 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
329 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
330 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
331 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
332 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
333 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
334 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
335 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
336 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
337 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
338 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
339 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
340 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
341 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
342 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
343 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
344 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
345 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
346 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
347 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
348 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
349 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
350 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
351 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
352 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
353 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
354 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
355 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
356 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
357 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
358 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
359
360 union uvh_event_occurred0_u {
361 unsigned long v;
362 struct uv1h_event_occurred0_s {
363 unsigned long lb_hcerr:1; /* RW, W1C */
364 unsigned long gr0_hcerr:1; /* RW, W1C */
365 unsigned long gr1_hcerr:1; /* RW, W1C */
366 unsigned long lh_hcerr:1; /* RW, W1C */
367 unsigned long rh_hcerr:1; /* RW, W1C */
368 unsigned long xn_hcerr:1; /* RW, W1C */
369 unsigned long si_hcerr:1; /* RW, W1C */
370 unsigned long lb_aoerr0:1; /* RW, W1C */
371 unsigned long gr0_aoerr0:1; /* RW, W1C */
372 unsigned long gr1_aoerr0:1; /* RW, W1C */
373 unsigned long lh_aoerr0:1; /* RW, W1C */
374 unsigned long rh_aoerr0:1; /* RW, W1C */
375 unsigned long xn_aoerr0:1; /* RW, W1C */
376 unsigned long si_aoerr0:1; /* RW, W1C */
377 unsigned long lb_aoerr1:1; /* RW, W1C */
378 unsigned long gr0_aoerr1:1; /* RW, W1C */
379 unsigned long gr1_aoerr1:1; /* RW, W1C */
380 unsigned long lh_aoerr1:1; /* RW, W1C */
381 unsigned long rh_aoerr1:1; /* RW, W1C */
382 unsigned long xn_aoerr1:1; /* RW, W1C */
383 unsigned long si_aoerr1:1; /* RW, W1C */
384 unsigned long rh_vpi_int:1; /* RW, W1C */
385 unsigned long system_shutdown_int:1; /* RW, W1C */
386 unsigned long lb_irq_int_0:1; /* RW, W1C */
387 unsigned long lb_irq_int_1:1; /* RW, W1C */
388 unsigned long lb_irq_int_2:1; /* RW, W1C */
389 unsigned long lb_irq_int_3:1; /* RW, W1C */
390 unsigned long lb_irq_int_4:1; /* RW, W1C */
391 unsigned long lb_irq_int_5:1; /* RW, W1C */
392 unsigned long lb_irq_int_6:1; /* RW, W1C */
393 unsigned long lb_irq_int_7:1; /* RW, W1C */
394 unsigned long lb_irq_int_8:1; /* RW, W1C */
395 unsigned long lb_irq_int_9:1; /* RW, W1C */
396 unsigned long lb_irq_int_10:1; /* RW, W1C */
397 unsigned long lb_irq_int_11:1; /* RW, W1C */
398 unsigned long lb_irq_int_12:1; /* RW, W1C */
399 unsigned long lb_irq_int_13:1; /* RW, W1C */
400 unsigned long lb_irq_int_14:1; /* RW, W1C */
401 unsigned long lb_irq_int_15:1; /* RW, W1C */
402 unsigned long l1_nmi_int:1; /* RW, W1C */
403 unsigned long stop_clock:1; /* RW, W1C */
404 unsigned long asic_to_l1:1; /* RW, W1C */
405 unsigned long l1_to_asic:1; /* RW, W1C */
406 unsigned long ltc_int:1; /* RW, W1C */
407 unsigned long la_seq_trigger:1; /* RW, W1C */
408 unsigned long ipi_int:1; /* RW, W1C */
409 unsigned long extio_int0:1; /* RW, W1C */
410 unsigned long extio_int1:1; /* RW, W1C */
411 unsigned long extio_int2:1; /* RW, W1C */
412 unsigned long extio_int3:1; /* RW, W1C */
413 unsigned long profile_int:1; /* RW, W1C */
414 unsigned long rtc0:1; /* RW, W1C */
415 unsigned long rtc1:1; /* RW, W1C */
416 unsigned long rtc2:1; /* RW, W1C */
417 unsigned long rtc3:1; /* RW, W1C */
418 unsigned long bau_data:1; /* RW, W1C */
419 unsigned long power_management_req:1; /* RW, W1C */
420 unsigned long rsvd_57_63:7;
421 } s1;
422 struct uv2h_event_occurred0_s {
423 unsigned long lb_hcerr:1; /* RW */
424 unsigned long qp_hcerr:1; /* RW */
425 unsigned long rh_hcerr:1; /* RW */
426 unsigned long lh0_hcerr:1; /* RW */
427 unsigned long lh1_hcerr:1; /* RW */
428 unsigned long gr0_hcerr:1; /* RW */
429 unsigned long gr1_hcerr:1; /* RW */
430 unsigned long ni0_hcerr:1; /* RW */
431 unsigned long ni1_hcerr:1; /* RW */
432 unsigned long lb_aoerr0:1; /* RW */
433 unsigned long qp_aoerr0:1; /* RW */
434 unsigned long rh_aoerr0:1; /* RW */
435 unsigned long lh0_aoerr0:1; /* RW */
436 unsigned long lh1_aoerr0:1; /* RW */
437 unsigned long gr0_aoerr0:1; /* RW */
438 unsigned long gr1_aoerr0:1; /* RW */
439 unsigned long xb_aoerr0:1; /* RW */
440 unsigned long rt_aoerr0:1; /* RW */
441 unsigned long ni0_aoerr0:1; /* RW */
442 unsigned long ni1_aoerr0:1; /* RW */
443 unsigned long lb_aoerr1:1; /* RW */
444 unsigned long qp_aoerr1:1; /* RW */
445 unsigned long rh_aoerr1:1; /* RW */
446 unsigned long lh0_aoerr1:1; /* RW */
447 unsigned long lh1_aoerr1:1; /* RW */
448 unsigned long gr0_aoerr1:1; /* RW */
449 unsigned long gr1_aoerr1:1; /* RW */
450 unsigned long xb_aoerr1:1; /* RW */
451 unsigned long rt_aoerr1:1; /* RW */
452 unsigned long ni0_aoerr1:1; /* RW */
453 unsigned long ni1_aoerr1:1; /* RW */
454 unsigned long system_shutdown_int:1; /* RW */
455 unsigned long lb_irq_int_0:1; /* RW */
456 unsigned long lb_irq_int_1:1; /* RW */
457 unsigned long lb_irq_int_2:1; /* RW */
458 unsigned long lb_irq_int_3:1; /* RW */
459 unsigned long lb_irq_int_4:1; /* RW */
460 unsigned long lb_irq_int_5:1; /* RW */
461 unsigned long lb_irq_int_6:1; /* RW */
462 unsigned long lb_irq_int_7:1; /* RW */
463 unsigned long lb_irq_int_8:1; /* RW */
464 unsigned long lb_irq_int_9:1; /* RW */
465 unsigned long lb_irq_int_10:1; /* RW */
466 unsigned long lb_irq_int_11:1; /* RW */
467 unsigned long lb_irq_int_12:1; /* RW */
468 unsigned long lb_irq_int_13:1; /* RW */
469 unsigned long lb_irq_int_14:1; /* RW */
470 unsigned long lb_irq_int_15:1; /* RW */
471 unsigned long l1_nmi_int:1; /* RW */
472 unsigned long stop_clock:1; /* RW */
473 unsigned long asic_to_l1:1; /* RW */
474 unsigned long l1_to_asic:1; /* RW */
475 unsigned long la_seq_trigger:1; /* RW */
476 unsigned long ipi_int:1; /* RW */
477 unsigned long extio_int0:1; /* RW */
478 unsigned long extio_int1:1; /* RW */
479 unsigned long extio_int2:1; /* RW */
480 unsigned long extio_int3:1; /* RW */
481 unsigned long profile_int:1; /* RW */
482 unsigned long rsvd_59_63:5;
483 } s2;
484 };
485
486 /* ========================================================================= */
487 /* UVH_EVENT_OCCURRED0_ALIAS */
488 /* ========================================================================= */
489 #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
490 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
491
492 /* ========================================================================= */
493 /* UVH_GR0_TLB_INT0_CONFIG */
494 /* ========================================================================= */
495 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
496
497 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
498 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
499 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
500 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
501 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
502 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
503 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
504 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
505 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
506 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
507 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
508 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
509 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
510 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
511 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
512 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
513
514 union uvh_gr0_tlb_int0_config_u {
515 unsigned long v;
516 struct uvh_gr0_tlb_int0_config_s {
517 unsigned long vector_:8; /* RW */
518 unsigned long dm:3; /* RW */
519 unsigned long destmode:1; /* RW */
520 unsigned long status:1; /* RO */
521 unsigned long p:1; /* RO */
522 unsigned long rsvd_14:1;
523 unsigned long t:1; /* RO */
524 unsigned long m:1; /* RW */
525 unsigned long rsvd_17_31:15;
526 unsigned long apic_id:32; /* RW */
527 } s;
528 };
529
530 /* ========================================================================= */
531 /* UVH_GR0_TLB_INT1_CONFIG */
532 /* ========================================================================= */
533 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
534
535 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
536 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
537 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
538 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
539 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
540 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
541 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
542 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
543 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
544 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
545 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
546 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
547 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
548 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
549 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
550 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
551
552 union uvh_gr0_tlb_int1_config_u {
553 unsigned long v;
554 struct uvh_gr0_tlb_int1_config_s {
555 unsigned long vector_:8; /* RW */
556 unsigned long dm:3; /* RW */
557 unsigned long destmode:1; /* RW */
558 unsigned long status:1; /* RO */
559 unsigned long p:1; /* RO */
560 unsigned long rsvd_14:1;
561 unsigned long t:1; /* RO */
562 unsigned long m:1; /* RW */
563 unsigned long rsvd_17_31:15;
564 unsigned long apic_id:32; /* RW */
565 } s;
566 };
567
568 /* ========================================================================= */
569 /* UVH_GR0_TLB_MMR_CONTROL */
570 /* ========================================================================= */
571 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
572 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
573 #define UVH_GR0_TLB_MMR_CONTROL (is_uv1_hub() ? \
574 UV1H_GR0_TLB_MMR_CONTROL : \
575 UV2H_GR0_TLB_MMR_CONTROL)
576
577 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
578 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
579 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
580 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
581 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
582 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
583 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
584 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
585 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
586 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
587 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
588 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
589
590 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
591 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
592 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
593 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
594 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
595 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
596 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
597 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
598 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
599 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56
600 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60
601 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
602 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
603 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
604 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
605 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
606 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
607 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
608 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
609 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
610 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL
611 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL
612
613 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
614 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
615 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
616 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
617 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
618 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
619 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
620 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
621 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
622 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
623 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
624 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
625 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
626 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
627 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
628 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
629 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
630 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
631
632 union uvh_gr0_tlb_mmr_control_u {
633 unsigned long v;
634 struct uvh_gr0_tlb_mmr_control_s {
635 unsigned long index:12; /* RW */
636 unsigned long mem_sel:2; /* RW */
637 unsigned long rsvd_14_15:2;
638 unsigned long auto_valid_en:1; /* RW */
639 unsigned long rsvd_17_19:3;
640 unsigned long mmr_hash_index_en:1; /* RW */
641 unsigned long rsvd_21_29:9;
642 unsigned long mmr_write:1; /* WP */
643 unsigned long mmr_read:1; /* WP */
644 unsigned long rsvd_32_63:32;
645 } s;
646 struct uv1h_gr0_tlb_mmr_control_s {
647 unsigned long index:12; /* RW */
648 unsigned long mem_sel:2; /* RW */
649 unsigned long rsvd_14_15:2;
650 unsigned long auto_valid_en:1; /* RW */
651 unsigned long rsvd_17_19:3;
652 unsigned long mmr_hash_index_en:1; /* RW */
653 unsigned long rsvd_21_29:9;
654 unsigned long mmr_write:1; /* WP */
655 unsigned long mmr_read:1; /* WP */
656 unsigned long rsvd_32_47:16;
657 unsigned long mmr_inj_con:1; /* RW */
658 unsigned long rsvd_49_51:3;
659 unsigned long mmr_inj_tlbram:1; /* RW */
660 unsigned long rsvd_53:1;
661 unsigned long mmr_inj_tlbpgsize:1; /* RW */
662 unsigned long rsvd_55:1;
663 unsigned long mmr_inj_tlbrreg:1; /* RW */
664 unsigned long rsvd_57_59:3;
665 unsigned long mmr_inj_tlblruv:1; /* RW */
666 unsigned long rsvd_61_63:3;
667 } s1;
668 struct uv2h_gr0_tlb_mmr_control_s {
669 unsigned long index:12; /* RW */
670 unsigned long mem_sel:2; /* RW */
671 unsigned long rsvd_14_15:2;
672 unsigned long auto_valid_en:1; /* RW */
673 unsigned long rsvd_17_19:3;
674 unsigned long mmr_hash_index_en:1; /* RW */
675 unsigned long rsvd_21_29:9;
676 unsigned long mmr_write:1; /* WP */
677 unsigned long mmr_read:1; /* WP */
678 unsigned long mmr_op_done:1; /* RW */
679 unsigned long rsvd_33_47:15;
680 unsigned long mmr_inj_con:1; /* RW */
681 unsigned long rsvd_49_51:3;
682 unsigned long mmr_inj_tlbram:1; /* RW */
683 unsigned long rsvd_53_63:11;
684 } s2;
685 };
686
687 /* ========================================================================= */
688 /* UVH_GR0_TLB_MMR_READ_DATA_HI */
689 /* ========================================================================= */
690 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
691 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
692 #define UVH_GR0_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \
693 UV1H_GR0_TLB_MMR_READ_DATA_HI : \
694 UV2H_GR0_TLB_MMR_READ_DATA_HI)
695
696 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
697 #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
698 #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
699 #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
700 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
701 #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
702 #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
703 #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
704
705 union uvh_gr0_tlb_mmr_read_data_hi_u {
706 unsigned long v;
707 struct uvh_gr0_tlb_mmr_read_data_hi_s {
708 unsigned long pfn:41; /* RO */
709 unsigned long gaa:2; /* RO */
710 unsigned long dirty:1; /* RO */
711 unsigned long larger:1; /* RO */
712 unsigned long rsvd_45_63:19;
713 } s;
714 };
715
716 /* ========================================================================= */
717 /* UVH_GR0_TLB_MMR_READ_DATA_LO */
718 /* ========================================================================= */
719 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
720 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
721 #define UVH_GR0_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \
722 UV1H_GR0_TLB_MMR_READ_DATA_LO : \
723 UV2H_GR0_TLB_MMR_READ_DATA_LO)
724
725 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
726 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
727 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63
728 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL
729 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
730 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
731
732 union uvh_gr0_tlb_mmr_read_data_lo_u {
733 unsigned long v;
734 struct uvh_gr0_tlb_mmr_read_data_lo_s {
735 unsigned long vpn:39; /* RO */
736 unsigned long asid:24; /* RO */
737 unsigned long valid:1; /* RO */
738 } s;
739 };
740
741 /* ========================================================================= */
742 /* UVH_GR1_TLB_INT0_CONFIG */
743 /* ========================================================================= */
744 #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
745
746 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
747 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
748 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
749 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
750 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
751 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
752 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
753 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
754 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
755 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
756 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
757 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
758 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
759 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
760 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
761 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
762
763 union uvh_gr1_tlb_int0_config_u {
764 unsigned long v;
765 struct uvh_gr1_tlb_int0_config_s {
766 unsigned long vector_:8; /* RW */
767 unsigned long dm:3; /* RW */
768 unsigned long destmode:1; /* RW */
769 unsigned long status:1; /* RO */
770 unsigned long p:1; /* RO */
771 unsigned long rsvd_14:1;
772 unsigned long t:1; /* RO */
773 unsigned long m:1; /* RW */
774 unsigned long rsvd_17_31:15;
775 unsigned long apic_id:32; /* RW */
776 } s;
777 };
778
779 /* ========================================================================= */
780 /* UVH_GR1_TLB_INT1_CONFIG */
781 /* ========================================================================= */
782 #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
783
784 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
785 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
786 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
787 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
788 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
789 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
790 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
791 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
792 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
793 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
794 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
795 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
796 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
797 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
798 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
799 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
800
801 union uvh_gr1_tlb_int1_config_u {
802 unsigned long v;
803 struct uvh_gr1_tlb_int1_config_s {
804 unsigned long vector_:8; /* RW */
805 unsigned long dm:3; /* RW */
806 unsigned long destmode:1; /* RW */
807 unsigned long status:1; /* RO */
808 unsigned long p:1; /* RO */
809 unsigned long rsvd_14:1;
810 unsigned long t:1; /* RO */
811 unsigned long m:1; /* RW */
812 unsigned long rsvd_17_31:15;
813 unsigned long apic_id:32; /* RW */
814 } s;
815 };
816
817 /* ========================================================================= */
818 /* UVH_GR1_TLB_MMR_CONTROL */
819 /* ========================================================================= */
820 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
821 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
822 #define UVH_GR1_TLB_MMR_CONTROL (is_uv1_hub() ? \
823 UV1H_GR1_TLB_MMR_CONTROL : \
824 UV2H_GR1_TLB_MMR_CONTROL)
825
826 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
827 #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
828 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
829 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
830 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
831 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
832 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
833 #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
834 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
835 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
836 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
837 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
838
839 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
840 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
841 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
842 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
843 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
844 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
845 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
846 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
847 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
848 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56
849 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60
850 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
851 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
852 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
853 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
854 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
855 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
856 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
857 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
858 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
859 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL
860 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL
861
862 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
863 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
864 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
865 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
866 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
867 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
868 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
869 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
870 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
871 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
872 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
873 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
874 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
875 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
876 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
877 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
878 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
879 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
880
881 union uvh_gr1_tlb_mmr_control_u {
882 unsigned long v;
883 struct uvh_gr1_tlb_mmr_control_s {
884 unsigned long index:12; /* RW */
885 unsigned long mem_sel:2; /* RW */
886 unsigned long rsvd_14_15:2;
887 unsigned long auto_valid_en:1; /* RW */
888 unsigned long rsvd_17_19:3;
889 unsigned long mmr_hash_index_en:1; /* RW */
890 unsigned long rsvd_21_29:9;
891 unsigned long mmr_write:1; /* WP */
892 unsigned long mmr_read:1; /* WP */
893 unsigned long rsvd_32_63:32;
894 } s;
895 struct uv1h_gr1_tlb_mmr_control_s {
896 unsigned long index:12; /* RW */
897 unsigned long mem_sel:2; /* RW */
898 unsigned long rsvd_14_15:2;
899 unsigned long auto_valid_en:1; /* RW */
900 unsigned long rsvd_17_19:3;
901 unsigned long mmr_hash_index_en:1; /* RW */
902 unsigned long rsvd_21_29:9;
903 unsigned long mmr_write:1; /* WP */
904 unsigned long mmr_read:1; /* WP */
905 unsigned long rsvd_32_47:16;
906 unsigned long mmr_inj_con:1; /* RW */
907 unsigned long rsvd_49_51:3;
908 unsigned long mmr_inj_tlbram:1; /* RW */
909 unsigned long rsvd_53:1;
910 unsigned long mmr_inj_tlbpgsize:1; /* RW */
911 unsigned long rsvd_55:1;
912 unsigned long mmr_inj_tlbrreg:1; /* RW */
913 unsigned long rsvd_57_59:3;
914 unsigned long mmr_inj_tlblruv:1; /* RW */
915 unsigned long rsvd_61_63:3;
916 } s1;
917 struct uv2h_gr1_tlb_mmr_control_s {
918 unsigned long index:12; /* RW */
919 unsigned long mem_sel:2; /* RW */
920 unsigned long rsvd_14_15:2;
921 unsigned long auto_valid_en:1; /* RW */
922 unsigned long rsvd_17_19:3;
923 unsigned long mmr_hash_index_en:1; /* RW */
924 unsigned long rsvd_21_29:9;
925 unsigned long mmr_write:1; /* WP */
926 unsigned long mmr_read:1; /* WP */
927 unsigned long mmr_op_done:1; /* RW */
928 unsigned long rsvd_33_47:15;
929 unsigned long mmr_inj_con:1; /* RW */
930 unsigned long rsvd_49_51:3;
931 unsigned long mmr_inj_tlbram:1; /* RW */
932 unsigned long rsvd_53_63:11;
933 } s2;
934 };
935
936 /* ========================================================================= */
937 /* UVH_GR1_TLB_MMR_READ_DATA_HI */
938 /* ========================================================================= */
939 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
940 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
941 #define UVH_GR1_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \
942 UV1H_GR1_TLB_MMR_READ_DATA_HI : \
943 UV2H_GR1_TLB_MMR_READ_DATA_HI)
944
945 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
946 #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
947 #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
948 #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
949 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
950 #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
951 #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
952 #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
953
954 union uvh_gr1_tlb_mmr_read_data_hi_u {
955 unsigned long v;
956 struct uvh_gr1_tlb_mmr_read_data_hi_s {
957 unsigned long pfn:41; /* RO */
958 unsigned long gaa:2; /* RO */
959 unsigned long dirty:1; /* RO */
960 unsigned long larger:1; /* RO */
961 unsigned long rsvd_45_63:19;
962 } s;
963 };
964
965 /* ========================================================================= */
966 /* UVH_GR1_TLB_MMR_READ_DATA_LO */
967 /* ========================================================================= */
968 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
969 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
970 #define UVH_GR1_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \
971 UV1H_GR1_TLB_MMR_READ_DATA_LO : \
972 UV2H_GR1_TLB_MMR_READ_DATA_LO)
973
974 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
975 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
976 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63
977 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL
978 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
979 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
980
981 union uvh_gr1_tlb_mmr_read_data_lo_u {
982 unsigned long v;
983 struct uvh_gr1_tlb_mmr_read_data_lo_s {
984 unsigned long vpn:39; /* RO */
985 unsigned long asid:24; /* RO */
986 unsigned long valid:1; /* RO */
987 } s;
988 };
989
990 /* ========================================================================= */
991 /* UVH_INT_CMPB */
992 /* ========================================================================= */
993 #define UVH_INT_CMPB 0x22080UL
994
995 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
996 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
997
998 union uvh_int_cmpb_u {
999 unsigned long v;
1000 struct uvh_int_cmpb_s {
1001 unsigned long real_time_cmpb:56; /* RW */
1002 unsigned long rsvd_56_63:8;
1003 } s;
1004 };
1005
1006 /* ========================================================================= */
1007 /* UVH_INT_CMPC */
1008 /* ========================================================================= */
1009 #define UVH_INT_CMPC 0x22100UL
1010
1011 #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
1012 #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
1013
1014 union uvh_int_cmpc_u {
1015 unsigned long v;
1016 struct uvh_int_cmpc_s {
1017 unsigned long real_time_cmpc:56; /* RW */
1018 unsigned long rsvd_56_63:8;
1019 } s;
1020 };
1021
1022 /* ========================================================================= */
1023 /* UVH_INT_CMPD */
1024 /* ========================================================================= */
1025 #define UVH_INT_CMPD 0x22180UL
1026
1027 #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
1028 #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
1029
1030 union uvh_int_cmpd_u {
1031 unsigned long v;
1032 struct uvh_int_cmpd_s {
1033 unsigned long real_time_cmpd:56; /* RW */
1034 unsigned long rsvd_56_63:8;
1035 } s;
1036 };
1037
1038 /* ========================================================================= */
1039 /* UVH_IPI_INT */
1040 /* ========================================================================= */
1041 #define UVH_IPI_INT 0x60500UL
1042 #define UVH_IPI_INT_32 0x348
1043
1044 #define UVH_IPI_INT_VECTOR_SHFT 0
1045 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
1046 #define UVH_IPI_INT_DESTMODE_SHFT 11
1047 #define UVH_IPI_INT_APIC_ID_SHFT 16
1048 #define UVH_IPI_INT_SEND_SHFT 63
1049 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
1050 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
1051 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
1052 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
1053 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
1054
1055 union uvh_ipi_int_u {
1056 unsigned long v;
1057 struct uvh_ipi_int_s {
1058 unsigned long vector_:8; /* RW */
1059 unsigned long delivery_mode:3; /* RW */
1060 unsigned long destmode:1; /* RW */
1061 unsigned long rsvd_12_15:4;
1062 unsigned long apic_id:32; /* RW */
1063 unsigned long rsvd_48_62:15;
1064 unsigned long send:1; /* WP */
1065 } s;
1066 };
1067
1068 /* ========================================================================= */
1069 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
1070 /* ========================================================================= */
1071 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1072 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
1073
1074 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1075 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1076 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1077 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1078
1079 union uvh_lb_bau_intd_payload_queue_first_u {
1080 unsigned long v;
1081 struct uvh_lb_bau_intd_payload_queue_first_s {
1082 unsigned long rsvd_0_3:4;
1083 unsigned long address:39; /* RW */
1084 unsigned long rsvd_43_48:6;
1085 unsigned long node_id:14; /* RW */
1086 unsigned long rsvd_63:1;
1087 } s;
1088 };
1089
1090 /* ========================================================================= */
1091 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
1092 /* ========================================================================= */
1093 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1094 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
1095
1096 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1097 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1098
1099 union uvh_lb_bau_intd_payload_queue_last_u {
1100 unsigned long v;
1101 struct uvh_lb_bau_intd_payload_queue_last_s {
1102 unsigned long rsvd_0_3:4;
1103 unsigned long address:39; /* RW */
1104 unsigned long rsvd_43_63:21;
1105 } s;
1106 };
1107
1108 /* ========================================================================= */
1109 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
1110 /* ========================================================================= */
1111 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1112 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
1113
1114 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1115 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1116
1117 union uvh_lb_bau_intd_payload_queue_tail_u {
1118 unsigned long v;
1119 struct uvh_lb_bau_intd_payload_queue_tail_s {
1120 unsigned long rsvd_0_3:4;
1121 unsigned long address:39; /* RW */
1122 unsigned long rsvd_43_63:21;
1123 } s;
1124 };
1125
1126 /* ========================================================================= */
1127 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
1128 /* ========================================================================= */
1129 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
1130 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
1131
1132 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
1133 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
1134 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
1135 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
1136 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
1137 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
1138 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
1139 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
1140 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
1141 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
1142 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
1143 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
1144 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
1145 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
1146 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
1147 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
1148 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
1149 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
1150 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
1151 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
1152 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
1153 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
1154 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
1155 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
1156 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
1157 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
1158 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
1159 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
1160 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
1161 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
1162 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
1163 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
1164
1165 union uvh_lb_bau_intd_software_acknowledge_u {
1166 unsigned long v;
1167 struct uvh_lb_bau_intd_software_acknowledge_s {
1168 unsigned long pending_0:1; /* RW, W1C */
1169 unsigned long pending_1:1; /* RW, W1C */
1170 unsigned long pending_2:1; /* RW, W1C */
1171 unsigned long pending_3:1; /* RW, W1C */
1172 unsigned long pending_4:1; /* RW, W1C */
1173 unsigned long pending_5:1; /* RW, W1C */
1174 unsigned long pending_6:1; /* RW, W1C */
1175 unsigned long pending_7:1; /* RW, W1C */
1176 unsigned long timeout_0:1; /* RW, W1C */
1177 unsigned long timeout_1:1; /* RW, W1C */
1178 unsigned long timeout_2:1; /* RW, W1C */
1179 unsigned long timeout_3:1; /* RW, W1C */
1180 unsigned long timeout_4:1; /* RW, W1C */
1181 unsigned long timeout_5:1; /* RW, W1C */
1182 unsigned long timeout_6:1; /* RW, W1C */
1183 unsigned long timeout_7:1; /* RW, W1C */
1184 unsigned long rsvd_16_63:48;
1185 } s;
1186 };
1187
1188 /* ========================================================================= */
1189 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
1190 /* ========================================================================= */
1191 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
1192 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
1193
1194 /* ========================================================================= */
1195 /* UVH_LB_BAU_MISC_CONTROL */
1196 /* ========================================================================= */
1197 #define UVH_LB_BAU_MISC_CONTROL 0x320170UL
1198 #define UVH_LB_BAU_MISC_CONTROL_32 0xa10
1199
1200 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
1201 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
1202 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
1203 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
1204 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1205 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1206 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1207 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1208 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1209 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1210 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
1211 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
1212 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
1213 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
1214 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1215 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1216 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1217 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1218 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1219 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1220 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1221 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1222 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1223 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1224 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1225 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1226 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1227 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1228 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1229 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1230
1231 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
1232 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
1233 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
1234 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
1235 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1236 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1237 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1238 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1239 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1240 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1241 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
1242 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
1243 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
1244 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
1245 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1246 #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
1247 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1248 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1249 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1250 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1251 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1252 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1253 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1254 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1255 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1256 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1257 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1258 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1259 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1260 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1261 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1262 #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
1263
1264 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
1265 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
1266 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
1267 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
1268 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1269 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1270 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1271 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1272 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1273 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1274 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
1275 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
1276 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
1277 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
1278 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1279 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
1280 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
1281 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
1282 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
1283 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
1284 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
1285 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
1286 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
1287 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1288 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1289 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1290 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1291 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1292 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1293 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1294 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1295 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1296 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1297 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1298 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1299 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1300 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1301 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1302 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
1303 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
1304 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
1305 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
1306 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
1307 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
1308 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
1309 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
1310
1311 union uvh_lb_bau_misc_control_u {
1312 unsigned long v;
1313 struct uvh_lb_bau_misc_control_s {
1314 unsigned long rejection_delay:8; /* RW */
1315 unsigned long apic_mode:1; /* RW */
1316 unsigned long force_broadcast:1; /* RW */
1317 unsigned long force_lock_nop:1; /* RW */
1318 unsigned long qpi_agent_presence_vector:3; /* RW */
1319 unsigned long descriptor_fetch_mode:1; /* RW */
1320 unsigned long enable_intd_soft_ack_mode:1; /* RW */
1321 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1322 unsigned long enable_dual_mapping_mode:1; /* RW */
1323 unsigned long vga_io_port_decode_enable:1; /* RW */
1324 unsigned long vga_io_port_16_bit_decode:1; /* RW */
1325 unsigned long suppress_dest_registration:1; /* RW */
1326 unsigned long programmed_initial_priority:3; /* RW */
1327 unsigned long use_incoming_priority:1; /* RW */
1328 unsigned long enable_programmed_initial_priority:1;/* RW */
1329 unsigned long rsvd_29_63:35;
1330 } s;
1331 struct uv1h_lb_bau_misc_control_s {
1332 unsigned long rejection_delay:8; /* RW */
1333 unsigned long apic_mode:1; /* RW */
1334 unsigned long force_broadcast:1; /* RW */
1335 unsigned long force_lock_nop:1; /* RW */
1336 unsigned long qpi_agent_presence_vector:3; /* RW */
1337 unsigned long descriptor_fetch_mode:1; /* RW */
1338 unsigned long enable_intd_soft_ack_mode:1; /* RW */
1339 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1340 unsigned long enable_dual_mapping_mode:1; /* RW */
1341 unsigned long vga_io_port_decode_enable:1; /* RW */
1342 unsigned long vga_io_port_16_bit_decode:1; /* RW */
1343 unsigned long suppress_dest_registration:1; /* RW */
1344 unsigned long programmed_initial_priority:3; /* RW */
1345 unsigned long use_incoming_priority:1; /* RW */
1346 unsigned long enable_programmed_initial_priority:1;/* RW */
1347 unsigned long rsvd_29_47:19;
1348 unsigned long fun:16; /* RW */
1349 } s1;
1350 struct uv2h_lb_bau_misc_control_s {
1351 unsigned long rejection_delay:8; /* RW */
1352 unsigned long apic_mode:1; /* RW */
1353 unsigned long force_broadcast:1; /* RW */
1354 unsigned long force_lock_nop:1; /* RW */
1355 unsigned long qpi_agent_presence_vector:3; /* RW */
1356 unsigned long descriptor_fetch_mode:1; /* RW */
1357 unsigned long enable_intd_soft_ack_mode:1; /* RW */
1358 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1359 unsigned long enable_dual_mapping_mode:1; /* RW */
1360 unsigned long vga_io_port_decode_enable:1; /* RW */
1361 unsigned long vga_io_port_16_bit_decode:1; /* RW */
1362 unsigned long suppress_dest_registration:1; /* RW */
1363 unsigned long programmed_initial_priority:3; /* RW */
1364 unsigned long use_incoming_priority:1; /* RW */
1365 unsigned long enable_programmed_initial_priority:1;/* RW */
1366 unsigned long enable_automatic_apic_mode_selection:1;/* RW */
1367 unsigned long apic_mode_status:1; /* RO */
1368 unsigned long suppress_interrupts_to_self:1; /* RW */
1369 unsigned long enable_lock_based_system_flush:1;/* RW */
1370 unsigned long enable_extended_sb_status:1; /* RW */
1371 unsigned long suppress_int_prio_udt_to_self:1;/* RW */
1372 unsigned long use_legacy_descriptor_formats:1;/* RW */
1373 unsigned long rsvd_36_47:12;
1374 unsigned long fun:16; /* RW */
1375 } s2;
1376 };
1377
1378 /* ========================================================================= */
1379 /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
1380 /* ========================================================================= */
1381 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
1382 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
1383
1384 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
1385 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
1386 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
1387 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
1388 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
1389 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
1390
1391 union uvh_lb_bau_sb_activation_control_u {
1392 unsigned long v;
1393 struct uvh_lb_bau_sb_activation_control_s {
1394 unsigned long index:6; /* RW */
1395 unsigned long rsvd_6_61:56;
1396 unsigned long push:1; /* WP */
1397 unsigned long init:1; /* WP */
1398 } s;
1399 };
1400
1401 /* ========================================================================= */
1402 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
1403 /* ========================================================================= */
1404 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
1405 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
1406
1407 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
1408 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
1409
1410 union uvh_lb_bau_sb_activation_status_0_u {
1411 unsigned long v;
1412 struct uvh_lb_bau_sb_activation_status_0_s {
1413 unsigned long status:64; /* RW */
1414 } s;
1415 };
1416
1417 /* ========================================================================= */
1418 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
1419 /* ========================================================================= */
1420 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
1421 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
1422
1423 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
1424 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
1425
1426 union uvh_lb_bau_sb_activation_status_1_u {
1427 unsigned long v;
1428 struct uvh_lb_bau_sb_activation_status_1_s {
1429 unsigned long status:64; /* RW */
1430 } s;
1431 };
1432
1433 /* ========================================================================= */
1434 /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
1435 /* ========================================================================= */
1436 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
1437 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
1438
1439 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
1440 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
1441 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
1442 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
1443
1444 union uvh_lb_bau_sb_descriptor_base_u {
1445 unsigned long v;
1446 struct uvh_lb_bau_sb_descriptor_base_s {
1447 unsigned long rsvd_0_11:12;
1448 unsigned long page_address:31; /* RW */
1449 unsigned long rsvd_43_48:6;
1450 unsigned long node_id:14; /* RW */
1451 unsigned long rsvd_63:1;
1452 } s;
1453 };
1454
1455 /* ========================================================================= */
1456 /* UVH_NODE_ID */
1457 /* ========================================================================= */
1458 #define UVH_NODE_ID 0x0UL
1459
1460 #define UVH_NODE_ID_FORCE1_SHFT 0
1461 #define UVH_NODE_ID_MANUFACTURER_SHFT 1
1462 #define UVH_NODE_ID_PART_NUMBER_SHFT 12
1463 #define UVH_NODE_ID_REVISION_SHFT 28
1464 #define UVH_NODE_ID_NODE_ID_SHFT 32
1465 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1466 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1467 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1468 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1469 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1470
1471 #define UV1H_NODE_ID_FORCE1_SHFT 0
1472 #define UV1H_NODE_ID_MANUFACTURER_SHFT 1
1473 #define UV1H_NODE_ID_PART_NUMBER_SHFT 12
1474 #define UV1H_NODE_ID_REVISION_SHFT 28
1475 #define UV1H_NODE_ID_NODE_ID_SHFT 32
1476 #define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48
1477 #define UV1H_NODE_ID_NI_PORT_SHFT 56
1478 #define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1479 #define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1480 #define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1481 #define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1482 #define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1483 #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
1484 #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
1485
1486 #define UV2H_NODE_ID_FORCE1_SHFT 0
1487 #define UV2H_NODE_ID_MANUFACTURER_SHFT 1
1488 #define UV2H_NODE_ID_PART_NUMBER_SHFT 12
1489 #define UV2H_NODE_ID_REVISION_SHFT 28
1490 #define UV2H_NODE_ID_NODE_ID_SHFT 32
1491 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50
1492 #define UV2H_NODE_ID_NI_PORT_SHFT 57
1493 #define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1494 #define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1495 #define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1496 #define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1497 #define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1498 #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
1499 #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
1500
1501 union uvh_node_id_u {
1502 unsigned long v;
1503 struct uvh_node_id_s {
1504 unsigned long force1:1; /* RO */
1505 unsigned long manufacturer:11; /* RO */
1506 unsigned long part_number:16; /* RO */
1507 unsigned long revision:4; /* RO */
1508 unsigned long node_id:15; /* RW */
1509 unsigned long rsvd_47_63:17;
1510 } s;
1511 struct uv1h_node_id_s {
1512 unsigned long force1:1; /* RO */
1513 unsigned long manufacturer:11; /* RO */
1514 unsigned long part_number:16; /* RO */
1515 unsigned long revision:4; /* RO */
1516 unsigned long node_id:15; /* RW */
1517 unsigned long rsvd_47:1;
1518 unsigned long nodes_per_bit:7; /* RW */
1519 unsigned long rsvd_55:1;
1520 unsigned long ni_port:4; /* RO */
1521 unsigned long rsvd_60_63:4;
1522 } s1;
1523 struct uv2h_node_id_s {
1524 unsigned long force1:1; /* RO */
1525 unsigned long manufacturer:11; /* RO */
1526 unsigned long part_number:16; /* RO */
1527 unsigned long revision:4; /* RO */
1528 unsigned long node_id:15; /* RW */
1529 unsigned long rsvd_47_49:3;
1530 unsigned long nodes_per_bit:7; /* RO */
1531 unsigned long ni_port:5; /* RO */
1532 unsigned long rsvd_62_63:2;
1533 } s2;
1534 };
1535
1536 /* ========================================================================= */
1537 /* UVH_NODE_PRESENT_TABLE */
1538 /* ========================================================================= */
1539 #define UVH_NODE_PRESENT_TABLE 0x1400UL
1540 #define UVH_NODE_PRESENT_TABLE_DEPTH 16
1541
1542 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
1543 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
1544
1545 union uvh_node_present_table_u {
1546 unsigned long v;
1547 struct uvh_node_present_table_s {
1548 unsigned long nodes:64; /* RW */
1549 } s;
1550 };
1551
1552 /* ========================================================================= */
1553 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */
1554 /* ========================================================================= */
1555 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
1556
1557 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
1558 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
1559 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
1560 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
1561 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
1562 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
1563
1564 union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
1565 unsigned long v;
1566 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
1567 unsigned long rsvd_0_23:24;
1568 unsigned long base:8; /* RW */
1569 unsigned long rsvd_32_47:16;
1570 unsigned long m_alias:5; /* RW */
1571 unsigned long rsvd_53_62:10;
1572 unsigned long enable:1; /* RW */
1573 } s;
1574 };
1575
1576 /* ========================================================================= */
1577 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */
1578 /* ========================================================================= */
1579 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
1580
1581 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
1582 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
1583 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
1584 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
1585 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
1586 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
1587
1588 union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
1589 unsigned long v;
1590 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
1591 unsigned long rsvd_0_23:24;
1592 unsigned long base:8; /* RW */
1593 unsigned long rsvd_32_47:16;
1594 unsigned long m_alias:5; /* RW */
1595 unsigned long rsvd_53_62:10;
1596 unsigned long enable:1; /* RW */
1597 } s;
1598 };
1599
1600 /* ========================================================================= */
1601 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */
1602 /* ========================================================================= */
1603 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
1604
1605 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
1606 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
1607 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
1608 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
1609 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
1610 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
1611
1612 union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
1613 unsigned long v;
1614 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
1615 unsigned long rsvd_0_23:24;
1616 unsigned long base:8; /* RW */
1617 unsigned long rsvd_32_47:16;
1618 unsigned long m_alias:5; /* RW */
1619 unsigned long rsvd_53_62:10;
1620 unsigned long enable:1; /* RW */
1621 } s;
1622 };
1623
1624 /* ========================================================================= */
1625 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
1626 /* ========================================================================= */
1627 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
1628
1629 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
1630 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1631
1632 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
1633 unsigned long v;
1634 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
1635 unsigned long rsvd_0_23:24;
1636 unsigned long dest_base:22; /* RW */
1637 unsigned long rsvd_46_63:18;
1638 } s;
1639 };
1640
1641 /* ========================================================================= */
1642 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
1643 /* ========================================================================= */
1644 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
1645
1646 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
1647 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1648
1649 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
1650 unsigned long v;
1651 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
1652 unsigned long rsvd_0_23:24;
1653 unsigned long dest_base:22; /* RW */
1654 unsigned long rsvd_46_63:18;
1655 } s;
1656 };
1657
1658 /* ========================================================================= */
1659 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
1660 /* ========================================================================= */
1661 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
1662
1663 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
1664 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1665
1666 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
1667 unsigned long v;
1668 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
1669 unsigned long rsvd_0_23:24;
1670 unsigned long dest_base:22; /* RW */
1671 unsigned long rsvd_46_63:18;
1672 } s;
1673 };
1674
1675 /* ========================================================================= */
1676 /* UVH_RH_GAM_CONFIG_MMR */
1677 /* ========================================================================= */
1678 #define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
1679
1680 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1681 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1682 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1683 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1684
1685 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1686 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1687 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
1688 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1689 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1690 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
1691
1692 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1693 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1694 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1695 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1696
1697 union uvh_rh_gam_config_mmr_u {
1698 unsigned long v;
1699 struct uvh_rh_gam_config_mmr_s {
1700 unsigned long m_skt:6; /* RW */
1701 unsigned long n_skt:4; /* RW */
1702 unsigned long rsvd_10_63:54;
1703 } s;
1704 struct uv1h_rh_gam_config_mmr_s {
1705 unsigned long m_skt:6; /* RW */
1706 unsigned long n_skt:4; /* RW */
1707 unsigned long rsvd_10_11:2;
1708 unsigned long mmiol_cfg:1; /* RW */
1709 unsigned long rsvd_13_63:51;
1710 } s1;
1711 struct uv2h_rh_gam_config_mmr_s {
1712 unsigned long m_skt:6; /* RW */
1713 unsigned long n_skt:4; /* RW */
1714 unsigned long rsvd_10_63:54;
1715 } s2;
1716 };
1717
1718 /* ========================================================================= */
1719 /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
1720 /* ========================================================================= */
1721 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
1722
1723 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1724 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1725
1726 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1727 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
1728 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1729 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1730 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1731 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
1732 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1733 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1734
1735 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1736 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1737 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1738 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1739 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1740 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1741
1742 union uvh_rh_gam_gru_overlay_config_mmr_u {
1743 unsigned long v;
1744 struct uvh_rh_gam_gru_overlay_config_mmr_s {
1745 unsigned long rsvd_0_27:28;
1746 unsigned long base:18; /* RW */
1747 unsigned long rsvd_46_62:17;
1748 unsigned long enable:1; /* RW */
1749 } s;
1750 struct uv1h_rh_gam_gru_overlay_config_mmr_s {
1751 unsigned long rsvd_0_27:28;
1752 unsigned long base:18; /* RW */
1753 unsigned long rsvd_46_47:2;
1754 unsigned long gr4:1; /* RW */
1755 unsigned long rsvd_49_51:3;
1756 unsigned long n_gru:4; /* RW */
1757 unsigned long rsvd_56_62:7;
1758 unsigned long enable:1; /* RW */
1759 } s1;
1760 struct uv2h_rh_gam_gru_overlay_config_mmr_s {
1761 unsigned long rsvd_0_27:28;
1762 unsigned long base:18; /* RW */
1763 unsigned long rsvd_46_51:6;
1764 unsigned long n_gru:4; /* RW */
1765 unsigned long rsvd_56_62:7;
1766 unsigned long enable:1; /* RW */
1767 } s2;
1768 };
1769
1770 /* ========================================================================= */
1771 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
1772 /* ========================================================================= */
1773 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1774
1775 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1776 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1777 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1778 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1779 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1780 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1781 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1782 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1783
1784 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27
1785 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1786 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1787 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1788 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL
1789 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1790 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1791 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1792
1793 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1794 unsigned long v;
1795 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
1796 unsigned long rsvd_0_29:30;
1797 unsigned long base:16; /* RW */
1798 unsigned long m_io:6; /* RW */
1799 unsigned long n_io:4; /* RW */
1800 unsigned long rsvd_56_62:7;
1801 unsigned long enable:1; /* RW */
1802 } s1;
1803 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
1804 unsigned long rsvd_0_26:27;
1805 unsigned long base:19; /* RW */
1806 unsigned long m_io:6; /* RW */
1807 unsigned long n_io:4; /* RW */
1808 unsigned long rsvd_56_62:7;
1809 unsigned long enable:1; /* RW */
1810 } s2;
1811 };
1812
1813 /* ========================================================================= */
1814 /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
1815 /* ========================================================================= */
1816 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
1817
1818 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1819 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1820
1821 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1822 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
1823 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1824 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1825 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
1826 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1827
1828 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1829 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1830 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1831 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1832
1833 union uvh_rh_gam_mmr_overlay_config_mmr_u {
1834 unsigned long v;
1835 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
1836 unsigned long rsvd_0_25:26;
1837 unsigned long base:20; /* RW */
1838 unsigned long rsvd_46_62:17;
1839 unsigned long enable:1; /* RW */
1840 } s;
1841 struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
1842 unsigned long rsvd_0_25:26;
1843 unsigned long base:20; /* RW */
1844 unsigned long dual_hub:1; /* RW */
1845 unsigned long rsvd_47_62:16;
1846 unsigned long enable:1; /* RW */
1847 } s1;
1848 struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
1849 unsigned long rsvd_0_25:26;
1850 unsigned long base:20; /* RW */
1851 unsigned long rsvd_46_62:17;
1852 unsigned long enable:1; /* RW */
1853 } s2;
1854 };
1855
1856 /* ========================================================================= */
1857 /* UVH_RTC */
1858 /* ========================================================================= */
1859 #define UVH_RTC 0x340000UL
1860
1861 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
1862 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
1863
1864 union uvh_rtc_u {
1865 unsigned long v;
1866 struct uvh_rtc_s {
1867 unsigned long real_time_clock:56; /* RW */
1868 unsigned long rsvd_56_63:8;
1869 } s;
1870 };
1871
1872 /* ========================================================================= */
1873 /* UVH_RTC1_INT_CONFIG */
1874 /* ========================================================================= */
1875 #define UVH_RTC1_INT_CONFIG 0x615c0UL
1876
1877 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
1878 #define UVH_RTC1_INT_CONFIG_DM_SHFT 8
1879 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
1880 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
1881 #define UVH_RTC1_INT_CONFIG_P_SHFT 13
1882 #define UVH_RTC1_INT_CONFIG_T_SHFT 15
1883 #define UVH_RTC1_INT_CONFIG_M_SHFT 16
1884 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
1885 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1886 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
1887 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1888 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1889 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
1890 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
1891 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
1892 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1893
1894 union uvh_rtc1_int_config_u {
1895 unsigned long v;
1896 struct uvh_rtc1_int_config_s {
1897 unsigned long vector_:8; /* RW */
1898 unsigned long dm:3; /* RW */
1899 unsigned long destmode:1; /* RW */
1900 unsigned long status:1; /* RO */
1901 unsigned long p:1; /* RO */
1902 unsigned long rsvd_14:1;
1903 unsigned long t:1; /* RO */
1904 unsigned long m:1; /* RW */
1905 unsigned long rsvd_17_31:15;
1906 unsigned long apic_id:32; /* RW */
1907 } s;
1908 };
1909
1910 /* ========================================================================= */
1911 /* UVH_SCRATCH5 */
1912 /* ========================================================================= */
1913 #define UVH_SCRATCH5 0x2d0200UL
1914 #define UVH_SCRATCH5_32 0x778
1915
1916 #define UVH_SCRATCH5_SCRATCH5_SHFT 0
1917 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
1918
1919 union uvh_scratch5_u {
1920 unsigned long v;
1921 struct uvh_scratch5_s {
1922 unsigned long scratch5:64; /* RW, W1CS */
1923 } s;
1924 };
1925
1926 /* ========================================================================= */
1927 /* UV2H_EVENT_OCCURRED2 */
1928 /* ========================================================================= */
1929 #define UV2H_EVENT_OCCURRED2 0x70100UL
1930 #define UV2H_EVENT_OCCURRED2_32 0xb68
1931
1932 #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
1933 #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
1934 #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
1935 #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
1936 #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
1937 #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
1938 #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
1939 #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
1940 #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
1941 #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
1942 #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
1943 #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
1944 #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
1945 #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
1946 #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
1947 #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
1948 #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
1949 #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
1950 #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
1951 #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
1952 #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
1953 #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
1954 #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
1955 #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
1956 #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
1957 #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
1958 #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
1959 #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
1960 #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
1961 #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
1962 #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
1963 #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
1964 #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
1965 #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
1966 #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
1967 #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
1968 #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
1969 #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
1970 #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
1971 #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
1972 #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
1973 #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
1974 #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
1975 #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
1976 #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
1977 #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
1978 #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
1979 #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
1980 #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
1981 #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
1982 #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
1983 #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
1984 #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
1985 #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
1986 #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
1987 #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
1988 #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
1989 #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
1990 #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
1991 #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
1992 #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
1993 #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
1994 #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
1995 #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
1996
1997 union uv2h_event_occurred2_u {
1998 unsigned long v;
1999 struct uv2h_event_occurred2_s {
2000 unsigned long rtc_0:1; /* RW */
2001 unsigned long rtc_1:1; /* RW */
2002 unsigned long rtc_2:1; /* RW */
2003 unsigned long rtc_3:1; /* RW */
2004 unsigned long rtc_4:1; /* RW */
2005 unsigned long rtc_5:1; /* RW */
2006 unsigned long rtc_6:1; /* RW */
2007 unsigned long rtc_7:1; /* RW */
2008 unsigned long rtc_8:1; /* RW */
2009 unsigned long rtc_9:1; /* RW */
2010 unsigned long rtc_10:1; /* RW */
2011 unsigned long rtc_11:1; /* RW */
2012 unsigned long rtc_12:1; /* RW */
2013 unsigned long rtc_13:1; /* RW */
2014 unsigned long rtc_14:1; /* RW */
2015 unsigned long rtc_15:1; /* RW */
2016 unsigned long rtc_16:1; /* RW */
2017 unsigned long rtc_17:1; /* RW */
2018 unsigned long rtc_18:1; /* RW */
2019 unsigned long rtc_19:1; /* RW */
2020 unsigned long rtc_20:1; /* RW */
2021 unsigned long rtc_21:1; /* RW */
2022 unsigned long rtc_22:1; /* RW */
2023 unsigned long rtc_23:1; /* RW */
2024 unsigned long rtc_24:1; /* RW */
2025 unsigned long rtc_25:1; /* RW */
2026 unsigned long rtc_26:1; /* RW */
2027 unsigned long rtc_27:1; /* RW */
2028 unsigned long rtc_28:1; /* RW */
2029 unsigned long rtc_29:1; /* RW */
2030 unsigned long rtc_30:1; /* RW */
2031 unsigned long rtc_31:1; /* RW */
2032 unsigned long rsvd_32_63:32;
2033 } s1;
2034 };
2035
2036 /* ========================================================================= */
2037 /* UV2H_EVENT_OCCURRED2_ALIAS */
2038 /* ========================================================================= */
2039 #define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL
2040 #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
2041
2042 /* ========================================================================= */
2043 /* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */
2044 /* ========================================================================= */
2045 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
2046 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
2047
2048 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
2049 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
2050
2051 union uv2h_lb_bau_sb_activation_status_2_u {
2052 unsigned long v;
2053 struct uv2h_lb_bau_sb_activation_status_2_s {
2054 unsigned long aux_error:64; /* RW */
2055 } s1;
2056 };
2057
2058 /* ========================================================================= */
2059 /* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */
2060 /* ========================================================================= */
2061 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
2062 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0
2063
2064 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
2065 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
2066
2067 union uv1h_lb_target_physical_apic_id_mask_u {
2068 unsigned long v;
2069 struct uv1h_lb_target_physical_apic_id_mask_s {
2070 unsigned long bit_enables:32; /* RW */
2071 unsigned long rsvd_32_63:32;
2072 } s1;
2073 };
2074
2075
2076 #endif /* _ASM_X86_UV_UV_MMRS_H */
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