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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / arch / x86 / kvm / paging_tmpl.h
blob507e2b844cfa96be64ee518e922916479f66a6d7
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 /*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26 #if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
38 #else
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
41 #endif
42 #elif PTTYPE == 32
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
53 #else
54 #error Invalid PTTYPE value
55 #endif
56
57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
59
60 /*
61 * The guest_walker structure emulates the behavior of the hardware page
62 * table walker.
63 */
64 struct guest_walker {
65 int level;
66 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
67 pt_element_t ptes[PT_MAX_FULL_LEVELS];
68 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
70 unsigned pt_access;
71 unsigned pte_access;
72 gfn_t gfn;
73 struct x86_exception fault;
74 };
75
76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
77 {
78 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
79 }
80
81 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
82 pt_element_t __user *ptep_user, unsigned index,
83 pt_element_t orig_pte, pt_element_t new_pte)
84 {
85 int npages;
86 pt_element_t ret;
87 pt_element_t *table;
88 struct page *page;
89
90 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
91 /* Check if the user is doing something meaningless. */
92 if (unlikely(npages != 1))
93 return -EFAULT;
94
95 table = kmap_atomic(page, KM_USER0);
96 ret = CMPXCHG(&table[index], orig_pte, new_pte);
97 kunmap_atomic(table, KM_USER0);
98
99 kvm_release_page_dirty(page);
100
101 return (ret != orig_pte);
102 }
103
104 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte,
105 bool last)
106 {
107 unsigned access;
108
109 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
110 if (last && !is_dirty_gpte(gpte))
111 access &= ~ACC_WRITE_MASK;
112
113 #if PTTYPE == 64
114 if (vcpu->arch.mmu.nx)
115 access &= ~(gpte >> PT64_NX_SHIFT);
116 #endif
117 return access;
118 }
119
120 static bool FNAME(is_last_gpte)(struct guest_walker *walker,
121 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
122 pt_element_t gpte)
123 {
124 if (walker->level == PT_PAGE_TABLE_LEVEL)
125 return true;
126
127 if ((walker->level == PT_DIRECTORY_LEVEL) && is_large_pte(gpte) &&
128 (PTTYPE == 64 || is_pse(vcpu)))
129 return true;
130
131 if ((walker->level == PT_PDPE_LEVEL) && is_large_pte(gpte) &&
132 (mmu->root_level == PT64_ROOT_LEVEL))
133 return true;
134
135 return false;
136 }
137
138 /*
139 * Fetch a guest pte for a guest virtual address
140 */
141 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
142 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
143 gva_t addr, u32 access)
144 {
145 pt_element_t pte;
146 pt_element_t __user *uninitialized_var(ptep_user);
147 gfn_t table_gfn;
148 unsigned index, pt_access, uninitialized_var(pte_access);
149 gpa_t pte_gpa;
150 bool eperm;
151 int offset;
152 const int write_fault = access & PFERR_WRITE_MASK;
153 const int user_fault = access & PFERR_USER_MASK;
154 const int fetch_fault = access & PFERR_FETCH_MASK;
155 u16 errcode = 0;
156
157 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
158 fetch_fault);
159 retry_walk:
160 eperm = false;
161 walker->level = mmu->root_level;
162 pte = mmu->get_cr3(vcpu);
163
164 #if PTTYPE == 64
165 if (walker->level == PT32E_ROOT_LEVEL) {
166 pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
167 trace_kvm_mmu_paging_element(pte, walker->level);
168 if (!is_present_gpte(pte))
169 goto error;
170 --walker->level;
171 }
172 #endif
173 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
174 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
175
176 pt_access = ACC_ALL;
177
178 for (;;) {
179 gfn_t real_gfn;
180 unsigned long host_addr;
181
182 index = PT_INDEX(addr, walker->level);
183
184 table_gfn = gpte_to_gfn(pte);
185 offset = index * sizeof(pt_element_t);
186 pte_gpa = gfn_to_gpa(table_gfn) + offset;
187 walker->table_gfn[walker->level - 1] = table_gfn;
188 walker->pte_gpa[walker->level - 1] = pte_gpa;
189
190 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
191 PFERR_USER_MASK|PFERR_WRITE_MASK);
192 if (unlikely(real_gfn == UNMAPPED_GVA))
193 goto error;
194 real_gfn = gpa_to_gfn(real_gfn);
195
196 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
197 if (unlikely(kvm_is_error_hva(host_addr)))
198 goto error;
199
200 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
201 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
202 goto error;
203
204 trace_kvm_mmu_paging_element(pte, walker->level);
205
206 if (unlikely(!is_present_gpte(pte)))
207 goto error;
208
209 if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
210 walker->level))) {
211 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
212 goto error;
213 }
214
215 if (!check_write_user_access(vcpu, write_fault, user_fault,
216 pte))
217 eperm = true;
218
219 #if PTTYPE == 64
220 if (unlikely(fetch_fault && (pte & PT64_NX_MASK)))
221 eperm = true;
222 #endif
223
224 if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) {
225 int ret;
226 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
227 sizeof(pte));
228 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
229 pte, pte|PT_ACCESSED_MASK);
230 if (unlikely(ret < 0))
231 goto error;
232 else if (ret)
233 goto retry_walk;
234
235 mark_page_dirty(vcpu->kvm, table_gfn);
236 pte |= PT_ACCESSED_MASK;
237 }
238
239 walker->ptes[walker->level - 1] = pte;
240
241 if (FNAME(is_last_gpte)(walker, vcpu, mmu, pte)) {
242 int lvl = walker->level;
243 gpa_t real_gpa;
244 gfn_t gfn;
245 u32 ac;
246
247 /* check if the kernel is fetching from user page */
248 if (unlikely(pte_access & PT_USER_MASK) &&
249 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
250 if (fetch_fault && !user_fault)
251 eperm = true;
252
253 gfn = gpte_to_gfn_lvl(pte, lvl);
254 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
255
256 if (PTTYPE == 32 &&
257 walker->level == PT_DIRECTORY_LEVEL &&
258 is_cpuid_PSE36())
259 gfn += pse36_gfn_delta(pte);
260
261 ac = write_fault | fetch_fault | user_fault;
262
263 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
264 ac);
265 if (real_gpa == UNMAPPED_GVA)
266 return 0;
267
268 walker->gfn = real_gpa >> PAGE_SHIFT;
269
270 break;
271 }
272
273 pt_access &= FNAME(gpte_access)(vcpu, pte, false);
274 --walker->level;
275 }
276
277 if (unlikely(eperm)) {
278 errcode |= PFERR_PRESENT_MASK;
279 goto error;
280 }
281
282 if (write_fault && unlikely(!is_dirty_gpte(pte))) {
283 int ret;
284
285 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
286 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
287 pte, pte|PT_DIRTY_MASK);
288 if (unlikely(ret < 0))
289 goto error;
290 else if (ret)
291 goto retry_walk;
292
293 mark_page_dirty(vcpu->kvm, table_gfn);
294 pte |= PT_DIRTY_MASK;
295 walker->ptes[walker->level - 1] = pte;
296 }
297
298 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte, true);
299 walker->pt_access = pt_access;
300 walker->pte_access = pte_access;
301 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
302 __func__, (u64)pte, pte_access, pt_access);
303 return 1;
304
305 error:
306 errcode |= write_fault | user_fault;
307 if (fetch_fault && (mmu->nx ||
308 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
309 errcode |= PFERR_FETCH_MASK;
310
311 walker->fault.vector = PF_VECTOR;
312 walker->fault.error_code_valid = true;
313 walker->fault.error_code = errcode;
314 walker->fault.address = addr;
315 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
316
317 trace_kvm_mmu_walker_error(walker->fault.error_code);
318 return 0;
319 }
320
321 static int FNAME(walk_addr)(struct guest_walker *walker,
322 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
323 {
324 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
325 access);
326 }
327
328 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
329 struct kvm_vcpu *vcpu, gva_t addr,
330 u32 access)
331 {
332 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
333 addr, access);
334 }
335
336 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
337 struct kvm_mmu_page *sp, u64 *spte,
338 pt_element_t gpte)
339 {
340 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
341 goto no_present;
342
343 if (!is_present_gpte(gpte))
344 goto no_present;
345
346 if (!(gpte & PT_ACCESSED_MASK))
347 goto no_present;
348
349 return false;
350
351 no_present:
352 drop_spte(vcpu->kvm, spte);
353 return true;
354 }
355
356 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
357 u64 *spte, const void *pte)
358 {
359 pt_element_t gpte;
360 unsigned pte_access;
361 pfn_t pfn;
362
363 gpte = *(const pt_element_t *)pte;
364 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
365 return;
366
367 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
368 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte, true);
369 pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte));
370 if (mmu_invalid_pfn(pfn)) {
371 kvm_release_pfn_clean(pfn);
372 return;
373 }
374
375 /*
376 * we call mmu_set_spte() with host_writable = true because that
377 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
378 */
379 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
380 NULL, PT_PAGE_TABLE_LEVEL,
381 gpte_to_gfn(gpte), pfn, true, true);
382 }
383
384 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
385 struct guest_walker *gw, int level)
386 {
387 pt_element_t curr_pte;
388 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
389 u64 mask;
390 int r, index;
391
392 if (level == PT_PAGE_TABLE_LEVEL) {
393 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
394 base_gpa = pte_gpa & ~mask;
395 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
396
397 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
398 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
399 curr_pte = gw->prefetch_ptes[index];
400 } else
401 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
402 &curr_pte, sizeof(curr_pte));
403
404 return r || curr_pte != gw->ptes[level - 1];
405 }
406
407 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
408 u64 *sptep)
409 {
410 struct kvm_mmu_page *sp;
411 pt_element_t *gptep = gw->prefetch_ptes;
412 u64 *spte;
413 int i;
414
415 sp = page_header(__pa(sptep));
416
417 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
418 return;
419
420 if (sp->role.direct)
421 return __direct_pte_prefetch(vcpu, sp, sptep);
422
423 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
424 spte = sp->spt + i;
425
426 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
427 pt_element_t gpte;
428 unsigned pte_access;
429 gfn_t gfn;
430 pfn_t pfn;
431
432 if (spte == sptep)
433 continue;
434
435 if (is_shadow_present_pte(*spte))
436 continue;
437
438 gpte = gptep[i];
439
440 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
441 continue;
442
443 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte,
444 true);
445 gfn = gpte_to_gfn(gpte);
446 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
447 pte_access & ACC_WRITE_MASK);
448 if (mmu_invalid_pfn(pfn)) {
449 kvm_release_pfn_clean(pfn);
450 break;
451 }
452
453 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
454 NULL, PT_PAGE_TABLE_LEVEL, gfn,
455 pfn, true, true);
456 }
457 }
458
459 /*
460 * Fetch a shadow pte for a specific level in the paging hierarchy.
461 */
462 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
463 struct guest_walker *gw,
464 int user_fault, int write_fault, int hlevel,
465 int *emulate, pfn_t pfn, bool map_writable,
466 bool prefault)
467 {
468 unsigned access = gw->pt_access;
469 struct kvm_mmu_page *sp = NULL;
470 int top_level;
471 unsigned direct_access;
472 struct kvm_shadow_walk_iterator it;
473
474 if (!is_present_gpte(gw->ptes[gw->level - 1]))
475 return NULL;
476
477 direct_access = gw->pte_access;
478
479 top_level = vcpu->arch.mmu.root_level;
480 if (top_level == PT32E_ROOT_LEVEL)
481 top_level = PT32_ROOT_LEVEL;
482 /*
483 * Verify that the top-level gpte is still there. Since the page
484 * is a root page, it is either write protected (and cannot be
485 * changed from now on) or it is invalid (in which case, we don't
486 * really care if it changes underneath us after this point).
487 */
488 if (FNAME(gpte_changed)(vcpu, gw, top_level))
489 goto out_gpte_changed;
490
491 for (shadow_walk_init(&it, vcpu, addr);
492 shadow_walk_okay(&it) && it.level > gw->level;
493 shadow_walk_next(&it)) {
494 gfn_t table_gfn;
495
496 drop_large_spte(vcpu, it.sptep);
497
498 sp = NULL;
499 if (!is_shadow_present_pte(*it.sptep)) {
500 table_gfn = gw->table_gfn[it.level - 2];
501 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
502 false, access, it.sptep);
503 }
504
505 /*
506 * Verify that the gpte in the page we've just write
507 * protected is still there.
508 */
509 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
510 goto out_gpte_changed;
511
512 if (sp)
513 link_shadow_page(it.sptep, sp);
514 }
515
516 for (;
517 shadow_walk_okay(&it) && it.level > hlevel;
518 shadow_walk_next(&it)) {
519 gfn_t direct_gfn;
520
521 validate_direct_spte(vcpu, it.sptep, direct_access);
522
523 drop_large_spte(vcpu, it.sptep);
524
525 if (is_shadow_present_pte(*it.sptep))
526 continue;
527
528 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
529
530 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
531 true, direct_access, it.sptep);
532 link_shadow_page(it.sptep, sp);
533 }
534
535 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access,
536 user_fault, write_fault, emulate, it.level,
537 gw->gfn, pfn, prefault, map_writable);
538 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
539
540 return it.sptep;
541
542 out_gpte_changed:
543 if (sp)
544 kvm_mmu_put_page(sp, it.sptep);
545 kvm_release_pfn_clean(pfn);
546 return NULL;
547 }
548
549 /*
550 * Page fault handler. There are several causes for a page fault:
551 * - there is no shadow pte for the guest pte
552 * - write access through a shadow pte marked read only so that we can set
553 * the dirty bit
554 * - write access to a shadow pte marked read only so we can update the page
555 * dirty bitmap, when userspace requests it
556 * - mmio access; in this case we will never install a present shadow pte
557 * - normal guest page fault due to the guest pte marked not present, not
558 * writable, or not executable
559 *
560 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
561 * a negative value on error.
562 */
563 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
564 bool prefault)
565 {
566 int write_fault = error_code & PFERR_WRITE_MASK;
567 int user_fault = error_code & PFERR_USER_MASK;
568 struct guest_walker walker;
569 u64 *sptep;
570 int emulate = 0;
571 int r;
572 pfn_t pfn;
573 int level = PT_PAGE_TABLE_LEVEL;
574 int force_pt_level;
575 unsigned long mmu_seq;
576 bool map_writable;
577
578 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
579
580 if (unlikely(error_code & PFERR_RSVD_MASK))
581 return handle_mmio_page_fault(vcpu, addr, error_code,
582 mmu_is_nested(vcpu));
583
584 r = mmu_topup_memory_caches(vcpu);
585 if (r)
586 return r;
587
588 /*
589 * Look up the guest pte for the faulting address.
590 */
591 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
592
593 /*
594 * The page is not mapped by the guest. Let the guest handle it.
595 */
596 if (!r) {
597 pgprintk("%s: guest page fault\n", __func__);
598 if (!prefault) {
599 inject_page_fault(vcpu, &walker.fault);
600 /* reset fork detector */
601 vcpu->arch.last_pt_write_count = 0;
602 }
603 return 0;
604 }
605
606 if (walker.level >= PT_DIRECTORY_LEVEL)
607 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
608 else
609 force_pt_level = 1;
610 if (!force_pt_level) {
611 level = min(walker.level, mapping_level(vcpu, walker.gfn));
612 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
613 }
614
615 mmu_seq = vcpu->kvm->mmu_notifier_seq;
616 smp_rmb();
617
618 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
619 &map_writable))
620 return 0;
621
622 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
623 walker.gfn, pfn, walker.pte_access, &r))
624 return r;
625
626 spin_lock(&vcpu->kvm->mmu_lock);
627 if (mmu_notifier_retry(vcpu, mmu_seq))
628 goto out_unlock;
629
630 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
631 kvm_mmu_free_some_pages(vcpu);
632 if (!force_pt_level)
633 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
634 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
635 level, &emulate, pfn, map_writable, prefault);
636 (void)sptep;
637 pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__,
638 sptep, *sptep, emulate);
639
640 if (!emulate)
641 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
642
643 ++vcpu->stat.pf_fixed;
644 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
645 spin_unlock(&vcpu->kvm->mmu_lock);
646
647 return emulate;
648
649 out_unlock:
650 spin_unlock(&vcpu->kvm->mmu_lock);
651 kvm_release_pfn_clean(pfn);
652 return 0;
653 }
654
655 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
656 {
657 struct kvm_shadow_walk_iterator iterator;
658 struct kvm_mmu_page *sp;
659 gpa_t pte_gpa = -1;
660 int level;
661 u64 *sptep;
662 int need_flush = 0;
663
664 vcpu_clear_mmio_info(vcpu, gva);
665
666 spin_lock(&vcpu->kvm->mmu_lock);
667
668 for_each_shadow_entry(vcpu, gva, iterator) {
669 level = iterator.level;
670 sptep = iterator.sptep;
671
672 sp = page_header(__pa(sptep));
673 if (is_last_spte(*sptep, level)) {
674 int offset, shift;
675
676 if (!sp->unsync)
677 break;
678
679 shift = PAGE_SHIFT -
680 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
681 offset = sp->role.quadrant << shift;
682
683 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
684 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
685
686 if (is_shadow_present_pte(*sptep)) {
687 if (is_large_pte(*sptep))
688 --vcpu->kvm->stat.lpages;
689 drop_spte(vcpu->kvm, sptep);
690 need_flush = 1;
691 } else if (is_mmio_spte(*sptep))
692 mmu_spte_clear_no_track(sptep);
693
694 break;
695 }
696
697 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
698 break;
699 }
700
701 if (need_flush)
702 kvm_flush_remote_tlbs(vcpu->kvm);
703
704 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
705
706 spin_unlock(&vcpu->kvm->mmu_lock);
707
708 if (pte_gpa == -1)
709 return;
710
711 if (mmu_topup_memory_caches(vcpu))
712 return;
713 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
714 }
715
716 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
717 struct x86_exception *exception)
718 {
719 struct guest_walker walker;
720 gpa_t gpa = UNMAPPED_GVA;
721 int r;
722
723 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
724
725 if (r) {
726 gpa = gfn_to_gpa(walker.gfn);
727 gpa |= vaddr & ~PAGE_MASK;
728 } else if (exception)
729 *exception = walker.fault;
730
731 return gpa;
732 }
733
734 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
735 u32 access,
736 struct x86_exception *exception)
737 {
738 struct guest_walker walker;
739 gpa_t gpa = UNMAPPED_GVA;
740 int r;
741
742 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
743
744 if (r) {
745 gpa = gfn_to_gpa(walker.gfn);
746 gpa |= vaddr & ~PAGE_MASK;
747 } else if (exception)
748 *exception = walker.fault;
749
750 return gpa;
751 }
752
753 /*
754 * Using the cached information from sp->gfns is safe because:
755 * - The spte has a reference to the struct page, so the pfn for a given gfn
756 * can't change unless all sptes pointing to it are nuked first.
757 *
758 * Note:
759 * We should flush all tlbs if spte is dropped even though guest is
760 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
761 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
762 * used by guest then tlbs are not flushed, so guest is allowed to access the
763 * freed pages.
764 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
765 */
766 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
767 {
768 int i, offset, nr_present;
769 bool host_writable;
770 gpa_t first_pte_gpa;
771
772 offset = nr_present = 0;
773
774 /* direct kvm_mmu_page can not be unsync. */
775 BUG_ON(sp->role.direct);
776
777 if (PTTYPE == 32)
778 offset = sp->role.quadrant << PT64_LEVEL_BITS;
779
780 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
781
782 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
783 unsigned pte_access;
784 pt_element_t gpte;
785 gpa_t pte_gpa;
786 gfn_t gfn;
787
788 if (!sp->spt[i])
789 continue;
790
791 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
792
793 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
794 sizeof(pt_element_t)))
795 return -EINVAL;
796
797 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
798 vcpu->kvm->tlbs_dirty++;
799 continue;
800 }
801
802 gfn = gpte_to_gfn(gpte);
803 pte_access = sp->role.access;
804 pte_access &= FNAME(gpte_access)(vcpu, gpte, true);
805
806 if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present))
807 continue;
808
809 if (gfn != sp->gfns[i]) {
810 drop_spte(vcpu->kvm, &sp->spt[i]);
811 vcpu->kvm->tlbs_dirty++;
812 continue;
813 }
814
815 nr_present++;
816
817 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
818
819 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
820 PT_PAGE_TABLE_LEVEL, gfn,
821 spte_to_pfn(sp->spt[i]), true, false,
822 host_writable);
823 }
824
825 return !nr_present;
826 }
827
828 #undef pt_element_t
829 #undef guest_walker
830 #undef FNAME
831 #undef PT_BASE_ADDR_MASK
832 #undef PT_INDEX
833 #undef PT_LVL_ADDR_MASK
834 #undef PT_LVL_OFFSET_MASK
835 #undef PT_LEVEL_BITS
836 #undef PT_MAX_FULL_LEVELS
837 #undef gpte_to_gfn
838 #undef gpte_to_gfn_lvl
839 #undef CMPXCHG
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