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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / gpu / drm / nouveau / nouveau_hw.c
blobba896e54b799bfd43b92291358234197c4cd56b3
1 /*
2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #include "drmP.h"
26 #include "nouveau_drv.h"
27 #include "nouveau_hw.h"
28
29 #define CHIPSET_NFORCE 0x01a0
30 #define CHIPSET_NFORCE2 0x01f0
31
32 /*
33 * misc hw access wrappers/control functions
34 */
35
36 void
37 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
38 {
39 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
40 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
41 }
42
43 uint8_t
44 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
45 {
46 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
47 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
48 }
49
50 void
51 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
52 {
53 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
54 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
55 }
56
57 uint8_t
58 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
59 {
60 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
61 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
62 }
63
64 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
65 * it affects only the 8 bit vga io regs, which we access using mmio at
66 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
67 * in general, the set value of cr44 does not matter: reg access works as
68 * expected and values can be set for the appropriate head by using a 0x2000
69 * offset as required
70 * however:
71 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
72 * cr44 must be set to 0 or 3 for accessing values on the correct head
73 * through the common 0xc03c* addresses
74 * b) in tied mode (4) head B is programmed to the values set on head A, and
75 * access using the head B addresses can have strange results, ergo we leave
76 * tied mode in init once we know to what cr44 should be restored on exit
77 *
78 * the owner parameter is slightly abused:
79 * 0 and 1 are treated as head values and so the set value is (owner * 3)
80 * other values are treated as literal values to set
81 */
82 void
83 NVSetOwner(struct drm_device *dev, int owner)
84 {
85 struct drm_nouveau_private *dev_priv = dev->dev_private;
86
87 if (owner == 1)
88 owner *= 3;
89
90 if (dev_priv->chipset == 0x11) {
91 /* This might seem stupid, but the blob does it and
92 * omitting it often locks the system up.
93 */
94 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
95 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
96 }
97
98 /* CR44 is always changed on CRTC0 */
99 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
100
101 if (dev_priv->chipset == 0x11) { /* set me harder */
102 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
103 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
104 }
105 }
106
107 void
108 NVBlankScreen(struct drm_device *dev, int head, bool blank)
109 {
110 unsigned char seq1;
111
112 if (nv_two_heads(dev))
113 NVSetOwner(dev, head);
114
115 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
116
117 NVVgaSeqReset(dev, head, true);
118 if (blank)
119 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
120 else
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
122 NVVgaSeqReset(dev, head, false);
123 }
124
125 /*
126 * PLL setting
127 */
128
129 static int
130 powerctrl_1_shift(int chip_version, int reg)
131 {
132 int shift = -4;
133
134 if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
135 return shift;
136
137 switch (reg) {
138 case NV_RAMDAC_VPLL2:
139 shift += 4;
140 case NV_PRAMDAC_VPLL_COEFF:
141 shift += 4;
142 case NV_PRAMDAC_MPLL_COEFF:
143 shift += 4;
144 case NV_PRAMDAC_NVPLL_COEFF:
145 shift += 4;
146 }
147
148 /*
149 * the shift for vpll regs is only used for nv3x chips with a single
150 * stage pll
151 */
152 if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
153 chip_version == 0x36 || chip_version >= 0x40))
154 shift = -4;
155
156 return shift;
157 }
158
159 static void
160 setPLL_single(struct drm_device *dev, uint32_t reg, struct nouveau_pll_vals *pv)
161 {
162 struct drm_nouveau_private *dev_priv = dev->dev_private;
163 int chip_version = dev_priv->vbios.chip_version;
164 uint32_t oldpll = NVReadRAMDAC(dev, 0, reg);
165 int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
166 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
167 uint32_t saved_powerctrl_1 = 0;
168 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
169
170 if (oldpll == pll)
171 return; /* already set */
172
173 if (shift_powerctrl_1 >= 0) {
174 saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1);
175 nvWriteMC(dev, NV_PBUS_POWERCTRL_1,
176 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
177 1 << shift_powerctrl_1);
178 }
179
180 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
181 /* upclock -- write new post divider first */
182 NVWriteRAMDAC(dev, 0, reg, pv->log2P << 16 | (oldpll & 0xffff));
183 else
184 /* downclock -- write new NM first */
185 NVWriteRAMDAC(dev, 0, reg, (oldpll & 0xffff0000) | pv->NM1);
186
187 if (chip_version < 0x17 && chip_version != 0x11)
188 /* wait a bit on older chips */
189 msleep(64);
190 NVReadRAMDAC(dev, 0, reg);
191
192 /* then write the other half as well */
193 NVWriteRAMDAC(dev, 0, reg, pll);
194
195 if (shift_powerctrl_1 >= 0)
196 nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
197 }
198
199 static uint32_t
200 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
201 {
202 bool head_a = (reg1 == NV_PRAMDAC_VPLL_COEFF);
203
204 if (ss) /* single stage pll mode */
205 ramdac580 |= head_a ? NV_RAMDAC_580_VPLL1_ACTIVE :
206 NV_RAMDAC_580_VPLL2_ACTIVE;
207 else
208 ramdac580 &= head_a ? ~NV_RAMDAC_580_VPLL1_ACTIVE :
209 ~NV_RAMDAC_580_VPLL2_ACTIVE;
210
211 return ramdac580;
212 }
213
214 static void
215 setPLL_double_highregs(struct drm_device *dev, uint32_t reg1,
216 struct nouveau_pll_vals *pv)
217 {
218 struct drm_nouveau_private *dev_priv = dev->dev_private;
219 int chip_version = dev_priv->vbios.chip_version;
220 bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
221 uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
222 uint32_t oldpll1 = NVReadRAMDAC(dev, 0, reg1);
223 uint32_t oldpll2 = !nv3035 ? NVReadRAMDAC(dev, 0, reg2) : 0;
224 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
225 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
226 uint32_t oldramdac580 = 0, ramdac580 = 0;
227 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
228 uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
229 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
230
231 /* model specific additions to generic pll1 and pll2 set up above */
232 if (nv3035) {
233 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
234 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
235 pll2 = 0;
236 }
237 if (chip_version > 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { /* !nv40 */
238 oldramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
239 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
240 if (oldramdac580 != ramdac580)
241 oldpll1 = ~0; /* force mismatch */
242 if (single_stage)
243 /* magic value used by nvidia in single stage mode */
244 pll2 |= 0x011f;
245 }
246 if (chip_version > 0x70)
247 /* magic bits set by the blob (but not the bios) on g71-73 */
248 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
249
250 if (oldpll1 == pll1 && oldpll2 == pll2)
251 return; /* already set */
252
253 if (shift_powerctrl_1 >= 0) {
254 saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1);
255 nvWriteMC(dev, NV_PBUS_POWERCTRL_1,
256 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
257 1 << shift_powerctrl_1);
258 }
259
260 if (chip_version >= 0x40) {
261 int shift_c040 = 14;
262
263 switch (reg1) {
264 case NV_PRAMDAC_MPLL_COEFF:
265 shift_c040 += 2;
266 case NV_PRAMDAC_NVPLL_COEFF:
267 shift_c040 += 2;
268 case NV_RAMDAC_VPLL2:
269 shift_c040 += 2;
270 case NV_PRAMDAC_VPLL_COEFF:
271 shift_c040 += 2;
272 }
273
274 savedc040 = nvReadMC(dev, 0xc040);
275 if (shift_c040 != 14)
276 nvWriteMC(dev, 0xc040, savedc040 & ~(3 << shift_c040));
277 }
278
279 if (oldramdac580 != ramdac580)
280 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_580, ramdac580);
281
282 if (!nv3035)
283 NVWriteRAMDAC(dev, 0, reg2, pll2);
284 NVWriteRAMDAC(dev, 0, reg1, pll1);
285
286 if (shift_powerctrl_1 >= 0)
287 nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
288 if (chip_version >= 0x40)
289 nvWriteMC(dev, 0xc040, savedc040);
290 }
291
292 static void
293 setPLL_double_lowregs(struct drm_device *dev, uint32_t NMNMreg,
294 struct nouveau_pll_vals *pv)
295 {
296 /* When setting PLLs, there is a merry game of disabling and enabling
297 * various bits of hardware during the process. This function is a
298 * synthesis of six nv4x traces, nearly each card doing a subtly
299 * different thing. With luck all the necessary bits for each card are
300 * combined herein. Without luck it deviates from each card's formula
301 * so as to not work on any :)
302 */
303
304 uint32_t Preg = NMNMreg - 4;
305 bool mpll = Preg == 0x4020;
306 uint32_t oldPval = nvReadMC(dev, Preg);
307 uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
308 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
309 0xc << 28 | pv->log2P << 16;
310 uint32_t saved4600 = 0;
311 /* some cards have different maskc040s */
312 uint32_t maskc040 = ~(3 << 14), savedc040;
313 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
314
315 if (nvReadMC(dev, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
316 return;
317
318 if (Preg == 0x4000)
319 maskc040 = ~0x333;
320 if (Preg == 0x4058)
321 maskc040 = ~(0xc << 24);
322
323 if (mpll) {
324 struct pll_lims pll_lim;
325 uint8_t Pval2;
326
327 if (get_pll_limits(dev, Preg, &pll_lim))
328 return;
329
330 Pval2 = pv->log2P + pll_lim.log2p_bias;
331 if (Pval2 > pll_lim.max_log2p)
332 Pval2 = pll_lim.max_log2p;
333 Pval |= 1 << 28 | Pval2 << 20;
334
335 saved4600 = nvReadMC(dev, 0x4600);
336 nvWriteMC(dev, 0x4600, saved4600 | 8 << 28);
337 }
338 if (single_stage)
339 Pval |= mpll ? 1 << 12 : 1 << 8;
340
341 nvWriteMC(dev, Preg, oldPval | 1 << 28);
342 nvWriteMC(dev, Preg, Pval & ~(4 << 28));
343 if (mpll) {
344 Pval |= 8 << 20;
345 nvWriteMC(dev, 0x4020, Pval & ~(0xc << 28));
346 nvWriteMC(dev, 0x4038, Pval & ~(0xc << 28));
347 }
348
349 savedc040 = nvReadMC(dev, 0xc040);
350 nvWriteMC(dev, 0xc040, savedc040 & maskc040);
351
352 nvWriteMC(dev, NMNMreg, NMNM);
353 if (NMNMreg == 0x4024)
354 nvWriteMC(dev, 0x403c, NMNM);
355
356 nvWriteMC(dev, Preg, Pval);
357 if (mpll) {
358 Pval &= ~(8 << 20);
359 nvWriteMC(dev, 0x4020, Pval);
360 nvWriteMC(dev, 0x4038, Pval);
361 nvWriteMC(dev, 0x4600, saved4600);
362 }
363
364 nvWriteMC(dev, 0xc040, savedc040);
365
366 if (mpll) {
367 nvWriteMC(dev, 0x4020, Pval & ~(1 << 28));
368 nvWriteMC(dev, 0x4038, Pval & ~(1 << 28));
369 }
370 }
371
372 void
373 nouveau_hw_setpll(struct drm_device *dev, uint32_t reg1,
374 struct nouveau_pll_vals *pv)
375 {
376 struct drm_nouveau_private *dev_priv = dev->dev_private;
377 int cv = dev_priv->vbios.chip_version;
378
379 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
380 cv >= 0x40) {
381 if (reg1 > 0x405c)
382 setPLL_double_highregs(dev, reg1, pv);
383 else
384 setPLL_double_lowregs(dev, reg1, pv);
385 } else
386 setPLL_single(dev, reg1, pv);
387 }
388
389 /*
390 * PLL getting
391 */
392
393 static void
394 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
395 uint32_t pll2, struct nouveau_pll_vals *pllvals)
396 {
397 struct drm_nouveau_private *dev_priv = dev->dev_private;
398
399 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
400
401 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
402 pllvals->log2P = (pll1 >> 16) & 0x7;
403 pllvals->N2 = pllvals->M2 = 1;
404
405 if (reg1 <= 0x405c) {
406 pllvals->NM1 = pll2 & 0xffff;
407 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
408 if (!(pll1 & 0x1100))
409 pllvals->NM2 = pll2 >> 16;
410 } else {
411 pllvals->NM1 = pll1 & 0xffff;
412 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
413 pllvals->NM2 = pll2 & 0xffff;
414 else if (dev_priv->chipset == 0x30 || dev_priv->chipset == 0x35) {
415 pllvals->M1 &= 0xf; /* only 4 bits */
416 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
417 pllvals->M2 = (pll1 >> 4) & 0x7;
418 pllvals->N2 = ((pll1 >> 21) & 0x18) |
419 ((pll1 >> 19) & 0x7);
420 }
421 }
422 }
423 }
424
425 int
426 nouveau_hw_get_pllvals(struct drm_device *dev, enum pll_types plltype,
427 struct nouveau_pll_vals *pllvals)
428 {
429 struct drm_nouveau_private *dev_priv = dev->dev_private;
430 uint32_t reg1 = get_pll_register(dev, plltype), pll1, pll2 = 0;
431 struct pll_lims pll_lim;
432 int ret;
433
434 if (reg1 == 0)
435 return -ENOENT;
436
437 pll1 = nvReadMC(dev, reg1);
438
439 if (reg1 <= 0x405c)
440 pll2 = nvReadMC(dev, reg1 + 4);
441 else if (nv_two_reg_pll(dev)) {
442 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
443
444 pll2 = nvReadMC(dev, reg2);
445 }
446
447 if (dev_priv->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
448 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
449
450 /* check whether vpll has been forced into single stage mode */
451 if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
452 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
453 pll2 = 0;
454 } else
455 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)
456 pll2 = 0;
457 }
458
459 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
460
461 ret = get_pll_limits(dev, plltype, &pll_lim);
462 if (ret)
463 return ret;
464
465 pllvals->refclk = pll_lim.refclk;
466
467 return 0;
468 }
469
470 int
471 nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv)
472 {
473 /* Avoid divide by zero if called at an inappropriate time */
474 if (!pv->M1 || !pv->M2)
475 return 0;
476
477 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
478 }
479
480 int
481 nouveau_hw_get_clock(struct drm_device *dev, enum pll_types plltype)
482 {
483 struct nouveau_pll_vals pllvals;
484 int ret;
485
486 if (plltype == PLL_MEMORY &&
487 (dev->pci_device & 0x0ff0) == CHIPSET_NFORCE) {
488 uint32_t mpllP;
489
490 pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
491 if (!mpllP)
492 mpllP = 4;
493
494 return 400000 / mpllP;
495 } else
496 if (plltype == PLL_MEMORY &&
497 (dev->pci_device & 0xff0) == CHIPSET_NFORCE2) {
498 uint32_t clock;
499
500 pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
501 return clock;
502 }
503
504 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
505 if (ret)
506 return ret;
507
508 return nouveau_hw_pllvals_to_clk(&pllvals);
509 }
510
511 static void
512 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
513 {
514 /* the vpll on an unused head can come up with a random value, way
515 * beyond the pll limits. for some reason this causes the chip to
516 * lock up when reading the dac palette regs, so set a valid pll here
517 * when such a condition detected. only seen on nv11 to date
518 */
519
520 struct pll_lims pll_lim;
521 struct nouveau_pll_vals pv;
522 enum pll_types pll = head ? PLL_VPLL1 : PLL_VPLL0;
523
524 if (get_pll_limits(dev, pll, &pll_lim))
525 return;
526 nouveau_hw_get_pllvals(dev, pll, &pv);
527
528 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
529 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
530 pv.log2P <= pll_lim.max_log2p)
531 return;
532
533 NV_WARN(dev, "VPLL %d outwith limits, attempting to fix\n", head + 1);
534
535 /* set lowest clock within static limits */
536 pv.M1 = pll_lim.vco1.max_m;
537 pv.N1 = pll_lim.vco1.min_n;
538 pv.log2P = pll_lim.max_usable_log2p;
539 nouveau_hw_setpll(dev, pll_lim.reg, &pv);
540 }
541
542 /*
543 * vga font save/restore
544 */
545
546 static void nouveau_vga_font_io(struct drm_device *dev,
547 void __iomem *iovram,
548 bool save, unsigned plane)
549 {
550 struct drm_nouveau_private *dev_priv = dev->dev_private;
551 unsigned i;
552
553 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
554 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane);
555 for (i = 0; i < 16384; i++) {
556 if (save) {
557 dev_priv->saved_vga_font[plane][i] =
558 ioread32_native(iovram + i * 4);
559 } else {
560 iowrite32_native(dev_priv->saved_vga_font[plane][i],
561 iovram + i * 4);
562 }
563 }
564 }
565
566 void
567 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
568 {
569 uint8_t misc, gr4, gr5, gr6, seq2, seq4;
570 bool graphicsmode;
571 unsigned plane;
572 void __iomem *iovram;
573
574 if (nv_two_heads(dev))
575 NVSetOwner(dev, 0);
576
577 NVSetEnablePalette(dev, 0, true);
578 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1;
579 NVSetEnablePalette(dev, 0, false);
580
581 if (graphicsmode) /* graphics mode => framebuffer => no need to save */
582 return;
583
584 NV_INFO(dev, "%sing VGA fonts\n", save ? "Sav" : "Restor");
585
586 /* map first 64KiB of VRAM, holds VGA fonts etc */
587 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536);
588 if (!iovram) {
589 NV_ERROR(dev, "Failed to map VRAM, "
590 "cannot save/restore VGA fonts.\n");
591 return;
592 }
593
594 if (nv_two_heads(dev))
595 NVBlankScreen(dev, 1, true);
596 NVBlankScreen(dev, 0, true);
597
598 /* save control regs */
599 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ);
600 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX);
601 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX);
602 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX);
603 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX);
604 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX);
605
606 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67);
607 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
608 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0);
609 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5);
610
611 /* store font in planes 0..3 */
612 for (plane = 0; plane < 4; plane++)
613 nouveau_vga_font_io(dev, iovram, save, plane);
614
615 /* restore control regs */
616 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc);
617 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
618 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5);
619 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6);
620 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
621 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
622
623 if (nv_two_heads(dev))
624 NVBlankScreen(dev, 1, false);
625 NVBlankScreen(dev, 0, false);
626
627 iounmap(iovram);
628 }
629
630 /*
631 * mode state save/load
632 */
633
634 static void
635 rd_cio_state(struct drm_device *dev, int head,
636 struct nv04_crtc_reg *crtcstate, int index)
637 {
638 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
639 }
640
641 static void
642 wr_cio_state(struct drm_device *dev, int head,
643 struct nv04_crtc_reg *crtcstate, int index)
644 {
645 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
646 }
647
648 static void
649 nv_save_state_ramdac(struct drm_device *dev, int head,
650 struct nv04_mode_state *state)
651 {
652 struct drm_nouveau_private *dev_priv = dev->dev_private;
653 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
654 int i;
655
656 if (dev_priv->card_type >= NV_10)
657 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
658
659 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
660 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
661 if (nv_two_heads(dev))
662 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
663 if (dev_priv->chipset == 0x11)
664 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
665
666 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
667
668 if (nv_gf4_disp_arch(dev))
669 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
670 if (dev_priv->chipset >= 0x30)
671 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
672
673 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
674 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
675 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
676 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
677 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
678 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
679 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
680 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
681
682 for (i = 0; i < 7; i++) {
683 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
684 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
685 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
686 }
687
688 if (nv_gf4_disp_arch(dev)) {
689 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
690 for (i = 0; i < 3; i++) {
691 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
692 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
693 }
694 }
695
696 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
697 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
698 if (!nv_gf4_disp_arch(dev) && head == 0) {
699 /* early chips don't allow access to PRAMDAC_TMDS_* without
700 * the head A FPCLK on (nv11 even locks up) */
701 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
702 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK);
703 }
704 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
705 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
706
707 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
708
709 if (nv_gf4_disp_arch(dev))
710 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
711
712 if (dev_priv->card_type == NV_40) {
713 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
714 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
715 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
716
717 for (i = 0; i < 38; i++)
718 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
719 NV_PRAMDAC_CTV + 4*i);
720 }
721 }
722
723 static void
724 nv_load_state_ramdac(struct drm_device *dev, int head,
725 struct nv04_mode_state *state)
726 {
727 struct drm_nouveau_private *dev_priv = dev->dev_private;
728 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
729 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
730 int i;
731
732 if (dev_priv->card_type >= NV_10)
733 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
734
735 nouveau_hw_setpll(dev, pllreg, &regp->pllvals);
736 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
737 if (nv_two_heads(dev))
738 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
739 if (dev_priv->chipset == 0x11)
740 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
741
742 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
743
744 if (nv_gf4_disp_arch(dev))
745 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
746 if (dev_priv->chipset >= 0x30)
747 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
748
749 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
750 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
751 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
752 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
753 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
754 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
755 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
756 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
757
758 for (i = 0; i < 7; i++) {
759 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
760
761 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
762 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
763 }
764
765 if (nv_gf4_disp_arch(dev)) {
766 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
767 for (i = 0; i < 3; i++) {
768 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
769 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
770 }
771 }
772
773 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
774 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
775 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
776 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
777
778 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
779
780 if (nv_gf4_disp_arch(dev))
781 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
782
783 if (dev_priv->card_type == NV_40) {
784 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
785 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
786 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
787
788 for (i = 0; i < 38; i++)
789 NVWriteRAMDAC(dev, head,
790 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
791 }
792 }
793
794 static void
795 nv_save_state_vga(struct drm_device *dev, int head,
796 struct nv04_mode_state *state)
797 {
798 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
799 int i;
800
801 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
802
803 for (i = 0; i < 25; i++)
804 rd_cio_state(dev, head, regp, i);
805
806 NVSetEnablePalette(dev, head, true);
807 for (i = 0; i < 21; i++)
808 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
809 NVSetEnablePalette(dev, head, false);
810
811 for (i = 0; i < 9; i++)
812 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
813
814 for (i = 0; i < 5; i++)
815 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
816 }
817
818 static void
819 nv_load_state_vga(struct drm_device *dev, int head,
820 struct nv04_mode_state *state)
821 {
822 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
823 int i;
824
825 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
826
827 for (i = 0; i < 5; i++)
828 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
829
830 nv_lock_vga_crtc_base(dev, head, false);
831 for (i = 0; i < 25; i++)
832 wr_cio_state(dev, head, regp, i);
833 nv_lock_vga_crtc_base(dev, head, true);
834
835 for (i = 0; i < 9; i++)
836 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
837
838 NVSetEnablePalette(dev, head, true);
839 for (i = 0; i < 21; i++)
840 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
841 NVSetEnablePalette(dev, head, false);
842 }
843
844 static void
845 nv_save_state_ext(struct drm_device *dev, int head,
846 struct nv04_mode_state *state)
847 {
848 struct drm_nouveau_private *dev_priv = dev->dev_private;
849 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
850 int i;
851
852 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
853 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
854 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
855 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
856 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
857 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
858 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
859
860 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
861 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
862 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
863
864 if (dev_priv->card_type >= NV_20)
865 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
866
867 if (dev_priv->card_type >= NV_30)
868 rd_cio_state(dev, head, regp, 0x9f);
869
870 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
871 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
872 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
873 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
874 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
875
876 if (dev_priv->card_type >= NV_10) {
877 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
878 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
879
880 if (dev_priv->card_type >= NV_30)
881 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
882
883 if (dev_priv->card_type == NV_40)
884 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
885
886 if (nv_two_heads(dev))
887 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
888 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
889 }
890
891 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
892
893 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
894 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
895 if (dev_priv->card_type >= NV_10) {
896 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
897 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
898 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
899 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
900 }
901 /* NV11 and NV20 don't have this, they stop at 0x52. */
902 if (nv_gf4_disp_arch(dev)) {
903 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
904 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
905 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
906
907 for (i = 0; i < 0x10; i++)
908 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
909 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
910 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
911
912 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
913 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
914 }
915
916 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
917 }
918
919 static void
920 nv_load_state_ext(struct drm_device *dev, int head,
921 struct nv04_mode_state *state)
922 {
923 struct drm_nouveau_private *dev_priv = dev->dev_private;
924 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
925 uint32_t reg900;
926 int i;
927
928 if (dev_priv->card_type >= NV_10) {
929 if (nv_two_heads(dev))
930 /* setting ENGINE_CTRL (EC) *must* come before
931 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
932 * EC that should not be overwritten by writing stale EC
933 */
934 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
935
936 nvWriteVIDEO(dev, NV_PVIDEO_STOP, 1);
937 nvWriteVIDEO(dev, NV_PVIDEO_INTR_EN, 0);
938 nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(0), 0);
939 nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(1), 0);
940 nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(0), dev_priv->fb_available_size - 1);
941 nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(1), dev_priv->fb_available_size - 1);
942 nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(0), dev_priv->fb_available_size - 1);
943 nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(1), dev_priv->fb_available_size - 1);
944 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
945
946 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
947 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
948 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
949
950 if (dev_priv->card_type >= NV_30)
951 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
952
953 if (dev_priv->card_type == NV_40) {
954 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
955
956 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
957 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
958 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
959 else
960 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
961 }
962 }
963
964 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
965
966 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
967 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
968 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
969 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
970 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
971 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
972 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
973 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
974 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
975
976 if (dev_priv->card_type >= NV_20)
977 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
978
979 if (dev_priv->card_type >= NV_30)
980 wr_cio_state(dev, head, regp, 0x9f);
981
982 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
983 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
984 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
985 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
986 if (dev_priv->card_type == NV_40)
987 nv_fix_nv40_hw_cursor(dev, head);
988 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
989
990 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
991 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
992 if (dev_priv->card_type >= NV_10) {
993 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
994 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
995 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
996 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
997 }
998 /* NV11 and NV20 stop at 0x52. */
999 if (nv_gf4_disp_arch(dev)) {
1000 if (dev_priv->card_type == NV_10) {
1001 /* Not waiting for vertical retrace before modifying
1002 CRE_53/CRE_54 causes lockups. */
1003 nouveau_wait_eq(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
1004 nouveau_wait_eq(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
1005 }
1006
1007 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
1008 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
1009 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
1010
1011 for (i = 0; i < 0x10; i++)
1012 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
1013 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
1014 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
1015
1016 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
1017 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
1018 }
1019
1020 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
1021
1022 /* Enable vblank interrupts. */
1023 NVWriteCRTC(dev, head, NV_PCRTC_INTR_EN_0,
1024 (dev->vblank_enabled[head] ? 1 : 0));
1025 NVWriteCRTC(dev, head, NV_PCRTC_INTR_0, NV_PCRTC_INTR_0_VBLANK);
1026 }
1027
1028 static void
1029 nv_save_state_palette(struct drm_device *dev, int head,
1030 struct nv04_mode_state *state)
1031 {
1032 int head_offset = head * NV_PRMDIO_SIZE, i;
1033
1034 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset,
1035 NV_PRMDIO_PIXEL_MASK_MASK);
1036 nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
1037
1038 for (i = 0; i < 768; i++) {
1039 state->crtc_reg[head].DAC[i] = nv_rd08(dev,
1040 NV_PRMDIO_PALETTE_DATA + head_offset);
1041 }
1042
1043 NVSetEnablePalette(dev, head, false);
1044 }
1045
1046 void
1047 nouveau_hw_load_state_palette(struct drm_device *dev, int head,
1048 struct nv04_mode_state *state)
1049 {
1050 int head_offset = head * NV_PRMDIO_SIZE, i;
1051
1052 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset,
1053 NV_PRMDIO_PIXEL_MASK_MASK);
1054 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
1055
1056 for (i = 0; i < 768; i++) {
1057 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA + head_offset,
1058 state->crtc_reg[head].DAC[i]);
1059 }
1060
1061 NVSetEnablePalette(dev, head, false);
1062 }
1063
1064 void nouveau_hw_save_state(struct drm_device *dev, int head,
1065 struct nv04_mode_state *state)
1066 {
1067 struct drm_nouveau_private *dev_priv = dev->dev_private;
1068
1069 if (dev_priv->chipset == 0x11)
1070 /* NB: no attempt is made to restore the bad pll later on */
1071 nouveau_hw_fix_bad_vpll(dev, head);
1072 nv_save_state_ramdac(dev, head, state);
1073 nv_save_state_vga(dev, head, state);
1074 nv_save_state_palette(dev, head, state);
1075 nv_save_state_ext(dev, head, state);
1076 }
1077
1078 void nouveau_hw_load_state(struct drm_device *dev, int head,
1079 struct nv04_mode_state *state)
1080 {
1081 NVVgaProtect(dev, head, true);
1082 nv_load_state_ramdac(dev, head, state);
1083 nv_load_state_ext(dev, head, state);
1084 nouveau_hw_load_state_palette(dev, head, state);
1085 nv_load_state_vga(dev, head, state);
1086 NVVgaProtect(dev, head, false);
1087 }
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