Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / gpu / drm / nouveau / nouveau_perf.c
blobef9dec0e6f8b343c293eb7002560686838731180
1 /*
2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs
25 #include "drmP.h"
27 #include "nouveau_drv.h"
28 #include "nouveau_pm.h"
30 static void
31 legacy_perf_init(struct drm_device *dev)
33 struct drm_nouveau_private *dev_priv = dev->dev_private;
34 struct nvbios *bios = &dev_priv->vbios;
35 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
36 char *perf, *entry, *bmp = &bios->data[bios->offset];
37 int headerlen, use_straps;
39 if (bmp[5] < 0x5 || bmp[6] < 0x14) {
40 NV_DEBUG(dev, "BMP version too old for perf\n");
41 return;
44 perf = ROMPTR(bios, bmp[0x73]);
45 if (!perf) {
46 NV_DEBUG(dev, "No memclock table pointer found.\n");
47 return;
50 switch (perf[0]) {
51 case 0x12:
52 case 0x14:
53 case 0x18:
54 use_straps = 0;
55 headerlen = 1;
56 break;
57 case 0x01:
58 use_straps = perf[1] & 1;
59 headerlen = (use_straps ? 8 : 2);
60 break;
61 default:
62 NV_WARN(dev, "Unknown memclock table version %x.\n", perf[0]);
63 return;
66 entry = perf + headerlen;
67 if (use_straps)
68 entry += (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;
70 sprintf(pm->perflvl[0].name, "performance_level_0");
71 pm->perflvl[0].memory = ROM16(entry[0]) * 20;
72 pm->nr_perflvl = 1;
75 static struct nouveau_pm_memtiming *
76 nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P,
77 u16 memclk, u8 *entry, u8 recordlen, u8 entries)
79 struct drm_nouveau_private *dev_priv = dev->dev_private;
80 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
81 struct nvbios *bios = &dev_priv->vbios;
82 u8 ramcfg;
83 int i;
85 /* perf v2 has a separate "timing map" table, we have to match
86 * the target memory clock to a specific entry, *then* use
87 * ramcfg to select the correct subentry
89 if (P->version == 2) {
90 u8 *tmap = ROMPTR(bios, P->data[4]);
91 if (!tmap) {
92 NV_DEBUG(dev, "no timing map pointer\n");
93 return NULL;
96 if (tmap[0] != 0x10) {
97 NV_WARN(dev, "timing map 0x%02x unknown\n", tmap[0]);
98 return NULL;
101 entry = tmap + tmap[1];
102 recordlen = tmap[2] + (tmap[4] * tmap[3]);
103 for (i = 0; i < tmap[5]; i++, entry += recordlen) {
104 if (memclk >= ROM16(entry[0]) &&
105 memclk <= ROM16(entry[2]))
106 break;
109 if (i == tmap[5]) {
110 NV_WARN(dev, "no match in timing map table\n");
111 return NULL;
114 entry += tmap[2];
115 recordlen = tmap[3];
116 entries = tmap[4];
119 ramcfg = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
120 if (bios->ram_restrict_tbl_ptr)
121 ramcfg = bios->data[bios->ram_restrict_tbl_ptr + ramcfg];
123 if (ramcfg >= entries) {
124 NV_WARN(dev, "ramcfg strap out of bounds!\n");
125 return NULL;
128 entry += ramcfg * recordlen;
129 if (entry[1] >= pm->memtimings.nr_timing) {
130 NV_WARN(dev, "timingset %d does not exist\n", entry[1]);
131 return NULL;
134 return &pm->memtimings.timing[entry[1]];
137 void
138 nouveau_perf_init(struct drm_device *dev)
140 struct drm_nouveau_private *dev_priv = dev->dev_private;
141 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
142 struct nvbios *bios = &dev_priv->vbios;
143 struct bit_entry P;
144 u8 version, headerlen, recordlen, entries;
145 u8 *perf, *entry;
146 int vid, i;
148 if (bios->type == NVBIOS_BIT) {
149 if (bit_table(dev, 'P', &P))
150 return;
152 if (P.version != 1 && P.version != 2) {
153 NV_WARN(dev, "unknown perf for BIT P %d\n", P.version);
154 return;
157 perf = ROMPTR(bios, P.data[0]);
158 version = perf[0];
159 headerlen = perf[1];
160 if (version < 0x40) {
161 recordlen = perf[3] + (perf[4] * perf[5]);
162 entries = perf[2];
163 } else {
164 recordlen = perf[2] + (perf[3] * perf[4]);
165 entries = perf[5];
167 } else {
168 if (bios->data[bios->offset + 6] < 0x25) {
169 legacy_perf_init(dev);
170 return;
173 perf = ROMPTR(bios, bios->data[bios->offset + 0x94]);
174 if (!perf) {
175 NV_DEBUG(dev, "perf table pointer invalid\n");
176 return;
179 version = perf[1];
180 headerlen = perf[0];
181 recordlen = perf[3];
182 entries = perf[2];
185 if (entries > NOUVEAU_PM_MAX_LEVEL) {
186 NV_DEBUG(dev, "perf table has too many entries - buggy vbios?\n");
187 entries = NOUVEAU_PM_MAX_LEVEL;
190 entry = perf + headerlen;
191 for (i = 0; i < entries; i++) {
192 struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
194 perflvl->timing = NULL;
196 if (entry[0] == 0xff) {
197 entry += recordlen;
198 continue;
201 switch (version) {
202 case 0x12:
203 case 0x13:
204 case 0x15:
205 perflvl->fanspeed = entry[55];
206 perflvl->voltage = (recordlen > 56) ? entry[56] : 0;
207 perflvl->core = ROM32(entry[1]) * 10;
208 perflvl->memory = ROM32(entry[5]) * 20;
209 break;
210 case 0x21:
211 case 0x23:
212 case 0x24:
213 perflvl->fanspeed = entry[4];
214 perflvl->voltage = entry[5];
215 perflvl->core = ROM16(entry[6]) * 1000;
217 if (dev_priv->chipset == 0x49 ||
218 dev_priv->chipset == 0x4b)
219 perflvl->memory = ROM16(entry[11]) * 1000;
220 else
221 perflvl->memory = ROM16(entry[11]) * 2000;
223 break;
224 case 0x25:
225 perflvl->fanspeed = entry[4];
226 perflvl->voltage = entry[5];
227 perflvl->core = ROM16(entry[6]) * 1000;
228 perflvl->shader = ROM16(entry[10]) * 1000;
229 perflvl->memory = ROM16(entry[12]) * 1000;
230 break;
231 case 0x30:
232 perflvl->memscript = ROM16(entry[2]);
233 case 0x35:
234 perflvl->fanspeed = entry[6];
235 perflvl->voltage = entry[7];
236 perflvl->core = ROM16(entry[8]) * 1000;
237 perflvl->shader = ROM16(entry[10]) * 1000;
238 perflvl->memory = ROM16(entry[12]) * 1000;
239 /*XXX: confirm on 0x35 */
240 perflvl->unk05 = ROM16(entry[16]) * 1000;
241 break;
242 case 0x40:
243 #define subent(n) entry[perf[2] + ((n) * perf[3])]
244 perflvl->fanspeed = 0; /*XXX*/
245 perflvl->voltage = entry[2];
246 if (dev_priv->card_type == NV_50) {
247 perflvl->core = ROM16(subent(0)) & 0xfff;
248 perflvl->shader = ROM16(subent(1)) & 0xfff;
249 perflvl->memory = ROM16(subent(2)) & 0xfff;
250 } else {
251 perflvl->shader = ROM16(subent(3)) & 0xfff;
252 perflvl->core = perflvl->shader / 2;
253 perflvl->unk0a = ROM16(subent(4)) & 0xfff;
254 perflvl->memory = ROM16(subent(5)) & 0xfff;
257 perflvl->core *= 1000;
258 perflvl->shader *= 1000;
259 perflvl->memory *= 1000;
260 perflvl->unk0a *= 1000;
261 break;
264 /* make sure vid is valid */
265 if (pm->voltage.supported && perflvl->voltage) {
266 vid = nouveau_volt_vid_lookup(dev, perflvl->voltage);
267 if (vid < 0) {
268 NV_DEBUG(dev, "drop perflvl %d, bad vid\n", i);
269 entry += recordlen;
270 continue;
274 /* get the corresponding memory timings */
275 if (version > 0x15) {
276 /* last 3 args are for < 0x40, ignored for >= 0x40 */
277 perflvl->timing =
278 nouveau_perf_timing(dev, &P,
279 perflvl->memory / 1000,
280 entry + perf[3],
281 perf[5], perf[4]);
284 snprintf(perflvl->name, sizeof(perflvl->name),
285 "performance_level_%d", i);
286 perflvl->id = i;
287 pm->nr_perflvl++;
289 entry += recordlen;
293 void
294 nouveau_perf_fini(struct drm_device *dev)