drivers/gpu/drm/radeon/r100_track.h

   1
   2 #define R100_TRACK_MAX_TEXTURE 3
   3 #define R200_TRACK_MAX_TEXTURE 6
   4 #define R300_TRACK_MAX_TEXTURE 16
   5
   6 #define R100_MAX_CB 1
   7 #define R300_MAX_CB 4
   8
   9 /*
  10  * CS functions
  11  */
  12 struct r100_cs_track_cb {
  13         struct radeon_bo        *robj;
  14         unsigned                pitch;
  15         unsigned                cpp;
  16         unsigned                offset;
  17 };
  18
  19 struct r100_cs_track_array {
  20         struct radeon_bo        *robj;
  21         unsigned                esize;
  22 };
  23
  24 struct r100_cs_cube_info {
  25         struct radeon_bo        *robj;
  26         unsigned                offset;
  27         unsigned                width;
  28         unsigned                height;
  29 };
  30
  31 #define R100_TRACK_COMP_NONE   0
  32 #define R100_TRACK_COMP_DXT1   1
  33 #define R100_TRACK_COMP_DXT35  2
  34
  35 struct r100_cs_track_texture {
  36         struct radeon_bo        *robj;
  37         struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
  38         unsigned                pitch;
  39         unsigned                width;
  40         unsigned                height;
  41         unsigned                num_levels;
  42         unsigned                cpp;
  43         unsigned                tex_coord_type;
  44         unsigned                txdepth;
  45         unsigned                width_11;
  46         unsigned                height_11;
  47         bool                    use_pitch;
  48         bool                    enabled;
  49         bool                    lookup_disable;
  50         bool                    roundup_w;
  51         bool                    roundup_h;
  52         unsigned                compress_format;
  53 };
  54
  55 struct r100_cs_track {
  56         unsigned                        num_cb;
  57         unsigned                        num_texture;
  58         unsigned                        maxy;
  59         unsigned                        vtx_size;
  60         unsigned                        vap_vf_cntl;
  61         unsigned                        vap_alt_nverts;
  62         unsigned                        immd_dwords;
  63         unsigned                        num_arrays;
  64         unsigned                        max_indx;
  65         unsigned                        color_channel_mask;
  66         struct r100_cs_track_array      arrays[16];
  67         struct r100_cs_track_cb         cb[R300_MAX_CB];
  68         struct r100_cs_track_cb         zb;
  69         struct r100_cs_track_cb         aa;
  70         struct r100_cs_track_texture    textures[R300_TRACK_MAX_TEXTURE];
  71         bool                            z_enabled;
  72         bool                            separate_cube;
  73         bool                            zb_cb_clear;
  74         bool                            blend_read_enable;
  75         bool                            cb_dirty;
  76         bool                            zb_dirty;
  77         bool                            tex_dirty;
  78         bool                            aa_dirty;
  79         bool                            aaresolve;
  80 };
  81
  82 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
  83 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
  84 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
  85                               struct radeon_cs_reloc **cs_reloc);
  86 void r100_cs_dump_packet(struct radeon_cs_parser *p,
  87                          struct radeon_cs_packet *pkt);
  88
  89 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
  90
  91 int r200_packet0_check(struct radeon_cs_parser *p,
  92                        struct radeon_cs_packet *pkt,
  93                        unsigned idx, unsigned reg);
  94
  95
  96
  97 static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
  98                                           struct radeon_cs_packet *pkt,
  99                                           unsigned idx,
 100                                           unsigned reg)
 101 {
 102         int r;
 103         u32 tile_flags = 0;
 104         u32 tmp;
 105         struct radeon_cs_reloc *reloc;
 106         u32 value;
 107
 108         r = r100_cs_packet_next_reloc(p, &reloc);
 109         if (r) {
 110                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 111                           idx, reg);
 112                 r100_cs_dump_packet(p, pkt);
 113                 return r;
 114         }
 115         value = radeon_get_ib_value(p, idx);
 116         tmp = value & 0x003fffff;
 117         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
 118
 119         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 120                 tile_flags |= RADEON_DST_TILE_MACRO;
 121         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
 122                 if (reg == RADEON_SRC_PITCH_OFFSET) {
 123                         DRM_ERROR("Cannot src blit from microtiled surface\n");
 124                         r100_cs_dump_packet(p, pkt);
 125                         return -EINVAL;
 126                 }
 127                 tile_flags |= RADEON_DST_TILE_MICRO;
 128         }
 129
 130         tmp |= tile_flags;
 131         p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
 132         return 0;
 133 }
 134
 135 static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
 136                                            struct radeon_cs_packet *pkt,
 137                                            int idx)
 138 {
 139         unsigned c, i;
 140         struct radeon_cs_reloc *reloc;
 141         struct r100_cs_track *track;
 142         int r = 0;
 143         volatile uint32_t *ib;
 144         u32 idx_value;
 145
 146         ib = p->ib->ptr;
 147         track = (struct r100_cs_track *)p->track;
 148         c = radeon_get_ib_value(p, idx++) & 0x1F;
 149         if (c > 16) {
 150             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
 151                       pkt->opcode);
 152             r100_cs_dump_packet(p, pkt);
 153             return -EINVAL;
 154         }
 155         track->num_arrays = c;
 156         for (i = 0; i < (c - 1); i+=2, idx+=3) {
 157                 r = r100_cs_packet_next_reloc(p, &reloc);
 158                 if (r) {
 159                         DRM_ERROR("No reloc for packet3 %d\n",
 160                                   pkt->opcode);
 161                         r100_cs_dump_packet(p, pkt);
 162                         return r;
 163                 }
 164                 idx_value = radeon_get_ib_value(p, idx);
 165                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 166
 167                 track->arrays[i + 0].esize = idx_value >> 8;
 168                 track->arrays[i + 0].robj = reloc->robj;
 169                 track->arrays[i + 0].esize &= 0x7F;
 170                 r = r100_cs_packet_next_reloc(p, &reloc);
 171                 if (r) {
 172                         DRM_ERROR("No reloc for packet3 %d\n",
 173                                   pkt->opcode);
 174                         r100_cs_dump_packet(p, pkt);
 175                         return r;
 176                 }
 177                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
 178                 track->arrays[i + 1].robj = reloc->robj;
 179                 track->arrays[i + 1].esize = idx_value >> 24;
 180                 track->arrays[i + 1].esize &= 0x7F;
 181         }
 182         if (c & 1) {
 183                 r = r100_cs_packet_next_reloc(p, &reloc);
 184                 if (r) {
 185                         DRM_ERROR("No reloc for packet3 %d\n",
 186                                           pkt->opcode);
 187                         r100_cs_dump_packet(p, pkt);
 188                         return r;
 189                 }
 190                 idx_value = radeon_get_ib_value(p, idx);
 191                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
 192                 track->arrays[i + 0].robj = reloc->robj;
 193                 track->arrays[i + 0].esize = idx_value >> 8;
 194                 track->arrays[i + 0].esize &= 0x7F;
 195         }
 196         return r;
 197 }