drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96
  97 /*
  98  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  99  * symbol;
 100  */
 101 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
 102 #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
 103 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 104 #define RADEON_IB_POOL_SIZE             16
 105 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
 106 #define RADEONFB_CONN_LIMIT             4
 107 #define RADEON_BIOS_NUM_SCRATCH         8
 108
 109 /*
 110  * Errata workarounds.
 111  */
 112 enum radeon_pll_errata {
 113         CHIP_ERRATA_R300_CG             = 0x00000001,
 114         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 115         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 116 };
 117
 118
 119 struct radeon_device;
 120
 121
 122 /*
 123  * BIOS.
 124  */
 125 #define ATRM_BIOS_PAGE 4096
 126
 127 #if defined(CONFIG_VGA_SWITCHEROO)
 128 bool radeon_atrm_supported(struct pci_dev *pdev);
 129 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 130 #else
 131 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 132 {
 133         return false;
 134 }
 135
 136 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 137         return -EINVAL;
 138 }
 139 #endif
 140 bool radeon_get_bios(struct radeon_device *rdev);
 141
 142
 143 /*
 144  * Dummy page
 145  */
 146 struct radeon_dummy_page {
 147         struct page     *page;
 148         dma_addr_t      addr;
 149 };
 150 int radeon_dummy_page_init(struct radeon_device *rdev);
 151 void radeon_dummy_page_fini(struct radeon_device *rdev);
 152
 153
 154 /*
 155  * Clocks
 156  */
 157 struct radeon_clock {
 158         struct radeon_pll p1pll;
 159         struct radeon_pll p2pll;
 160         struct radeon_pll dcpll;
 161         struct radeon_pll spll;
 162         struct radeon_pll mpll;
 163         /* 10 Khz units */
 164         uint32_t default_mclk;
 165         uint32_t default_sclk;
 166         uint32_t default_dispclk;
 167         uint32_t dp_extclk;
 168         uint32_t max_pixel_clock;
 169 };
 170
 171 /*
 172  * Power management
 173  */
 174 int radeon_pm_init(struct radeon_device *rdev);
 175 void radeon_pm_fini(struct radeon_device *rdev);
 176 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 177 void radeon_pm_suspend(struct radeon_device *rdev);
 178 void radeon_pm_resume(struct radeon_device *rdev);
 179 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 180 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 181 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 182 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
 183 void rs690_pm_info(struct radeon_device *rdev);
 184 extern int rv6xx_get_temp(struct radeon_device *rdev);
 185 extern int rv770_get_temp(struct radeon_device *rdev);
 186 extern int evergreen_get_temp(struct radeon_device *rdev);
 187 extern int sumo_get_temp(struct radeon_device *rdev);
 188
 189 /*
 190  * Fences.
 191  */
 192 struct radeon_fence_driver {
 193         uint32_t                        scratch_reg;
 194         atomic_t                        seq;
 195         uint32_t                        last_seq;
 196         unsigned long                   last_jiffies;
 197         unsigned long                   last_timeout;
 198         wait_queue_head_t               queue;
 199         rwlock_t                        lock;
 200         struct list_head                created;
 201         struct list_head                emited;
 202         struct list_head                signaled;
 203         bool                            initialized;
 204 };
 205
 206 struct radeon_fence {
 207         struct radeon_device            *rdev;
 208         struct kref                     kref;
 209         struct list_head                list;
 210         /* protected by radeon_fence.lock */
 211         uint32_t                        seq;
 212         bool                            emited;
 213         bool                            signaled;
 214 };
 215
 216 int radeon_fence_driver_init(struct radeon_device *rdev);
 217 void radeon_fence_driver_fini(struct radeon_device *rdev);
 218 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 219 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 220 void radeon_fence_process(struct radeon_device *rdev);
 221 bool radeon_fence_signaled(struct radeon_fence *fence);
 222 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 223 int radeon_fence_wait_next(struct radeon_device *rdev);
 224 int radeon_fence_wait_last(struct radeon_device *rdev);
 225 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 226 void radeon_fence_unref(struct radeon_fence **fence);
 227
 228 /*
 229  * Tiling registers
 230  */
 231 struct radeon_surface_reg {
 232         struct radeon_bo *bo;
 233 };
 234
 235 #define RADEON_GEM_MAX_SURFACES 8
 236
 237 /*
 238  * TTM.
 239  */
 240 struct radeon_mman {
 241         struct ttm_bo_global_ref        bo_global_ref;
 242         struct drm_global_reference     mem_global_ref;
 243         struct ttm_bo_device            bdev;
 244         bool                            mem_global_referenced;
 245         bool                            initialized;
 246 };
 247
 248 struct radeon_bo {
 249         /* Protected by gem.mutex */
 250         struct list_head                list;
 251         /* Protected by tbo.reserved */
 252         u32                             placements[3];
 253         struct ttm_placement            placement;
 254         struct ttm_buffer_object        tbo;
 255         struct ttm_bo_kmap_obj          kmap;
 256         unsigned                        pin_count;
 257         void                            *kptr;
 258         u32                             tiling_flags;
 259         u32                             pitch;
 260         int                             surface_reg;
 261         /* Constant after initialization */
 262         struct radeon_device            *rdev;
 263         struct drm_gem_object           gem_base;
 264 };
 265 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 266
 267 struct radeon_bo_list {
 268         struct ttm_validate_buffer tv;
 269         struct radeon_bo        *bo;
 270         uint64_t                gpu_offset;
 271         unsigned                rdomain;
 272         unsigned                wdomain;
 273         u32                     tiling_flags;
 274 };
 275
 276 /*
 277  * GEM objects.
 278  */
 279 struct radeon_gem {
 280         struct mutex            mutex;
 281         struct list_head        objects;
 282 };
 283
 284 int radeon_gem_init(struct radeon_device *rdev);
 285 void radeon_gem_fini(struct radeon_device *rdev);
 286 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 287                                 int alignment, int initial_domain,
 288                                 bool discardable, bool kernel,
 289                                 struct drm_gem_object **obj);
 290 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 291                           uint64_t *gpu_addr);
 292 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 293
 294 int radeon_mode_dumb_create(struct drm_file *file_priv,
 295                             struct drm_device *dev,
 296                             struct drm_mode_create_dumb *args);
 297 int radeon_mode_dumb_mmap(struct drm_file *filp,
 298                           struct drm_device *dev,
 299                           uint32_t handle, uint64_t *offset_p);
 300 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 301                              struct drm_device *dev,
 302                              uint32_t handle);
 303
 304 /*
 305  * GART structures, functions & helpers
 306  */
 307 struct radeon_mc;
 308
 309 struct radeon_gart_table_ram {
 310         volatile uint32_t               *ptr;
 311 };
 312
 313 struct radeon_gart_table_vram {
 314         struct radeon_bo                *robj;
 315         volatile uint32_t               *ptr;
 316 };
 317
 318 union radeon_gart_table {
 319         struct radeon_gart_table_ram    ram;
 320         struct radeon_gart_table_vram   vram;
 321 };
 322
 323 #define RADEON_GPU_PAGE_SIZE 4096
 324 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 325 #define RADEON_GPU_PAGE_SHIFT 12
 326
 327 struct radeon_gart {
 328         dma_addr_t                      table_addr;
 329         unsigned                        num_gpu_pages;
 330         unsigned                        num_cpu_pages;
 331         unsigned                        table_size;
 332         union radeon_gart_table         table;
 333         struct page                     **pages;
 334         dma_addr_t                      *pages_addr;
 335         bool                            *ttm_alloced;
 336         bool                            ready;
 337 };
 338
 339 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 340 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 341 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 342 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 343 int radeon_gart_init(struct radeon_device *rdev);
 344 void radeon_gart_fini(struct radeon_device *rdev);
 345 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 346                         int pages);
 347 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 348                      int pages, struct page **pagelist,
 349                      dma_addr_t *dma_addr);
 350
 351
 352 /*
 353  * GPU MC structures, functions & helpers
 354  */
 355 struct radeon_mc {
 356         resource_size_t         aper_size;
 357         resource_size_t         aper_base;
 358         resource_size_t         agp_base;
 359         /* for some chips with <= 32MB we need to lie
 360          * about vram size near mc fb location */
 361         u64                     mc_vram_size;
 362         u64                     visible_vram_size;
 363         u64                     gtt_size;
 364         u64                     gtt_start;
 365         u64                     gtt_end;
 366         u64                     vram_start;
 367         u64                     vram_end;
 368         unsigned                vram_width;
 369         u64                     real_vram_size;
 370         int                     vram_mtrr;
 371         bool                    vram_is_ddr;
 372         bool                    igp_sideport_enabled;
 373         u64                     gtt_base_align;
 374 };
 375
 376 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 377 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 378
 379 /*
 380  * GPU scratch registers structures, functions & helpers
 381  */
 382 struct radeon_scratch {
 383         unsigned                num_reg;
 384         uint32_t                reg_base;
 385         bool                    free[32];
 386         uint32_t                reg[32];
 387 };
 388
 389 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 390 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 391
 392
 393 /*
 394  * IRQS.
 395  */
 396
 397 struct radeon_unpin_work {
 398         struct work_struct work;
 399         struct radeon_device *rdev;
 400         int crtc_id;
 401         struct radeon_fence *fence;
 402         struct drm_pending_vblank_event *event;
 403         struct radeon_bo *old_rbo;
 404         u64 new_crtc_base;
 405 };
 406
 407 struct r500_irq_stat_regs {
 408         u32 disp_int;
 409 };
 410
 411 struct r600_irq_stat_regs {
 412         u32 disp_int;
 413         u32 disp_int_cont;
 414         u32 disp_int_cont2;
 415         u32 d1grph_int;
 416         u32 d2grph_int;
 417 };
 418
 419 struct evergreen_irq_stat_regs {
 420         u32 disp_int;
 421         u32 disp_int_cont;
 422         u32 disp_int_cont2;
 423         u32 disp_int_cont3;
 424         u32 disp_int_cont4;
 425         u32 disp_int_cont5;
 426         u32 d1grph_int;
 427         u32 d2grph_int;
 428         u32 d3grph_int;
 429         u32 d4grph_int;
 430         u32 d5grph_int;
 431         u32 d6grph_int;
 432 };
 433
 434 union radeon_irq_stat_regs {
 435         struct r500_irq_stat_regs r500;
 436         struct r600_irq_stat_regs r600;
 437         struct evergreen_irq_stat_regs evergreen;
 438 };
 439
 440 struct radeon_irq {
 441         bool            installed;
 442         bool            sw_int;
 443         /* FIXME: use a define max crtc rather than hardcode it */
 444         bool            crtc_vblank_int[6];
 445         bool            pflip[6];
 446         wait_queue_head_t       vblank_queue;
 447         /* FIXME: use defines for max hpd/dacs */
 448         bool            hpd[6];
 449         bool            gui_idle;
 450         bool            gui_idle_acked;
 451         wait_queue_head_t       idle_queue;
 452         /* FIXME: use defines for max HDMI blocks */
 453         bool            hdmi[2];
 454         spinlock_t sw_lock;
 455         int sw_refcount;
 456         union radeon_irq_stat_regs stat_regs;
 457         spinlock_t pflip_lock[6];
 458         int pflip_refcount[6];
 459 };
 460
 461 int radeon_irq_kms_init(struct radeon_device *rdev);
 462 void radeon_irq_kms_fini(struct radeon_device *rdev);
 463 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 464 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 465 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 466 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 467
 468 /*
 469  * CP & ring.
 470  */
 471 struct radeon_ib {
 472         struct list_head        list;
 473         unsigned                idx;
 474         uint64_t                gpu_addr;
 475         struct radeon_fence     *fence;
 476         uint32_t                *ptr;
 477         uint32_t                length_dw;
 478         bool                    free;
 479 };
 480
 481 /*
 482  * locking -
 483  * mutex protects scheduled_ibs, ready, alloc_bm
 484  */
 485 struct radeon_ib_pool {
 486         struct mutex            mutex;
 487         struct radeon_bo        *robj;
 488         struct list_head        bogus_ib;
 489         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 490         bool                    ready;
 491         unsigned                head_id;
 492 };
 493
 494 struct radeon_cp {
 495         struct radeon_bo        *ring_obj;
 496         volatile uint32_t       *ring;
 497         unsigned                rptr;
 498         unsigned                wptr;
 499         unsigned                wptr_old;
 500         unsigned                ring_size;
 501         unsigned                ring_free_dw;
 502         int                     count_dw;
 503         uint64_t                gpu_addr;
 504         uint32_t                align_mask;
 505         uint32_t                ptr_mask;
 506         struct mutex            mutex;
 507         bool                    ready;
 508 };
 509
 510 /*
 511  * R6xx+ IH ring
 512  */
 513 struct r600_ih {
 514         struct radeon_bo        *ring_obj;
 515         volatile uint32_t       *ring;
 516         unsigned                rptr;
 517         unsigned                wptr;
 518         unsigned                wptr_old;
 519         unsigned                ring_size;
 520         uint64_t                gpu_addr;
 521         uint32_t                ptr_mask;
 522         spinlock_t              lock;
 523         bool                    enabled;
 524 };
 525
 526 struct r600_blit {
 527         struct mutex            mutex;
 528         struct radeon_bo        *shader_obj;
 529         u64 shader_gpu_addr;
 530         u32 vs_offset, ps_offset;
 531         u32 state_offset;
 532         u32 state_len;
 533         u32 vb_used, vb_total;
 534         struct radeon_ib *vb_ib;
 535 };
 536
 537 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 538 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 539 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 540 int radeon_ib_pool_init(struct radeon_device *rdev);
 541 void radeon_ib_pool_fini(struct radeon_device *rdev);
 542 int radeon_ib_test(struct radeon_device *rdev);
 543 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
 544 /* Ring access between begin & end cannot sleep */
 545 void radeon_ring_free_size(struct radeon_device *rdev);
 546 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
 547 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 548 void radeon_ring_commit(struct radeon_device *rdev);
 549 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 550 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 551 int radeon_ring_test(struct radeon_device *rdev);
 552 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 553 void radeon_ring_fini(struct radeon_device *rdev);
 554
 555
 556 /*
 557  * CS.
 558  */
 559 struct radeon_cs_reloc {
 560         struct drm_gem_object           *gobj;
 561         struct radeon_bo                *robj;
 562         struct radeon_bo_list           lobj;
 563         uint32_t                        handle;
 564         uint32_t                        flags;
 565 };
 566
 567 struct radeon_cs_chunk {
 568         uint32_t                chunk_id;
 569         uint32_t                length_dw;
 570         int kpage_idx[2];
 571         uint32_t                *kpage[2];
 572         uint32_t                *kdata;
 573         void __user *user_ptr;
 574         int last_copied_page;
 575         int last_page_index;
 576 };
 577
 578 struct radeon_cs_parser {
 579         struct device           *dev;
 580         struct radeon_device    *rdev;
 581         struct drm_file         *filp;
 582         /* chunks */
 583         unsigned                nchunks;
 584         struct radeon_cs_chunk  *chunks;
 585         uint64_t                *chunks_array;
 586         /* IB */
 587         unsigned                idx;
 588         /* relocations */
 589         unsigned                nrelocs;
 590         struct radeon_cs_reloc  *relocs;
 591         struct radeon_cs_reloc  **relocs_ptr;
 592         struct list_head        validated;
 593         /* indices of various chunks */
 594         int                     chunk_ib_idx;
 595         int                     chunk_relocs_idx;
 596         struct radeon_ib        *ib;
 597         void                    *track;
 598         unsigned                family;
 599         int parser_error;
 600 };
 601
 602 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 603 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 604
 605
 606 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 607 {
 608         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 609         u32 pg_idx, pg_offset;
 610         u32 idx_value = 0;
 611         int new_page;
 612
 613         pg_idx = (idx * 4) / PAGE_SIZE;
 614         pg_offset = (idx * 4) % PAGE_SIZE;
 615
 616         if (ibc->kpage_idx[0] == pg_idx)
 617                 return ibc->kpage[0][pg_offset/4];
 618         if (ibc->kpage_idx[1] == pg_idx)
 619                 return ibc->kpage[1][pg_offset/4];
 620
 621         new_page = radeon_cs_update_pages(p, pg_idx);
 622         if (new_page < 0) {
 623                 p->parser_error = new_page;
 624                 return 0;
 625         }
 626
 627         idx_value = ibc->kpage[new_page][pg_offset/4];
 628         return idx_value;
 629 }
 630
 631 struct radeon_cs_packet {
 632         unsigned        idx;
 633         unsigned        type;
 634         unsigned        reg;
 635         unsigned        opcode;
 636         int             count;
 637         unsigned        one_reg_wr;
 638 };
 639
 640 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 641                                       struct radeon_cs_packet *pkt,
 642                                       unsigned idx, unsigned reg);
 643 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 644                                       struct radeon_cs_packet *pkt);
 645
 646
 647 /*
 648  * AGP
 649  */
 650 int radeon_agp_init(struct radeon_device *rdev);
 651 void radeon_agp_resume(struct radeon_device *rdev);
 652 void radeon_agp_suspend(struct radeon_device *rdev);
 653 void radeon_agp_fini(struct radeon_device *rdev);
 654
 655
 656 /*
 657  * Writeback
 658  */
 659 struct radeon_wb {
 660         struct radeon_bo        *wb_obj;
 661         volatile uint32_t       *wb;
 662         uint64_t                gpu_addr;
 663         bool                    enabled;
 664         bool                    use_event;
 665 };
 666
 667 #define RADEON_WB_SCRATCH_OFFSET 0
 668 #define RADEON_WB_CP_RPTR_OFFSET 1024
 669 #define RADEON_WB_CP1_RPTR_OFFSET 1280
 670 #define RADEON_WB_CP2_RPTR_OFFSET 1536
 671 #define R600_WB_IH_WPTR_OFFSET   2048
 672 #define R600_WB_EVENT_OFFSET     3072
 673
 674 /**
 675  * struct radeon_pm - power management datas
 676  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 677  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 678  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 679  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 680  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 681  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 682  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 683  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 684  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 685  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
 686  * @needed_bandwidth:   current bandwidth needs
 687  *
 688  * It keeps track of various data needed to take powermanagement decision.
 689  * Bandwidth need is used to determine minimun clock of the GPU and memory.
 690  * Equation between gpu/memory clock and available bandwidth is hw dependent
 691  * (type of memory, bus size, efficiency, ...)
 692  */
 693
 694 enum radeon_pm_method {
 695         PM_METHOD_PROFILE,
 696         PM_METHOD_DYNPM,
 697 };
 698
 699 enum radeon_dynpm_state {
 700         DYNPM_STATE_DISABLED,
 701         DYNPM_STATE_MINIMUM,
 702         DYNPM_STATE_PAUSED,
 703         DYNPM_STATE_ACTIVE,
 704         DYNPM_STATE_SUSPENDED,
 705 };
 706 enum radeon_dynpm_action {
 707         DYNPM_ACTION_NONE,
 708         DYNPM_ACTION_MINIMUM,
 709         DYNPM_ACTION_DOWNCLOCK,
 710         DYNPM_ACTION_UPCLOCK,
 711         DYNPM_ACTION_DEFAULT
 712 };
 713
 714 enum radeon_voltage_type {
 715         VOLTAGE_NONE = 0,
 716         VOLTAGE_GPIO,
 717         VOLTAGE_VDDC,
 718         VOLTAGE_SW
 719 };
 720
 721 enum radeon_pm_state_type {
 722         POWER_STATE_TYPE_DEFAULT,
 723         POWER_STATE_TYPE_POWERSAVE,
 724         POWER_STATE_TYPE_BATTERY,
 725         POWER_STATE_TYPE_BALANCED,
 726         POWER_STATE_TYPE_PERFORMANCE,
 727 };
 728
 729 enum radeon_pm_profile_type {
 730         PM_PROFILE_DEFAULT,
 731         PM_PROFILE_AUTO,
 732         PM_PROFILE_LOW,
 733         PM_PROFILE_MID,
 734         PM_PROFILE_HIGH,
 735 };
 736
 737 #define PM_PROFILE_DEFAULT_IDX 0
 738 #define PM_PROFILE_LOW_SH_IDX  1
 739 #define PM_PROFILE_MID_SH_IDX  2
 740 #define PM_PROFILE_HIGH_SH_IDX 3
 741 #define PM_PROFILE_LOW_MH_IDX  4
 742 #define PM_PROFILE_MID_MH_IDX  5
 743 #define PM_PROFILE_HIGH_MH_IDX 6
 744 #define PM_PROFILE_MAX         7
 745
 746 struct radeon_pm_profile {
 747         int dpms_off_ps_idx;
 748         int dpms_on_ps_idx;
 749         int dpms_off_cm_idx;
 750         int dpms_on_cm_idx;
 751 };
 752
 753 enum radeon_int_thermal_type {
 754         THERMAL_TYPE_NONE,
 755         THERMAL_TYPE_RV6XX,
 756         THERMAL_TYPE_RV770,
 757         THERMAL_TYPE_EVERGREEN,
 758         THERMAL_TYPE_SUMO,
 759         THERMAL_TYPE_NI,
 760 };
 761
 762 struct radeon_voltage {
 763         enum radeon_voltage_type type;
 764         /* gpio voltage */
 765         struct radeon_gpio_rec gpio;
 766         u32 delay; /* delay in usec from voltage drop to sclk change */
 767         bool active_high; /* voltage drop is active when bit is high */
 768         /* VDDC voltage */
 769         u8 vddc_id; /* index into vddc voltage table */
 770         u8 vddci_id; /* index into vddci voltage table */
 771         bool vddci_enabled;
 772         /* r6xx+ sw */
 773         u16 voltage;
 774         /* evergreen+ vddci */
 775         u16 vddci;
 776 };
 777
 778 /* clock mode flags */
 779 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
 780
 781 struct radeon_pm_clock_info {
 782         /* memory clock */
 783         u32 mclk;
 784         /* engine clock */
 785         u32 sclk;
 786         /* voltage info */
 787         struct radeon_voltage voltage;
 788         /* standardized clock flags */
 789         u32 flags;
 790 };
 791
 792 /* state flags */
 793 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
 794
 795 struct radeon_power_state {
 796         enum radeon_pm_state_type type;
 797         /* XXX: use a define for num clock modes */
 798         struct radeon_pm_clock_info clock_info[8];
 799         /* number of valid clock modes in this power state */
 800         int num_clock_modes;
 801         struct radeon_pm_clock_info *default_clock_mode;
 802         /* standardized state flags */
 803         u32 flags;
 804         u32 misc; /* vbios specific flags */
 805         u32 misc2; /* vbios specific flags */
 806         int pcie_lanes; /* pcie lanes */
 807 };
 808
 809 /*
 810  * Some modes are overclocked by very low value, accept them
 811  */
 812 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
 813
 814 struct radeon_pm {
 815         struct mutex            mutex;
 816         u32                     active_crtcs;
 817         int                     active_crtc_count;
 818         int                     req_vblank;
 819         bool                    vblank_sync;
 820         bool                    gui_idle;
 821         fixed20_12              max_bandwidth;
 822         fixed20_12              igp_sideport_mclk;
 823         fixed20_12              igp_system_mclk;
 824         fixed20_12              igp_ht_link_clk;
 825         fixed20_12              igp_ht_link_width;
 826         fixed20_12              k8_bandwidth;
 827         fixed20_12              sideport_bandwidth;
 828         fixed20_12              ht_bandwidth;
 829         fixed20_12              core_bandwidth;
 830         fixed20_12              sclk;
 831         fixed20_12              mclk;
 832         fixed20_12              needed_bandwidth;
 833         struct radeon_power_state *power_state;
 834         /* number of valid power states */
 835         int                     num_power_states;
 836         int                     current_power_state_index;
 837         int                     current_clock_mode_index;
 838         int                     requested_power_state_index;
 839         int                     requested_clock_mode_index;
 840         int                     default_power_state_index;
 841         u32                     current_sclk;
 842         u32                     current_mclk;
 843         u16                     current_vddc;
 844         u16                     current_vddci;
 845         u32                     default_sclk;
 846         u32                     default_mclk;
 847         u16                     default_vddc;
 848         u16                     default_vddci;
 849         struct radeon_i2c_chan *i2c_bus;
 850         /* selected pm method */
 851         enum radeon_pm_method     pm_method;
 852         /* dynpm power management */
 853         struct delayed_work     dynpm_idle_work;
 854         enum radeon_dynpm_state dynpm_state;
 855         enum radeon_dynpm_action        dynpm_planned_action;
 856         unsigned long           dynpm_action_timeout;
 857         bool                    dynpm_can_upclock;
 858         bool                    dynpm_can_downclock;
 859         /* profile-based power management */
 860         enum radeon_pm_profile_type profile;
 861         int                     profile_index;
 862         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
 863         /* internal thermal controller on rv6xx+ */
 864         enum radeon_int_thermal_type int_thermal_type;
 865         struct device           *int_hwmon_dev;
 866 };
 867
 868
 869 /*
 870  * Benchmarking
 871  */
 872 void radeon_benchmark(struct radeon_device *rdev);
 873
 874
 875 /*
 876  * Testing
 877  */
 878 void radeon_test_moves(struct radeon_device *rdev);
 879
 880
 881 /*
 882  * Debugfs
 883  */
 884 int radeon_debugfs_add_files(struct radeon_device *rdev,
 885                              struct drm_info_list *files,
 886                              unsigned nfiles);
 887 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 888
 889
 890 /*
 891  * ASIC specific functions.
 892  */
 893 struct radeon_asic {
 894         int (*init)(struct radeon_device *rdev);
 895         void (*fini)(struct radeon_device *rdev);
 896         int (*resume)(struct radeon_device *rdev);
 897         int (*suspend)(struct radeon_device *rdev);
 898         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 899         bool (*gpu_is_lockup)(struct radeon_device *rdev);
 900         int (*asic_reset)(struct radeon_device *rdev);
 901         void (*gart_tlb_flush)(struct radeon_device *rdev);
 902         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 903         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 904         void (*cp_fini)(struct radeon_device *rdev);
 905         void (*cp_disable)(struct radeon_device *rdev);
 906         void (*cp_commit)(struct radeon_device *rdev);
 907         void (*ring_start)(struct radeon_device *rdev);
 908         int (*ring_test)(struct radeon_device *rdev);
 909         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 910         int (*irq_set)(struct radeon_device *rdev);
 911         int (*irq_process)(struct radeon_device *rdev);
 912         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 913         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 914         int (*cs_parse)(struct radeon_cs_parser *p);
 915         int (*copy_blit)(struct radeon_device *rdev,
 916                          uint64_t src_offset,
 917                          uint64_t dst_offset,
 918                          unsigned num_gpu_pages,
 919                          struct radeon_fence *fence);
 920         int (*copy_dma)(struct radeon_device *rdev,
 921                         uint64_t src_offset,
 922                         uint64_t dst_offset,
 923                         unsigned num_gpu_pages,
 924                         struct radeon_fence *fence);
 925         int (*copy)(struct radeon_device *rdev,
 926                     uint64_t src_offset,
 927                     uint64_t dst_offset,
 928                     unsigned num_gpu_pages,
 929                     struct radeon_fence *fence);
 930         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
 931         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 932         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
 933         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 934         int (*get_pcie_lanes)(struct radeon_device *rdev);
 935         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 936         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 937         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 938                                uint32_t tiling_flags, uint32_t pitch,
 939                                uint32_t offset, uint32_t obj_size);
 940         void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 941         void (*bandwidth_update)(struct radeon_device *rdev);
 942         void (*hpd_init)(struct radeon_device *rdev);
 943         void (*hpd_fini)(struct radeon_device *rdev);
 944         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 945         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 946         /* ioctl hw specific callback. Some hw might want to perform special
 947          * operation on specific ioctl. For instance on wait idle some hw
 948          * might want to perform and HDP flush through MMIO as it seems that
 949          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
 950          * through ring.
 951          */
 952         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
 953         bool (*gui_idle)(struct radeon_device *rdev);
 954         /* power management */
 955         void (*pm_misc)(struct radeon_device *rdev);
 956         void (*pm_prepare)(struct radeon_device *rdev);
 957         void (*pm_finish)(struct radeon_device *rdev);
 958         void (*pm_init_profile)(struct radeon_device *rdev);
 959         void (*pm_get_dynpm_state)(struct radeon_device *rdev);
 960         /* pageflipping */
 961         void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
 962         u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
 963         void (*post_page_flip)(struct radeon_device *rdev, int crtc);
 964 };
 965
 966 /*
 967  * Asic structures
 968  */
 969 struct r100_gpu_lockup {
 970         unsigned long   last_jiffies;
 971         u32             last_cp_rptr;
 972 };
 973
 974 struct r100_asic {
 975         const unsigned          *reg_safe_bm;
 976         unsigned                reg_safe_bm_size;
 977         u32                     hdp_cntl;
 978         struct r100_gpu_lockup  lockup;
 979 };
 980
 981 struct r300_asic {
 982         const unsigned          *reg_safe_bm;
 983         unsigned                reg_safe_bm_size;
 984         u32                     resync_scratch;
 985         u32                     hdp_cntl;
 986         struct r100_gpu_lockup  lockup;
 987 };
 988
 989 struct r600_asic {
 990         unsigned                max_pipes;
 991         unsigned                max_tile_pipes;
 992         unsigned                max_simds;
 993         unsigned                max_backends;
 994         unsigned                max_gprs;
 995         unsigned                max_threads;
 996         unsigned                max_stack_entries;
 997         unsigned                max_hw_contexts;
 998         unsigned                max_gs_threads;
 999         unsigned                sx_max_export_size;
1000         unsigned                sx_max_export_pos_size;
1001         unsigned                sx_max_export_smx_size;
1002         unsigned                sq_num_cf_insts;
1003         unsigned                tiling_nbanks;
1004         unsigned                tiling_npipes;
1005         unsigned                tiling_group_size;
1006         unsigned                tile_config;
1007         unsigned                backend_map;
1008         struct r100_gpu_lockup  lockup;
1009 };
1010
1011 struct rv770_asic {
1012         unsigned                max_pipes;
1013         unsigned                max_tile_pipes;
1014         unsigned                max_simds;
1015         unsigned                max_backends;
1016         unsigned                max_gprs;
1017         unsigned                max_threads;
1018         unsigned                max_stack_entries;
1019         unsigned                max_hw_contexts;
1020         unsigned                max_gs_threads;
1021         unsigned                sx_max_export_size;
1022         unsigned                sx_max_export_pos_size;
1023         unsigned                sx_max_export_smx_size;
1024         unsigned                sq_num_cf_insts;
1025         unsigned                sx_num_of_sets;
1026         unsigned                sc_prim_fifo_size;
1027         unsigned                sc_hiz_tile_fifo_size;
1028         unsigned                sc_earlyz_tile_fifo_fize;
1029         unsigned                tiling_nbanks;
1030         unsigned                tiling_npipes;
1031         unsigned                tiling_group_size;
1032         unsigned                tile_config;
1033         unsigned                backend_map;
1034         struct r100_gpu_lockup  lockup;
1035 };
1036
1037 struct evergreen_asic {
1038         unsigned num_ses;
1039         unsigned max_pipes;
1040         unsigned max_tile_pipes;
1041         unsigned max_simds;
1042         unsigned max_backends;
1043         unsigned max_gprs;
1044         unsigned max_threads;
1045         unsigned max_stack_entries;
1046         unsigned max_hw_contexts;
1047         unsigned max_gs_threads;
1048         unsigned sx_max_export_size;
1049         unsigned sx_max_export_pos_size;
1050         unsigned sx_max_export_smx_size;
1051         unsigned sq_num_cf_insts;
1052         unsigned sx_num_of_sets;
1053         unsigned sc_prim_fifo_size;
1054         unsigned sc_hiz_tile_fifo_size;
1055         unsigned sc_earlyz_tile_fifo_size;
1056         unsigned tiling_nbanks;
1057         unsigned tiling_npipes;
1058         unsigned tiling_group_size;
1059         unsigned tile_config;
1060         unsigned backend_map;
1061         struct r100_gpu_lockup  lockup;
1062 };
1063
1064 struct cayman_asic {
1065         unsigned max_shader_engines;
1066         unsigned max_pipes_per_simd;
1067         unsigned max_tile_pipes;
1068         unsigned max_simds_per_se;
1069         unsigned max_backends_per_se;
1070         unsigned max_texture_channel_caches;
1071         unsigned max_gprs;
1072         unsigned max_threads;
1073         unsigned max_gs_threads;
1074         unsigned max_stack_entries;
1075         unsigned sx_num_of_sets;
1076         unsigned sx_max_export_size;
1077         unsigned sx_max_export_pos_size;
1078         unsigned sx_max_export_smx_size;
1079         unsigned max_hw_contexts;
1080         unsigned sq_num_cf_insts;
1081         unsigned sc_prim_fifo_size;
1082         unsigned sc_hiz_tile_fifo_size;
1083         unsigned sc_earlyz_tile_fifo_size;
1084
1085         unsigned num_shader_engines;
1086         unsigned num_shader_pipes_per_simd;
1087         unsigned num_tile_pipes;
1088         unsigned num_simds_per_se;
1089         unsigned num_backends_per_se;
1090         unsigned backend_disable_mask_per_asic;
1091         unsigned backend_map;
1092         unsigned num_texture_channel_caches;
1093         unsigned mem_max_burst_length_bytes;
1094         unsigned mem_row_size_in_kb;
1095         unsigned shader_engine_tile_size;
1096         unsigned num_gpus;
1097         unsigned multi_gpu_tile_size;
1098
1099         unsigned tile_config;
1100         struct r100_gpu_lockup  lockup;
1101 };
1102
1103 union radeon_asic_config {
1104         struct r300_asic        r300;
1105         struct r100_asic        r100;
1106         struct r600_asic        r600;
1107         struct rv770_asic       rv770;
1108         struct evergreen_asic   evergreen;
1109         struct cayman_asic      cayman;
1110 };
1111
1112 /*
1113  * asic initizalization from radeon_asic.c
1114  */
1115 void radeon_agp_disable(struct radeon_device *rdev);
1116 int radeon_asic_init(struct radeon_device *rdev);
1117
1118
1119 /*
1120  * IOCTL.
1121  */
1122 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1123                           struct drm_file *filp);
1124 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1125                             struct drm_file *filp);
1126 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1127                          struct drm_file *file_priv);
1128 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1129                            struct drm_file *file_priv);
1130 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1131                             struct drm_file *file_priv);
1132 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1133                            struct drm_file *file_priv);
1134 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1135                                 struct drm_file *filp);
1136 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1137                           struct drm_file *filp);
1138 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1139                           struct drm_file *filp);
1140 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1141                               struct drm_file *filp);
1142 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1143 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1144                                 struct drm_file *filp);
1145 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1146                                 struct drm_file *filp);
1147
1148 /* VRAM scratch page for HDP bug */
1149 struct r700_vram_scratch {
1150         struct radeon_bo                *robj;
1151         volatile uint32_t               *ptr;
1152 };
1153
1154 /*
1155  * Core structure, functions and helpers.
1156  */
1157 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1158 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1159
1160 struct radeon_device {
1161         struct device                   *dev;
1162         struct drm_device               *ddev;
1163         struct pci_dev                  *pdev;
1164         /* ASIC */
1165         union radeon_asic_config        config;
1166         enum radeon_family              family;
1167         unsigned long                   flags;
1168         int                             usec_timeout;
1169         enum radeon_pll_errata          pll_errata;
1170         int                             num_gb_pipes;
1171         int                             num_z_pipes;
1172         int                             disp_priority;
1173         /* BIOS */
1174         uint8_t                         *bios;
1175         bool                            is_atom_bios;
1176         uint16_t                        bios_header_start;
1177         struct radeon_bo                *stollen_vga_memory;
1178         /* Register mmio */
1179         resource_size_t                 rmmio_base;
1180         resource_size_t                 rmmio_size;
1181         void __iomem                    *rmmio;
1182         radeon_rreg_t                   mc_rreg;
1183         radeon_wreg_t                   mc_wreg;
1184         radeon_rreg_t                   pll_rreg;
1185         radeon_wreg_t                   pll_wreg;
1186         uint32_t                        pcie_reg_mask;
1187         radeon_rreg_t                   pciep_rreg;
1188         radeon_wreg_t                   pciep_wreg;
1189         /* io port */
1190         void __iomem                    *rio_mem;
1191         resource_size_t                 rio_mem_size;
1192         struct radeon_clock             clock;
1193         struct radeon_mc                mc;
1194         struct radeon_gart              gart;
1195         struct radeon_mode_info         mode_info;
1196         struct radeon_scratch           scratch;
1197         struct radeon_mman              mman;
1198         struct radeon_fence_driver      fence_drv;
1199         struct radeon_cp                cp;
1200         /* cayman compute rings */
1201         struct radeon_cp                cp1;
1202         struct radeon_cp                cp2;
1203         struct radeon_ib_pool           ib_pool;
1204         struct radeon_irq               irq;
1205         struct radeon_asic              *asic;
1206         struct radeon_gem               gem;
1207         struct radeon_pm                pm;
1208         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1209         struct mutex                    cs_mutex;
1210         struct radeon_wb                wb;
1211         struct radeon_dummy_page        dummy_page;
1212         bool                            gpu_lockup;
1213         bool                            shutdown;
1214         bool                            suspend;
1215         bool                            need_dma32;
1216         bool                            accel_working;
1217         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1218         const struct firmware *me_fw;   /* all family ME firmware */
1219         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1220         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1221         const struct firmware *mc_fw;   /* NI MC firmware */
1222         struct r600_blit r600_blit;
1223         struct r700_vram_scratch vram_scratch;
1224         int msi_enabled; /* msi enabled */
1225         struct r600_ih ih; /* r6/700 interrupt ring */
1226         struct work_struct hotplug_work;
1227         int num_crtc; /* number of crtcs */
1228         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1229         struct mutex vram_mutex;
1230
1231         /* audio stuff */
1232         bool                    audio_enabled;
1233         struct timer_list       audio_timer;
1234         int                     audio_channels;
1235         int                     audio_rate;
1236         int                     audio_bits_per_sample;
1237         uint8_t                 audio_status_bits;
1238         uint8_t                 audio_category_code;
1239
1240         struct notifier_block acpi_nb;
1241         /* only one userspace can use Hyperz features or CMASK at a time */
1242         struct drm_file *hyperz_filp;
1243         struct drm_file *cmask_filp;
1244         /* i2c buses */
1245         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1246 };
1247
1248 int radeon_device_init(struct radeon_device *rdev,
1249                        struct drm_device *ddev,
1250                        struct pci_dev *pdev,
1251                        uint32_t flags);
1252 void radeon_device_fini(struct radeon_device *rdev);
1253 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1254
1255 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1256 {
1257         if (reg < rdev->rmmio_size)
1258                 return readl((rdev->rmmio) + reg);
1259         else {
1260                 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1261                 return readl((rdev->rmmio) + RADEON_MM_DATA);
1262         }
1263 }
1264
1265 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1266 {
1267         if (reg < rdev->rmmio_size)
1268                 writel(v, (rdev->rmmio) + reg);
1269         else {
1270                 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1271                 writel(v, (rdev->rmmio) + RADEON_MM_DATA);
1272         }
1273 }
1274
1275 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1276 {
1277         if (reg < rdev->rio_mem_size)
1278                 return ioread32(rdev->rio_mem + reg);
1279         else {
1280                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1281                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1282         }
1283 }
1284
1285 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1286 {
1287         if (reg < rdev->rio_mem_size)
1288                 iowrite32(v, rdev->rio_mem + reg);
1289         else {
1290                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1291                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1292         }
1293 }
1294
1295 /*
1296  * Cast helper
1297  */
1298 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1299
1300 /*
1301  * Registers read & write functions.
1302  */
1303 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1304 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1305 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1306 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1307 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1308 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1309 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1310 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1311 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1312 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1313 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1314 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1315 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1316 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1317 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1318 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1319 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1320 #define WREG32_P(reg, val, mask)                                \
1321         do {                                                    \
1322                 uint32_t tmp_ = RREG32(reg);                    \
1323                 tmp_ &= (mask);                                 \
1324                 tmp_ |= ((val) & ~(mask));                      \
1325                 WREG32(reg, tmp_);                              \
1326         } while (0)
1327 #define WREG32_PLL_P(reg, val, mask)                            \
1328         do {                                                    \
1329                 uint32_t tmp_ = RREG32_PLL(reg);                \
1330                 tmp_ &= (mask);                                 \
1331                 tmp_ |= ((val) & ~(mask));                      \
1332                 WREG32_PLL(reg, tmp_);                          \
1333         } while (0)
1334 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1335 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1336 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1337
1338 /*
1339  * Indirect registers accessor
1340  */
1341 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1342 {
1343         uint32_t r;
1344
1345         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1346         r = RREG32(RADEON_PCIE_DATA);
1347         return r;
1348 }
1349
1350 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1351 {
1352         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1353         WREG32(RADEON_PCIE_DATA, (v));
1354 }
1355
1356 void r100_pll_errata_after_index(struct radeon_device *rdev);
1357
1358
1359 /*
1360  * ASICs helpers.
1361  */
1362 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1363                             (rdev->pdev->device == 0x5969))
1364 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1365                 (rdev->family == CHIP_RV200) || \
1366                 (rdev->family == CHIP_RS100) || \
1367                 (rdev->family == CHIP_RS200) || \
1368                 (rdev->family == CHIP_RV250) || \
1369                 (rdev->family == CHIP_RV280) || \
1370                 (rdev->family == CHIP_RS300))
1371 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1372                 (rdev->family == CHIP_RV350) ||                 \
1373                 (rdev->family == CHIP_R350)  ||                 \
1374                 (rdev->family == CHIP_RV380) ||                 \
1375                 (rdev->family == CHIP_R420)  ||                 \
1376                 (rdev->family == CHIP_R423)  ||                 \
1377                 (rdev->family == CHIP_RV410) ||                 \
1378                 (rdev->family == CHIP_RS400) ||                 \
1379                 (rdev->family == CHIP_RS480))
1380 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1381                 (rdev->ddev->pdev->device == 0x9443) || \
1382                 (rdev->ddev->pdev->device == 0x944B) || \
1383                 (rdev->ddev->pdev->device == 0x9506) || \
1384                 (rdev->ddev->pdev->device == 0x9509) || \
1385                 (rdev->ddev->pdev->device == 0x950F) || \
1386                 (rdev->ddev->pdev->device == 0x689C) || \
1387                 (rdev->ddev->pdev->device == 0x689D))
1388 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1389 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1390                             (rdev->family == CHIP_RS690)  ||    \
1391                             (rdev->family == CHIP_RS740)  ||    \
1392                             (rdev->family >= CHIP_R600))
1393 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1394 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1395 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1396 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1397                              (rdev->flags & RADEON_IS_IGP))
1398 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1399
1400 /*
1401  * BIOS helpers.
1402  */
1403 #define RBIOS8(i) (rdev->bios[i])
1404 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1405 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1406
1407 int radeon_combios_init(struct radeon_device *rdev);
1408 void radeon_combios_fini(struct radeon_device *rdev);
1409 int radeon_atombios_init(struct radeon_device *rdev);
1410 void radeon_atombios_fini(struct radeon_device *rdev);
1411
1412
1413 /*
1414  * RING helpers.
1415  */
1416 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1417 {
1418 #if DRM_DEBUG_CODE
1419         if (rdev->cp.count_dw <= 0) {
1420                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1421         }
1422 #endif
1423         rdev->cp.ring[rdev->cp.wptr++] = v;
1424         rdev->cp.wptr &= rdev->cp.ptr_mask;
1425         rdev->cp.count_dw--;
1426         rdev->cp.ring_free_dw--;
1427 }
1428
1429
1430 /*
1431  * ASICs macro.
1432  */
1433 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1434 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1435 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1436 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1437 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1438 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1439 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1440 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1441 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1442 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1443 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1444 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1445 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1446 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1447 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1448 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1449 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1450 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1451 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1452 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1453 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1454 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1455 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1456 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1457 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1458 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1459 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1460 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1461 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1462 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1463 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1464 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1465 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1466 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1467 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1468 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1469 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1470 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1471 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1472 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1473 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1474 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1475 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1476 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1477
1478 /* Common functions */
1479 /* AGP */
1480 extern int radeon_gpu_reset(struct radeon_device *rdev);
1481 extern void radeon_agp_disable(struct radeon_device *rdev);
1482 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1483 extern void radeon_gart_restore(struct radeon_device *rdev);
1484 extern int radeon_modeset_init(struct radeon_device *rdev);
1485 extern void radeon_modeset_fini(struct radeon_device *rdev);
1486 extern bool radeon_card_posted(struct radeon_device *rdev);
1487 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1488 extern void radeon_update_display_priority(struct radeon_device *rdev);
1489 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1490 extern void radeon_scratch_init(struct radeon_device *rdev);
1491 extern void radeon_wb_fini(struct radeon_device *rdev);
1492 extern int radeon_wb_init(struct radeon_device *rdev);
1493 extern void radeon_wb_disable(struct radeon_device *rdev);
1494 extern void radeon_surface_init(struct radeon_device *rdev);
1495 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1496 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1497 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1498 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1499 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1500 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1501 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1502 extern int radeon_resume_kms(struct drm_device *dev);
1503 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1504 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1505
1506 /*
1507  * r600 functions used by radeon_encoder.c
1508  */
1509 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1510 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1511 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1512
1513 extern int ni_init_microcode(struct radeon_device *rdev);
1514 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1515
1516 /* radeon_acpi.c */
1517 #if defined(CONFIG_ACPI)
1518 extern int radeon_acpi_init(struct radeon_device *rdev);
1519 #else
1520 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1521 #endif
1522
1523 #include "radeon_object.h"
1524
1525 #endif