2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include "radeon_reg.h"
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
39 /* If you boot an IGP board with a discrete card as the primary,
40 * the IGP rom is not accessible via the rom bar as the IGP rom is
41 * part of the system bios. On boot, the system bios puts a
42 * copy of the igp rom at the start of vram if a discrete card is
45 static bool igp_read_bios_from_vram(struct radeon_device
*rdev
)
47 uint8_t __iomem
*bios
;
48 resource_size_t vram_base
;
49 resource_size_t size
= 256 * 1024; /* ??? */
51 if (!(rdev
->flags
& RADEON_IS_IGP
))
52 if (!radeon_card_posted(rdev
))
56 vram_base
= pci_resource_start(rdev
->pdev
, 0);
57 bios
= ioremap(vram_base
, size
);
62 if (size
== 0 || bios
[0] != 0x55 || bios
[1] != 0xaa) {
66 rdev
->bios
= kmalloc(size
, GFP_KERNEL
);
67 if (rdev
->bios
== NULL
) {
71 memcpy_fromio(rdev
->bios
, bios
, size
);
76 static bool radeon_read_bios(struct radeon_device
*rdev
)
78 uint8_t __iomem
*bios
;
82 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
83 bios
= pci_map_rom(rdev
->pdev
, &size
);
88 if (size
== 0 || bios
[0] != 0x55 || bios
[1] != 0xaa) {
89 pci_unmap_rom(rdev
->pdev
, bios
);
92 rdev
->bios
= kmemdup(bios
, size
, GFP_KERNEL
);
93 if (rdev
->bios
== NULL
) {
94 pci_unmap_rom(rdev
->pdev
, bios
);
97 pci_unmap_rom(rdev
->pdev
, bios
);
101 /* ATRM is used to get the BIOS on the discrete cards in
104 static bool radeon_atrm_get_bios(struct radeon_device
*rdev
)
107 int size
= 256 * 1024;
110 if (!radeon_atrm_supported(rdev
->pdev
))
113 rdev
->bios
= kmalloc(size
, GFP_KERNEL
);
115 DRM_ERROR("Unable to allocate bios\n");
119 for (i
= 0; i
< size
/ ATRM_BIOS_PAGE
; i
++) {
120 ret
= radeon_atrm_get_bios_chunk(rdev
->bios
,
121 (i
* ATRM_BIOS_PAGE
),
127 if (i
== 0 || rdev
->bios
[0] != 0x55 || rdev
->bios
[1] != 0xaa) {
134 static bool ni_read_disabled_bios(struct radeon_device
*rdev
)
139 u32 vga_render_control
;
143 bus_cntl
= RREG32(R600_BUS_CNTL
);
144 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
145 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
146 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
147 rom_cntl
= RREG32(R600_ROM_CNTL
);
150 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
151 /* Disable VGA mode */
152 WREG32(AVIVO_D1VGA_CONTROL
,
153 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
154 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
155 WREG32(AVIVO_D2VGA_CONTROL
,
156 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
157 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
158 WREG32(AVIVO_VGA_RENDER_CONTROL
,
159 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
160 WREG32(R600_ROM_CNTL
, rom_cntl
| R600_SCK_OVERWRITE
);
162 r
= radeon_read_bios(rdev
);
165 WREG32(R600_BUS_CNTL
, bus_cntl
);
166 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
167 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
168 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
169 WREG32(R600_ROM_CNTL
, rom_cntl
);
173 static bool r700_read_disabled_bios(struct radeon_device
*rdev
)
175 uint32_t viph_control
;
177 uint32_t d1vga_control
;
178 uint32_t d2vga_control
;
179 uint32_t vga_render_control
;
181 uint32_t cg_spll_func_cntl
= 0;
182 uint32_t cg_spll_status
;
185 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
186 bus_cntl
= RREG32(R600_BUS_CNTL
);
187 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
188 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
189 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
190 rom_cntl
= RREG32(R600_ROM_CNTL
);
193 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
195 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
196 /* Disable VGA mode */
197 WREG32(AVIVO_D1VGA_CONTROL
,
198 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
199 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
200 WREG32(AVIVO_D2VGA_CONTROL
,
201 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
202 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
203 WREG32(AVIVO_VGA_RENDER_CONTROL
,
204 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
206 if (rdev
->family
== CHIP_RV730
) {
207 cg_spll_func_cntl
= RREG32(R600_CG_SPLL_FUNC_CNTL
);
209 /* enable bypass mode */
210 WREG32(R600_CG_SPLL_FUNC_CNTL
, (cg_spll_func_cntl
|
211 R600_SPLL_BYPASS_EN
));
213 /* wait for SPLL_CHG_STATUS to change to 1 */
215 while (!(cg_spll_status
& R600_SPLL_CHG_STATUS
))
216 cg_spll_status
= RREG32(R600_CG_SPLL_STATUS
);
218 WREG32(R600_ROM_CNTL
, (rom_cntl
& ~R600_SCK_OVERWRITE
));
220 WREG32(R600_ROM_CNTL
, (rom_cntl
| R600_SCK_OVERWRITE
));
222 r
= radeon_read_bios(rdev
);
225 if (rdev
->family
== CHIP_RV730
) {
226 WREG32(R600_CG_SPLL_FUNC_CNTL
, cg_spll_func_cntl
);
228 /* wait for SPLL_CHG_STATUS to change to 1 */
230 while (!(cg_spll_status
& R600_SPLL_CHG_STATUS
))
231 cg_spll_status
= RREG32(R600_CG_SPLL_STATUS
);
233 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
234 WREG32(R600_BUS_CNTL
, bus_cntl
);
235 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
236 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
237 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
238 WREG32(R600_ROM_CNTL
, rom_cntl
);
242 static bool r600_read_disabled_bios(struct radeon_device
*rdev
)
244 uint32_t viph_control
;
246 uint32_t d1vga_control
;
247 uint32_t d2vga_control
;
248 uint32_t vga_render_control
;
250 uint32_t general_pwrmgt
;
251 uint32_t low_vid_lower_gpio_cntl
;
252 uint32_t medium_vid_lower_gpio_cntl
;
253 uint32_t high_vid_lower_gpio_cntl
;
254 uint32_t ctxsw_vid_lower_gpio_cntl
;
255 uint32_t lower_gpio_enable
;
258 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
259 bus_cntl
= RREG32(R600_BUS_CNTL
);
260 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
261 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
262 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
263 rom_cntl
= RREG32(R600_ROM_CNTL
);
264 general_pwrmgt
= RREG32(R600_GENERAL_PWRMGT
);
265 low_vid_lower_gpio_cntl
= RREG32(R600_LOW_VID_LOWER_GPIO_CNTL
);
266 medium_vid_lower_gpio_cntl
= RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
);
267 high_vid_lower_gpio_cntl
= RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
);
268 ctxsw_vid_lower_gpio_cntl
= RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
);
269 lower_gpio_enable
= RREG32(R600_LOWER_GPIO_ENABLE
);
272 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
274 WREG32(R600_BUS_CNTL
, (bus_cntl
& ~R600_BIOS_ROM_DIS
));
275 /* Disable VGA mode */
276 WREG32(AVIVO_D1VGA_CONTROL
,
277 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
278 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
279 WREG32(AVIVO_D2VGA_CONTROL
,
280 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
281 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
282 WREG32(AVIVO_VGA_RENDER_CONTROL
,
283 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
285 WREG32(R600_ROM_CNTL
,
286 ((rom_cntl
& ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK
) |
287 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT
) |
288 R600_SCK_OVERWRITE
));
290 WREG32(R600_GENERAL_PWRMGT
, (general_pwrmgt
& ~R600_OPEN_DRAIN_PADS
));
291 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL
,
292 (low_vid_lower_gpio_cntl
& ~0x400));
293 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
,
294 (medium_vid_lower_gpio_cntl
& ~0x400));
295 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
,
296 (high_vid_lower_gpio_cntl
& ~0x400));
297 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
,
298 (ctxsw_vid_lower_gpio_cntl
& ~0x400));
299 WREG32(R600_LOWER_GPIO_ENABLE
, (lower_gpio_enable
| 0x400));
301 r
= radeon_read_bios(rdev
);
304 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
305 WREG32(R600_BUS_CNTL
, bus_cntl
);
306 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
307 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
308 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
309 WREG32(R600_ROM_CNTL
, rom_cntl
);
310 WREG32(R600_GENERAL_PWRMGT
, general_pwrmgt
);
311 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL
, low_vid_lower_gpio_cntl
);
312 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL
, medium_vid_lower_gpio_cntl
);
313 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL
, high_vid_lower_gpio_cntl
);
314 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL
, ctxsw_vid_lower_gpio_cntl
);
315 WREG32(R600_LOWER_GPIO_ENABLE
, lower_gpio_enable
);
319 static bool avivo_read_disabled_bios(struct radeon_device
*rdev
)
321 uint32_t seprom_cntl1
;
322 uint32_t viph_control
;
324 uint32_t d1vga_control
;
325 uint32_t d2vga_control
;
326 uint32_t vga_render_control
;
329 uint32_t gpiopad_mask
;
332 seprom_cntl1
= RREG32(RADEON_SEPROM_CNTL1
);
333 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
334 bus_cntl
= RREG32(RV370_BUS_CNTL
);
335 d1vga_control
= RREG32(AVIVO_D1VGA_CONTROL
);
336 d2vga_control
= RREG32(AVIVO_D2VGA_CONTROL
);
337 vga_render_control
= RREG32(AVIVO_VGA_RENDER_CONTROL
);
338 gpiopad_a
= RREG32(RADEON_GPIOPAD_A
);
339 gpiopad_en
= RREG32(RADEON_GPIOPAD_EN
);
340 gpiopad_mask
= RREG32(RADEON_GPIOPAD_MASK
);
342 WREG32(RADEON_SEPROM_CNTL1
,
343 ((seprom_cntl1
& ~RADEON_SCK_PRESCALE_MASK
) |
344 (0xc << RADEON_SCK_PRESCALE_SHIFT
)));
345 WREG32(RADEON_GPIOPAD_A
, 0);
346 WREG32(RADEON_GPIOPAD_EN
, 0);
347 WREG32(RADEON_GPIOPAD_MASK
, 0);
350 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
353 WREG32(RV370_BUS_CNTL
, (bus_cntl
& ~RV370_BUS_BIOS_DIS_ROM
));
355 /* Disable VGA mode */
356 WREG32(AVIVO_D1VGA_CONTROL
,
357 (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
358 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
359 WREG32(AVIVO_D2VGA_CONTROL
,
360 (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
|
361 AVIVO_DVGA_CONTROL_TIMING_SELECT
)));
362 WREG32(AVIVO_VGA_RENDER_CONTROL
,
363 (vga_render_control
& ~AVIVO_VGA_VSTATUS_CNTL_MASK
));
365 r
= radeon_read_bios(rdev
);
368 WREG32(RADEON_SEPROM_CNTL1
, seprom_cntl1
);
369 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
370 WREG32(RV370_BUS_CNTL
, bus_cntl
);
371 WREG32(AVIVO_D1VGA_CONTROL
, d1vga_control
);
372 WREG32(AVIVO_D2VGA_CONTROL
, d2vga_control
);
373 WREG32(AVIVO_VGA_RENDER_CONTROL
, vga_render_control
);
374 WREG32(RADEON_GPIOPAD_A
, gpiopad_a
);
375 WREG32(RADEON_GPIOPAD_EN
, gpiopad_en
);
376 WREG32(RADEON_GPIOPAD_MASK
, gpiopad_mask
);
380 static bool legacy_read_disabled_bios(struct radeon_device
*rdev
)
382 uint32_t seprom_cntl1
;
383 uint32_t viph_control
;
385 uint32_t crtc_gen_cntl
;
386 uint32_t crtc2_gen_cntl
;
387 uint32_t crtc_ext_cntl
;
388 uint32_t fp2_gen_cntl
;
391 seprom_cntl1
= RREG32(RADEON_SEPROM_CNTL1
);
392 viph_control
= RREG32(RADEON_VIPH_CONTROL
);
393 if (rdev
->flags
& RADEON_IS_PCIE
)
394 bus_cntl
= RREG32(RV370_BUS_CNTL
);
396 bus_cntl
= RREG32(RADEON_BUS_CNTL
);
397 crtc_gen_cntl
= RREG32(RADEON_CRTC_GEN_CNTL
);
399 crtc_ext_cntl
= RREG32(RADEON_CRTC_EXT_CNTL
);
402 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
403 fp2_gen_cntl
= RREG32(RADEON_FP2_GEN_CNTL
);
406 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
407 crtc2_gen_cntl
= RREG32(RADEON_CRTC2_GEN_CNTL
);
410 WREG32(RADEON_SEPROM_CNTL1
,
411 ((seprom_cntl1
& ~RADEON_SCK_PRESCALE_MASK
) |
412 (0xc << RADEON_SCK_PRESCALE_SHIFT
)));
415 WREG32(RADEON_VIPH_CONTROL
, (viph_control
& ~RADEON_VIPH_EN
));
418 if (rdev
->flags
& RADEON_IS_PCIE
)
419 WREG32(RV370_BUS_CNTL
, (bus_cntl
& ~RV370_BUS_BIOS_DIS_ROM
));
421 WREG32(RADEON_BUS_CNTL
, (bus_cntl
& ~RADEON_BUS_BIOS_DIS_ROM
));
423 /* Turn off mem requests and CRTC for both controllers */
424 WREG32(RADEON_CRTC_GEN_CNTL
,
425 ((crtc_gen_cntl
& ~RADEON_CRTC_EN
) |
426 (RADEON_CRTC_DISP_REQ_EN_B
|
427 RADEON_CRTC_EXT_DISP_EN
)));
428 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
429 WREG32(RADEON_CRTC2_GEN_CNTL
,
430 ((crtc2_gen_cntl
& ~RADEON_CRTC2_EN
) |
431 RADEON_CRTC2_DISP_REQ_EN_B
));
434 WREG32(RADEON_CRTC_EXT_CNTL
,
435 ((crtc_ext_cntl
& ~RADEON_CRTC_CRT_ON
) |
436 (RADEON_CRTC_SYNC_TRISTAT
|
437 RADEON_CRTC_DISPLAY_DIS
)));
439 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
440 WREG32(RADEON_FP2_GEN_CNTL
, (fp2_gen_cntl
& ~RADEON_FP2_ON
));
443 r
= radeon_read_bios(rdev
);
446 WREG32(RADEON_SEPROM_CNTL1
, seprom_cntl1
);
447 WREG32(RADEON_VIPH_CONTROL
, viph_control
);
448 if (rdev
->flags
& RADEON_IS_PCIE
)
449 WREG32(RV370_BUS_CNTL
, bus_cntl
);
451 WREG32(RADEON_BUS_CNTL
, bus_cntl
);
452 WREG32(RADEON_CRTC_GEN_CNTL
, crtc_gen_cntl
);
453 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
454 WREG32(RADEON_CRTC2_GEN_CNTL
, crtc2_gen_cntl
);
456 WREG32(RADEON_CRTC_EXT_CNTL
, crtc_ext_cntl
);
457 if (rdev
->ddev
->pci_device
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
458 WREG32(RADEON_FP2_GEN_CNTL
, fp2_gen_cntl
);
463 static bool radeon_read_disabled_bios(struct radeon_device
*rdev
)
465 if (rdev
->flags
& RADEON_IS_IGP
)
466 return igp_read_bios_from_vram(rdev
);
467 else if (rdev
->family
>= CHIP_BARTS
)
468 return ni_read_disabled_bios(rdev
);
469 else if (rdev
->family
>= CHIP_RV770
)
470 return r700_read_disabled_bios(rdev
);
471 else if (rdev
->family
>= CHIP_R600
)
472 return r600_read_disabled_bios(rdev
);
473 else if (rdev
->family
>= CHIP_RS600
)
474 return avivo_read_disabled_bios(rdev
);
476 return legacy_read_disabled_bios(rdev
);
480 bool radeon_get_bios(struct radeon_device
*rdev
)
485 r
= radeon_atrm_get_bios(rdev
);
487 r
= igp_read_bios_from_vram(rdev
);
489 r
= radeon_read_bios(rdev
);
491 r
= radeon_read_disabled_bios(rdev
);
493 if (r
== false || rdev
->bios
== NULL
) {
494 DRM_ERROR("Unable to locate a BIOS ROM\n");
498 if (rdev
->bios
[0] != 0x55 || rdev
->bios
[1] != 0xaa) {
499 printk("BIOS signature incorrect %x %x\n", rdev
->bios
[0], rdev
->bios
[1]);
504 if (RBIOS8(tmp
+ 0x14) != 0x0) {
505 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
509 rdev
->bios_header_start
= RBIOS16(0x48);
510 if (!rdev
->bios_header_start
) {
513 tmp
= rdev
->bios_header_start
+ 4;
514 if (!memcmp(rdev
->bios
+ tmp
, "ATOM", 4) ||
515 !memcmp(rdev
->bios
+ tmp
, "MOTA", 4)) {
516 rdev
->is_atom_bios
= true;
518 rdev
->is_atom_bios
= false;
521 DRM_DEBUG("%sBIOS detected\n", rdev
->is_atom_bios
? "ATOM" : "COM");