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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / infiniband / hw / mthca / mthca_cmd.c
blob3082b3b3d620aec288d0f5245be798f09a6f65bf
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/completion.h>
36 #include <linux/pci.h>
37 #include <linux/errno.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <asm/io.h>
41 #include <rdma/ib_mad.h>
42
43 #include "mthca_dev.h"
44 #include "mthca_config_reg.h"
45 #include "mthca_cmd.h"
46 #include "mthca_memfree.h"
47
48 #define CMD_POLL_TOKEN 0xffff
49
50 enum {
51 HCR_IN_PARAM_OFFSET = 0x00,
52 HCR_IN_MODIFIER_OFFSET = 0x08,
53 HCR_OUT_PARAM_OFFSET = 0x0c,
54 HCR_TOKEN_OFFSET = 0x14,
55 HCR_STATUS_OFFSET = 0x18,
56
57 HCR_OPMOD_SHIFT = 12,
58 HCA_E_BIT = 22,
59 HCR_GO_BIT = 23
60 };
61
62 enum {
63 /* initialization and general commands */
64 CMD_SYS_EN = 0x1,
65 CMD_SYS_DIS = 0x2,
66 CMD_MAP_FA = 0xfff,
67 CMD_UNMAP_FA = 0xffe,
68 CMD_RUN_FW = 0xff6,
69 CMD_MOD_STAT_CFG = 0x34,
70 CMD_QUERY_DEV_LIM = 0x3,
71 CMD_QUERY_FW = 0x4,
72 CMD_ENABLE_LAM = 0xff8,
73 CMD_DISABLE_LAM = 0xff7,
74 CMD_QUERY_DDR = 0x5,
75 CMD_QUERY_ADAPTER = 0x6,
76 CMD_INIT_HCA = 0x7,
77 CMD_CLOSE_HCA = 0x8,
78 CMD_INIT_IB = 0x9,
79 CMD_CLOSE_IB = 0xa,
80 CMD_QUERY_HCA = 0xb,
81 CMD_SET_IB = 0xc,
82 CMD_ACCESS_DDR = 0x2e,
83 CMD_MAP_ICM = 0xffa,
84 CMD_UNMAP_ICM = 0xff9,
85 CMD_MAP_ICM_AUX = 0xffc,
86 CMD_UNMAP_ICM_AUX = 0xffb,
87 CMD_SET_ICM_SIZE = 0xffd,
88
89 /* TPT commands */
90 CMD_SW2HW_MPT = 0xd,
91 CMD_QUERY_MPT = 0xe,
92 CMD_HW2SW_MPT = 0xf,
93 CMD_READ_MTT = 0x10,
94 CMD_WRITE_MTT = 0x11,
95 CMD_SYNC_TPT = 0x2f,
96
97 /* EQ commands */
98 CMD_MAP_EQ = 0x12,
99 CMD_SW2HW_EQ = 0x13,
100 CMD_HW2SW_EQ = 0x14,
101 CMD_QUERY_EQ = 0x15,
102
103 /* CQ commands */
104 CMD_SW2HW_CQ = 0x16,
105 CMD_HW2SW_CQ = 0x17,
106 CMD_QUERY_CQ = 0x18,
107 CMD_RESIZE_CQ = 0x2c,
108
109 /* SRQ commands */
110 CMD_SW2HW_SRQ = 0x35,
111 CMD_HW2SW_SRQ = 0x36,
112 CMD_QUERY_SRQ = 0x37,
113 CMD_ARM_SRQ = 0x40,
114
115 /* QP/EE commands */
116 CMD_RST2INIT_QPEE = 0x19,
117 CMD_INIT2RTR_QPEE = 0x1a,
118 CMD_RTR2RTS_QPEE = 0x1b,
119 CMD_RTS2RTS_QPEE = 0x1c,
120 CMD_SQERR2RTS_QPEE = 0x1d,
121 CMD_2ERR_QPEE = 0x1e,
122 CMD_RTS2SQD_QPEE = 0x1f,
123 CMD_SQD2SQD_QPEE = 0x38,
124 CMD_SQD2RTS_QPEE = 0x20,
125 CMD_ERR2RST_QPEE = 0x21,
126 CMD_QUERY_QPEE = 0x22,
127 CMD_INIT2INIT_QPEE = 0x2d,
128 CMD_SUSPEND_QPEE = 0x32,
129 CMD_UNSUSPEND_QPEE = 0x33,
130 /* special QPs and management commands */
131 CMD_CONF_SPECIAL_QP = 0x23,
132 CMD_MAD_IFC = 0x24,
133
134 /* multicast commands */
135 CMD_READ_MGM = 0x25,
136 CMD_WRITE_MGM = 0x26,
137 CMD_MGID_HASH = 0x27,
138
139 /* miscellaneous commands */
140 CMD_DIAG_RPRT = 0x30,
141 CMD_NOP = 0x31,
142
143 /* debug commands */
144 CMD_QUERY_DEBUG_MSG = 0x2a,
145 CMD_SET_DEBUG_MSG = 0x2b,
146 };
147
148 /*
149 * According to Mellanox code, FW may be starved and never complete
150 * commands. So we can't use strict timeouts described in PRM -- we
151 * just arbitrarily select 60 seconds for now.
152 */
153 #if 0
154 /*
155 * Round up and add 1 to make sure we get the full wait time (since we
156 * will be starting in the middle of a jiffy)
157 */
158 enum {
159 CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
160 CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
161 CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1,
162 CMD_TIME_CLASS_D = 60 * HZ
163 };
164 #else
165 enum {
166 CMD_TIME_CLASS_A = 60 * HZ,
167 CMD_TIME_CLASS_B = 60 * HZ,
168 CMD_TIME_CLASS_C = 60 * HZ,
169 CMD_TIME_CLASS_D = 60 * HZ
170 };
171 #endif
172
173 enum {
174 GO_BIT_TIMEOUT = HZ * 10
175 };
176
177 struct mthca_cmd_context {
178 struct completion done;
179 int result;
180 int next;
181 u64 out_param;
182 u16 token;
183 u8 status;
184 };
185
186 static int fw_cmd_doorbell = 0;
187 module_param(fw_cmd_doorbell, int, 0644);
188 MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
189 "(and supported by FW)");
190
191 static inline int go_bit(struct mthca_dev *dev)
192 {
193 return readl(dev->hcr + HCR_STATUS_OFFSET) &
194 swab32(1 << HCR_GO_BIT);
195 }
196
197 static void mthca_cmd_post_dbell(struct mthca_dev *dev,
198 u64 in_param,
199 u64 out_param,
200 u32 in_modifier,
201 u8 op_modifier,
202 u16 op,
203 u16 token)
204 {
205 void __iomem *ptr = dev->cmd.dbell_map;
206 u16 *offs = dev->cmd.dbell_offsets;
207
208 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
209 wmb();
210 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
211 wmb();
212 __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
213 wmb();
214 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
215 wmb();
216 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
217 wmb();
218 __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
219 wmb();
220 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
221 (1 << HCA_E_BIT) |
222 (op_modifier << HCR_OPMOD_SHIFT) |
223 op), ptr + offs[6]);
224 wmb();
225 __raw_writel((__force u32) 0, ptr + offs[7]);
226 wmb();
227 }
228
229 static int mthca_cmd_post_hcr(struct mthca_dev *dev,
230 u64 in_param,
231 u64 out_param,
232 u32 in_modifier,
233 u8 op_modifier,
234 u16 op,
235 u16 token,
236 int event)
237 {
238 if (event) {
239 unsigned long end = jiffies + GO_BIT_TIMEOUT;
240
241 while (go_bit(dev) && time_before(jiffies, end)) {
242 set_current_state(TASK_RUNNING);
243 schedule();
244 }
245 }
246
247 if (go_bit(dev))
248 return -EAGAIN;
249
250 /*
251 * We use writel (instead of something like memcpy_toio)
252 * because writes of less than 32 bits to the HCR don't work
253 * (and some architectures such as ia64 implement memcpy_toio
254 * in terms of writeb).
255 */
256 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
257 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
258 __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
259 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
260 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
261 __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
262
263 /* __raw_writel may not order writes. */
264 wmb();
265
266 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
267 (event ? (1 << HCA_E_BIT) : 0) |
268 (op_modifier << HCR_OPMOD_SHIFT) |
269 op), dev->hcr + 6 * 4);
270
271 return 0;
272 }
273
274 static int mthca_cmd_post(struct mthca_dev *dev,
275 u64 in_param,
276 u64 out_param,
277 u32 in_modifier,
278 u8 op_modifier,
279 u16 op,
280 u16 token,
281 int event)
282 {
283 int err = 0;
284
285 mutex_lock(&dev->cmd.hcr_mutex);
286
287 if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
288 mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
289 op_modifier, op, token);
290 else
291 err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
292 op_modifier, op, token, event);
293
294 /*
295 * Make sure that our HCR writes don't get mixed in with
296 * writes from another CPU starting a FW command.
297 */
298 mmiowb();
299
300 mutex_unlock(&dev->cmd.hcr_mutex);
301 return err;
302 }
303
304
305 static int mthca_status_to_errno(u8 status)
306 {
307 static const int trans_table[] = {
308 [MTHCA_CMD_STAT_INTERNAL_ERR] = -EIO,
309 [MTHCA_CMD_STAT_BAD_OP] = -EPERM,
310 [MTHCA_CMD_STAT_BAD_PARAM] = -EINVAL,
311 [MTHCA_CMD_STAT_BAD_SYS_STATE] = -ENXIO,
312 [MTHCA_CMD_STAT_BAD_RESOURCE] = -EBADF,
313 [MTHCA_CMD_STAT_RESOURCE_BUSY] = -EBUSY,
314 [MTHCA_CMD_STAT_DDR_MEM_ERR] = -ENOMEM,
315 [MTHCA_CMD_STAT_EXCEED_LIM] = -ENOMEM,
316 [MTHCA_CMD_STAT_BAD_RES_STATE] = -EBADF,
317 [MTHCA_CMD_STAT_BAD_INDEX] = -EBADF,
318 [MTHCA_CMD_STAT_BAD_NVMEM] = -EFAULT,
319 [MTHCA_CMD_STAT_BAD_QPEE_STATE] = -EINVAL,
320 [MTHCA_CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
321 [MTHCA_CMD_STAT_REG_BOUND] = -EBUSY,
322 [MTHCA_CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
323 [MTHCA_CMD_STAT_BAD_PKT] = -EBADMSG,
324 [MTHCA_CMD_STAT_BAD_SIZE] = -ENOMEM,
325 };
326
327 if (status >= ARRAY_SIZE(trans_table) ||
328 (status != MTHCA_CMD_STAT_OK
329 && trans_table[status] == 0))
330 return -EINVAL;
331
332 return trans_table[status];
333 }
334
335
336 static int mthca_cmd_poll(struct mthca_dev *dev,
337 u64 in_param,
338 u64 *out_param,
339 int out_is_imm,
340 u32 in_modifier,
341 u8 op_modifier,
342 u16 op,
343 unsigned long timeout)
344 {
345 int err = 0;
346 unsigned long end;
347 u8 status;
348
349 down(&dev->cmd.poll_sem);
350
351 err = mthca_cmd_post(dev, in_param,
352 out_param ? *out_param : 0,
353 in_modifier, op_modifier,
354 op, CMD_POLL_TOKEN, 0);
355 if (err)
356 goto out;
357
358 end = timeout + jiffies;
359 while (go_bit(dev) && time_before(jiffies, end)) {
360 set_current_state(TASK_RUNNING);
361 schedule();
362 }
363
364 if (go_bit(dev)) {
365 err = -EBUSY;
366 goto out;
367 }
368
369 if (out_is_imm)
370 *out_param =
371 (u64) be32_to_cpu((__force __be32)
372 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
373 (u64) be32_to_cpu((__force __be32)
374 __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
375
376 status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
377 if (status) {
378 mthca_dbg(dev, "Command %02x completed with status %02x\n",
379 op, status);
380 err = mthca_status_to_errno(status);
381 }
382
383 out:
384 up(&dev->cmd.poll_sem);
385 return err;
386 }
387
388 void mthca_cmd_event(struct mthca_dev *dev,
389 u16 token,
390 u8 status,
391 u64 out_param)
392 {
393 struct mthca_cmd_context *context =
394 &dev->cmd.context[token & dev->cmd.token_mask];
395
396 /* previously timed out command completing at long last */
397 if (token != context->token)
398 return;
399
400 context->result = 0;
401 context->status = status;
402 context->out_param = out_param;
403
404 complete(&context->done);
405 }
406
407 static int mthca_cmd_wait(struct mthca_dev *dev,
408 u64 in_param,
409 u64 *out_param,
410 int out_is_imm,
411 u32 in_modifier,
412 u8 op_modifier,
413 u16 op,
414 unsigned long timeout)
415 {
416 int err = 0;
417 struct mthca_cmd_context *context;
418
419 down(&dev->cmd.event_sem);
420
421 spin_lock(&dev->cmd.context_lock);
422 BUG_ON(dev->cmd.free_head < 0);
423 context = &dev->cmd.context[dev->cmd.free_head];
424 context->token += dev->cmd.token_mask + 1;
425 dev->cmd.free_head = context->next;
426 spin_unlock(&dev->cmd.context_lock);
427
428 init_completion(&context->done);
429
430 err = mthca_cmd_post(dev, in_param,
431 out_param ? *out_param : 0,
432 in_modifier, op_modifier,
433 op, context->token, 1);
434 if (err)
435 goto out;
436
437 if (!wait_for_completion_timeout(&context->done, timeout)) {
438 err = -EBUSY;
439 goto out;
440 }
441
442 err = context->result;
443 if (err)
444 goto out;
445
446 if (context->status) {
447 mthca_dbg(dev, "Command %02x completed with status %02x\n",
448 op, context->status);
449 err = mthca_status_to_errno(context->status);
450 }
451
452 if (out_is_imm)
453 *out_param = context->out_param;
454
455 out:
456 spin_lock(&dev->cmd.context_lock);
457 context->next = dev->cmd.free_head;
458 dev->cmd.free_head = context - dev->cmd.context;
459 spin_unlock(&dev->cmd.context_lock);
460
461 up(&dev->cmd.event_sem);
462 return err;
463 }
464
465 /* Invoke a command with an output mailbox */
466 static int mthca_cmd_box(struct mthca_dev *dev,
467 u64 in_param,
468 u64 out_param,
469 u32 in_modifier,
470 u8 op_modifier,
471 u16 op,
472 unsigned long timeout)
473 {
474 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
475 return mthca_cmd_wait(dev, in_param, &out_param, 0,
476 in_modifier, op_modifier, op,
477 timeout);
478 else
479 return mthca_cmd_poll(dev, in_param, &out_param, 0,
480 in_modifier, op_modifier, op,
481 timeout);
482 }
483
484 /* Invoke a command with no output parameter */
485 static int mthca_cmd(struct mthca_dev *dev,
486 u64 in_param,
487 u32 in_modifier,
488 u8 op_modifier,
489 u16 op,
490 unsigned long timeout)
491 {
492 return mthca_cmd_box(dev, in_param, 0, in_modifier,
493 op_modifier, op, timeout);
494 }
495
496 /*
497 * Invoke a command with an immediate output parameter (and copy the
498 * output into the caller's out_param pointer after the command
499 * executes).
500 */
501 static int mthca_cmd_imm(struct mthca_dev *dev,
502 u64 in_param,
503 u64 *out_param,
504 u32 in_modifier,
505 u8 op_modifier,
506 u16 op,
507 unsigned long timeout)
508 {
509 if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
510 return mthca_cmd_wait(dev, in_param, out_param, 1,
511 in_modifier, op_modifier, op,
512 timeout);
513 else
514 return mthca_cmd_poll(dev, in_param, out_param, 1,
515 in_modifier, op_modifier, op,
516 timeout);
517 }
518
519 int mthca_cmd_init(struct mthca_dev *dev)
520 {
521 mutex_init(&dev->cmd.hcr_mutex);
522 sema_init(&dev->cmd.poll_sem, 1);
523 dev->cmd.flags = 0;
524
525 dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
526 MTHCA_HCR_SIZE);
527 if (!dev->hcr) {
528 mthca_err(dev, "Couldn't map command register.");
529 return -ENOMEM;
530 }
531
532 dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
533 MTHCA_MAILBOX_SIZE,
534 MTHCA_MAILBOX_SIZE, 0);
535 if (!dev->cmd.pool) {
536 iounmap(dev->hcr);
537 return -ENOMEM;
538 }
539
540 return 0;
541 }
542
543 void mthca_cmd_cleanup(struct mthca_dev *dev)
544 {
545 pci_pool_destroy(dev->cmd.pool);
546 iounmap(dev->hcr);
547 if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
548 iounmap(dev->cmd.dbell_map);
549 }
550
551 /*
552 * Switch to using events to issue FW commands (should be called after
553 * event queue to command events has been initialized).
554 */
555 int mthca_cmd_use_events(struct mthca_dev *dev)
556 {
557 int i;
558
559 dev->cmd.context = kmalloc(dev->cmd.max_cmds *
560 sizeof (struct mthca_cmd_context),
561 GFP_KERNEL);
562 if (!dev->cmd.context)
563 return -ENOMEM;
564
565 for (i = 0; i < dev->cmd.max_cmds; ++i) {
566 dev->cmd.context[i].token = i;
567 dev->cmd.context[i].next = i + 1;
568 }
569
570 dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
571 dev->cmd.free_head = 0;
572
573 sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
574 spin_lock_init(&dev->cmd.context_lock);
575
576 for (dev->cmd.token_mask = 1;
577 dev->cmd.token_mask < dev->cmd.max_cmds;
578 dev->cmd.token_mask <<= 1)
579 ; /* nothing */
580 --dev->cmd.token_mask;
581
582 dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
583
584 down(&dev->cmd.poll_sem);
585
586 return 0;
587 }
588
589 /*
590 * Switch back to polling (used when shutting down the device)
591 */
592 void mthca_cmd_use_polling(struct mthca_dev *dev)
593 {
594 int i;
595
596 dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
597
598 for (i = 0; i < dev->cmd.max_cmds; ++i)
599 down(&dev->cmd.event_sem);
600
601 kfree(dev->cmd.context);
602
603 up(&dev->cmd.poll_sem);
604 }
605
606 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
607 gfp_t gfp_mask)
608 {
609 struct mthca_mailbox *mailbox;
610
611 mailbox = kmalloc(sizeof *mailbox, gfp_mask);
612 if (!mailbox)
613 return ERR_PTR(-ENOMEM);
614
615 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
616 if (!mailbox->buf) {
617 kfree(mailbox);
618 return ERR_PTR(-ENOMEM);
619 }
620
621 return mailbox;
622 }
623
624 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
625 {
626 if (!mailbox)
627 return;
628
629 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
630 kfree(mailbox);
631 }
632
633 int mthca_SYS_EN(struct mthca_dev *dev)
634 {
635 u64 out;
636 int ret;
637
638 ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D);
639
640 if (ret == -ENOMEM)
641 mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
642 "sladdr=%d, SPD source=%s\n",
643 (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
644 (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
645
646 return ret;
647 }
648
649 int mthca_SYS_DIS(struct mthca_dev *dev)
650 {
651 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
652 }
653
654 static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
655 u64 virt)
656 {
657 struct mthca_mailbox *mailbox;
658 struct mthca_icm_iter iter;
659 __be64 *pages;
660 int lg;
661 int nent = 0;
662 int i;
663 int err = 0;
664 int ts = 0, tc = 0;
665
666 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
667 if (IS_ERR(mailbox))
668 return PTR_ERR(mailbox);
669 memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
670 pages = mailbox->buf;
671
672 for (mthca_icm_first(icm, &iter);
673 !mthca_icm_last(&iter);
674 mthca_icm_next(&iter)) {
675 /*
676 * We have to pass pages that are aligned to their
677 * size, so find the least significant 1 in the
678 * address or size and use that as our log2 size.
679 */
680 lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
681 if (lg < MTHCA_ICM_PAGE_SHIFT) {
682 mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
683 MTHCA_ICM_PAGE_SIZE,
684 (unsigned long long) mthca_icm_addr(&iter),
685 mthca_icm_size(&iter));
686 err = -EINVAL;
687 goto out;
688 }
689 for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
690 if (virt != -1) {
691 pages[nent * 2] = cpu_to_be64(virt);
692 virt += 1 << lg;
693 }
694
695 pages[nent * 2 + 1] =
696 cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
697 (lg - MTHCA_ICM_PAGE_SHIFT));
698 ts += 1 << (lg - 10);
699 ++tc;
700
701 if (++nent == MTHCA_MAILBOX_SIZE / 16) {
702 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
703 CMD_TIME_CLASS_B);
704 if (err)
705 goto out;
706 nent = 0;
707 }
708 }
709 }
710
711 if (nent)
712 err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
713 CMD_TIME_CLASS_B);
714
715 switch (op) {
716 case CMD_MAP_FA:
717 mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
718 break;
719 case CMD_MAP_ICM_AUX:
720 mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
721 break;
722 case CMD_MAP_ICM:
723 mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
724 tc, ts, (unsigned long long) virt - (ts << 10));
725 break;
726 }
727
728 out:
729 mthca_free_mailbox(dev, mailbox);
730 return err;
731 }
732
733 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm)
734 {
735 return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1);
736 }
737
738 int mthca_UNMAP_FA(struct mthca_dev *dev)
739 {
740 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B);
741 }
742
743 int mthca_RUN_FW(struct mthca_dev *dev)
744 {
745 return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A);
746 }
747
748 static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
749 {
750 phys_addr_t addr;
751 u16 max_off = 0;
752 int i;
753
754 for (i = 0; i < 8; ++i)
755 max_off = max(max_off, dev->cmd.dbell_offsets[i]);
756
757 if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
758 mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
759 "length 0x%x crosses a page boundary\n",
760 (unsigned long long) base, max_off);
761 return;
762 }
763
764 addr = pci_resource_start(dev->pdev, 2) +
765 ((pci_resource_len(dev->pdev, 2) - 1) & base);
766 dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
767 if (!dev->cmd.dbell_map)
768 return;
769
770 dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
771 mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
772 }
773
774 int mthca_QUERY_FW(struct mthca_dev *dev)
775 {
776 struct mthca_mailbox *mailbox;
777 u32 *outbox;
778 u64 base;
779 u32 tmp;
780 int err = 0;
781 u8 lg;
782 int i;
783
784 #define QUERY_FW_OUT_SIZE 0x100
785 #define QUERY_FW_VER_OFFSET 0x00
786 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
787 #define QUERY_FW_ERR_START_OFFSET 0x30
788 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
789
790 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
791 #define QUERY_FW_CMD_DB_OFFSET 0x50
792 #define QUERY_FW_CMD_DB_BASE 0x60
793
794 #define QUERY_FW_START_OFFSET 0x20
795 #define QUERY_FW_END_OFFSET 0x28
796
797 #define QUERY_FW_SIZE_OFFSET 0x00
798 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
799 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
800 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
801
802 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
803 if (IS_ERR(mailbox))
804 return PTR_ERR(mailbox);
805 outbox = mailbox->buf;
806
807 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
808 CMD_TIME_CLASS_A);
809
810 if (err)
811 goto out;
812
813 MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
814 /*
815 * FW subminor version is at more significant bits than minor
816 * version, so swap here.
817 */
818 dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
819 ((dev->fw_ver & 0xffff0000ull) >> 16) |
820 ((dev->fw_ver & 0x0000ffffull) << 16);
821
822 MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
823 dev->cmd.max_cmds = 1 << lg;
824
825 mthca_dbg(dev, "FW version %012llx, max commands %d\n",
826 (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
827
828 MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
829 MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
830
831 mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
832 (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
833
834 MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
835 if (tmp & 0x1) {
836 mthca_dbg(dev, "FW supports commands through doorbells\n");
837
838 MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
839 for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
840 MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
841 QUERY_FW_CMD_DB_OFFSET + (i << 1));
842
843 mthca_setup_cmd_doorbells(dev, base);
844 }
845
846 if (mthca_is_memfree(dev)) {
847 MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
848 MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
849 MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
850 MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
851 mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
852
853 /*
854 * Round up number of system pages needed in case
855 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
856 */
857 dev->fw.arbel.fw_pages =
858 ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
859 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
860
861 mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
862 (unsigned long long) dev->fw.arbel.clr_int_base,
863 (unsigned long long) dev->fw.arbel.eq_arm_base,
864 (unsigned long long) dev->fw.arbel.eq_set_ci_base);
865 } else {
866 MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
867 MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
868
869 mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
870 (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
871 (unsigned long long) dev->fw.tavor.fw_start,
872 (unsigned long long) dev->fw.tavor.fw_end);
873 }
874
875 out:
876 mthca_free_mailbox(dev, mailbox);
877 return err;
878 }
879
880 int mthca_ENABLE_LAM(struct mthca_dev *dev)
881 {
882 struct mthca_mailbox *mailbox;
883 u8 info;
884 u32 *outbox;
885 int err = 0;
886
887 #define ENABLE_LAM_OUT_SIZE 0x100
888 #define ENABLE_LAM_START_OFFSET 0x00
889 #define ENABLE_LAM_END_OFFSET 0x08
890 #define ENABLE_LAM_INFO_OFFSET 0x13
891
892 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
893 #define ENABLE_LAM_INFO_ECC_MASK 0x3
894
895 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
896 if (IS_ERR(mailbox))
897 return PTR_ERR(mailbox);
898 outbox = mailbox->buf;
899
900 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
901 CMD_TIME_CLASS_C);
902
903 if (err)
904 goto out;
905
906 MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
907 MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
908 MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
909
910 if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
911 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
912 mthca_info(dev, "FW reports that HCA-attached memory "
913 "is %s hidden; does not match PCI config\n",
914 (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
915 "" : "not");
916 }
917 if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
918 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
919
920 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
921 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
922 (unsigned long long) dev->ddr_start,
923 (unsigned long long) dev->ddr_end);
924
925 out:
926 mthca_free_mailbox(dev, mailbox);
927 return err;
928 }
929
930 int mthca_DISABLE_LAM(struct mthca_dev *dev)
931 {
932 return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C);
933 }
934
935 int mthca_QUERY_DDR(struct mthca_dev *dev)
936 {
937 struct mthca_mailbox *mailbox;
938 u8 info;
939 u32 *outbox;
940 int err = 0;
941
942 #define QUERY_DDR_OUT_SIZE 0x100
943 #define QUERY_DDR_START_OFFSET 0x00
944 #define QUERY_DDR_END_OFFSET 0x08
945 #define QUERY_DDR_INFO_OFFSET 0x13
946
947 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
948 #define QUERY_DDR_INFO_ECC_MASK 0x3
949
950 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
951 if (IS_ERR(mailbox))
952 return PTR_ERR(mailbox);
953 outbox = mailbox->buf;
954
955 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
956 CMD_TIME_CLASS_A);
957
958 if (err)
959 goto out;
960
961 MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
962 MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
963 MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
964
965 if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
966 !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
967 mthca_info(dev, "FW reports that HCA-attached memory "
968 "is %s hidden; does not match PCI config\n",
969 (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
970 "" : "not");
971 }
972 if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
973 mthca_dbg(dev, "HCA-attached memory is hidden.\n");
974
975 mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
976 (int) ((dev->ddr_end - dev->ddr_start) >> 10),
977 (unsigned long long) dev->ddr_start,
978 (unsigned long long) dev->ddr_end);
979
980 out:
981 mthca_free_mailbox(dev, mailbox);
982 return err;
983 }
984
985 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
986 struct mthca_dev_lim *dev_lim)
987 {
988 struct mthca_mailbox *mailbox;
989 u32 *outbox;
990 u8 field;
991 u16 size;
992 u16 stat_rate;
993 int err;
994
995 #define QUERY_DEV_LIM_OUT_SIZE 0x100
996 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
997 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
998 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
999 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
1000 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
1001 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
1002 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
1003 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
1004 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
1005 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
1006 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
1007 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
1008 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
1009 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
1010 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
1011 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
1012 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
1013 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
1014 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
1015 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
1016 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
1017 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
1018 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
1019 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
1020 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
1021 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
1022 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
1023 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
1024 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
1025 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
1026 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
1027 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
1028 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
1029 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
1030 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
1031 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
1032 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
1033 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
1034 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
1035 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
1036 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
1037 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
1038 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
1039 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1040 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1041 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1042 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1043 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1044 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1045 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1046 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1047 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1048 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1049 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1050 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1051 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1052 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1053 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1054 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1055
1056 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1057 if (IS_ERR(mailbox))
1058 return PTR_ERR(mailbox);
1059 outbox = mailbox->buf;
1060
1061 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
1062 CMD_TIME_CLASS_A);
1063
1064 if (err)
1065 goto out;
1066
1067 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
1068 dev_lim->reserved_qps = 1 << (field & 0xf);
1069 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
1070 dev_lim->max_qps = 1 << (field & 0x1f);
1071 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
1072 dev_lim->reserved_srqs = 1 << (field >> 4);
1073 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
1074 dev_lim->max_srqs = 1 << (field & 0x1f);
1075 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
1076 dev_lim->reserved_eecs = 1 << (field & 0xf);
1077 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
1078 dev_lim->max_eecs = 1 << (field & 0x1f);
1079 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
1080 dev_lim->max_cq_sz = 1 << field;
1081 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
1082 dev_lim->reserved_cqs = 1 << (field & 0xf);
1083 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
1084 dev_lim->max_cqs = 1 << (field & 0x1f);
1085 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
1086 dev_lim->max_mpts = 1 << (field & 0x3f);
1087 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
1088 dev_lim->reserved_eqs = 1 << (field & 0xf);
1089 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
1090 dev_lim->max_eqs = 1 << (field & 0x7);
1091 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
1092 if (mthca_is_memfree(dev))
1093 dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64),
1094 dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size;
1095 else
1096 dev_lim->reserved_mtts = 1 << (field >> 4);
1097 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
1098 dev_lim->max_mrw_sz = 1 << field;
1099 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
1100 dev_lim->reserved_mrws = 1 << (field & 0xf);
1101 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
1102 dev_lim->max_mtt_seg = 1 << (field & 0x3f);
1103 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
1104 dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
1105 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
1106 dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
1107 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
1108 dev_lim->max_rdma_global = 1 << (field & 0x3f);
1109 MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
1110 dev_lim->local_ca_ack_delay = field & 0x1f;
1111 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
1112 dev_lim->max_mtu = field >> 4;
1113 dev_lim->max_port_width = field & 0xf;
1114 MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
1115 dev_lim->max_vl = field >> 4;
1116 dev_lim->num_ports = field & 0xf;
1117 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
1118 dev_lim->max_gids = 1 << (field & 0xf);
1119 MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET);
1120 dev_lim->stat_rate_support = stat_rate;
1121 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
1122 dev_lim->max_pkeys = 1 << (field & 0xf);
1123 MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
1124 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
1125 dev_lim->reserved_uars = field >> 4;
1126 MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
1127 dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
1128 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
1129 dev_lim->min_page_sz = 1 << field;
1130 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
1131 dev_lim->max_sg = field;
1132
1133 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
1134 dev_lim->max_desc_sz = size;
1135
1136 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
1137 dev_lim->max_qp_per_mcg = 1 << field;
1138 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
1139 dev_lim->reserved_mgms = field & 0xf;
1140 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
1141 dev_lim->max_mcgs = 1 << field;
1142 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
1143 dev_lim->reserved_pds = field >> 4;
1144 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
1145 dev_lim->max_pds = 1 << (field & 0x3f);
1146 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
1147 dev_lim->reserved_rdds = field >> 4;
1148 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
1149 dev_lim->max_rdds = 1 << (field & 0x3f);
1150
1151 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
1152 dev_lim->eec_entry_sz = size;
1153 MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
1154 dev_lim->qpc_entry_sz = size;
1155 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
1156 dev_lim->eeec_entry_sz = size;
1157 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
1158 dev_lim->eqpc_entry_sz = size;
1159 MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
1160 dev_lim->eqc_entry_sz = size;
1161 MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
1162 dev_lim->cqc_entry_sz = size;
1163 MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
1164 dev_lim->srq_entry_sz = size;
1165 MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
1166 dev_lim->uar_scratch_entry_sz = size;
1167
1168 if (mthca_is_memfree(dev)) {
1169 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1170 dev_lim->max_srq_sz = 1 << field;
1171 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1172 dev_lim->max_qp_sz = 1 << field;
1173 MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
1174 dev_lim->hca.arbel.resize_srq = field & 1;
1175 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
1176 dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
1177 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
1178 dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
1179 MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
1180 dev_lim->mpt_entry_sz = size;
1181 MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
1182 dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
1183 MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
1184 QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
1185 MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
1186 QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
1187 MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
1188 dev_lim->hca.arbel.lam_required = field & 1;
1189 MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
1190 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
1191
1192 if (dev_lim->hca.arbel.bmme_flags & 1)
1193 mthca_dbg(dev, "Base MM extensions: yes "
1194 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1195 dev_lim->hca.arbel.bmme_flags,
1196 dev_lim->hca.arbel.max_pbl_sz,
1197 dev_lim->hca.arbel.reserved_lkey);
1198 else
1199 mthca_dbg(dev, "Base MM extensions: no\n");
1200
1201 mthca_dbg(dev, "Max ICM size %lld MB\n",
1202 (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
1203 } else {
1204 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
1205 dev_lim->max_srq_sz = (1 << field) - 1;
1206 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
1207 dev_lim->max_qp_sz = (1 << field) - 1;
1208 MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
1209 dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
1210 dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
1211 }
1212
1213 mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1214 dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
1215 mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1216 dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
1217 mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1218 dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
1219 mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1220 dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
1221 mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1222 dev_lim->reserved_mrws, dev_lim->reserved_mtts);
1223 mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1224 dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
1225 mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1226 dev_lim->max_pds, dev_lim->reserved_mgms);
1227 mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1228 dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
1229
1230 mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
1231
1232 out:
1233 mthca_free_mailbox(dev, mailbox);
1234 return err;
1235 }
1236
1237 static void get_board_id(void *vsd, char *board_id)
1238 {
1239 int i;
1240
1241 #define VSD_OFFSET_SIG1 0x00
1242 #define VSD_OFFSET_SIG2 0xde
1243 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1244 #define VSD_OFFSET_TS_BOARD_ID 0x20
1245
1246 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1247
1248 memset(board_id, 0, MTHCA_BOARD_ID_LEN);
1249
1250 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1251 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1252 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
1253 } else {
1254 /*
1255 * The board ID is a string but the firmware byte
1256 * swaps each 4-byte word before passing it back to
1257 * us. Therefore we need to swab it before printing.
1258 */
1259 for (i = 0; i < 4; ++i)
1260 ((u32 *) board_id)[i] =
1261 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1262 }
1263 }
1264
1265 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
1266 struct mthca_adapter *adapter)
1267 {
1268 struct mthca_mailbox *mailbox;
1269 u32 *outbox;
1270 int err;
1271
1272 #define QUERY_ADAPTER_OUT_SIZE 0x100
1273 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1274 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1275 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1276 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1277 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1278
1279 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1280 if (IS_ERR(mailbox))
1281 return PTR_ERR(mailbox);
1282 outbox = mailbox->buf;
1283
1284 err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
1285 CMD_TIME_CLASS_A);
1286
1287 if (err)
1288 goto out;
1289
1290 if (!mthca_is_memfree(dev)) {
1291 MTHCA_GET(adapter->vendor_id, outbox,
1292 QUERY_ADAPTER_VENDOR_ID_OFFSET);
1293 MTHCA_GET(adapter->device_id, outbox,
1294 QUERY_ADAPTER_DEVICE_ID_OFFSET);
1295 MTHCA_GET(adapter->revision_id, outbox,
1296 QUERY_ADAPTER_REVISION_ID_OFFSET);
1297 }
1298 MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1299
1300 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1301 adapter->board_id);
1302
1303 out:
1304 mthca_free_mailbox(dev, mailbox);
1305 return err;
1306 }
1307
1308 int mthca_INIT_HCA(struct mthca_dev *dev,
1309 struct mthca_init_hca_param *param)
1310 {
1311 struct mthca_mailbox *mailbox;
1312 __be32 *inbox;
1313 int err;
1314
1315 #define INIT_HCA_IN_SIZE 0x200
1316 #define INIT_HCA_FLAGS1_OFFSET 0x00c
1317 #define INIT_HCA_FLAGS2_OFFSET 0x014
1318 #define INIT_HCA_QPC_OFFSET 0x020
1319 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1320 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1321 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1322 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1323 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1324 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1325 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1326 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1327 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1328 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1329 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1330 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1331 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1332 #define INIT_HCA_UDAV_OFFSET 0x0b0
1333 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1334 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1335 #define INIT_HCA_MCAST_OFFSET 0x0c0
1336 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1337 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1338 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1339 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1340 #define INIT_HCA_TPT_OFFSET 0x0f0
1341 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1342 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1343 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1344 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1345 #define INIT_HCA_UAR_OFFSET 0x120
1346 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1347 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1348 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1349 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1350 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1351 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1352
1353 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1354 if (IS_ERR(mailbox))
1355 return PTR_ERR(mailbox);
1356 inbox = mailbox->buf;
1357
1358 memset(inbox, 0, INIT_HCA_IN_SIZE);
1359
1360 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
1361 MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
1362
1363 #if defined(__LITTLE_ENDIAN)
1364 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1365 #elif defined(__BIG_ENDIAN)
1366 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
1367 #else
1368 #error Host endianness not defined
1369 #endif
1370 /* Check port for UD address vector: */
1371 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
1372
1373 /* Enable IPoIB checksumming if we can: */
1374 if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM)
1375 *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3);
1376
1377 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1378
1379 /* QPC/EEC/CQC/EQC/RDB attributes */
1380
1381 MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1382 MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1383 MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
1384 MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
1385 MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1386 MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1387 MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1388 MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1389 MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
1390 MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
1391 MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1392 MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1393 MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
1394
1395 /* UD AV attributes */
1396
1397 /* multicast attributes */
1398
1399 MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1400 MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1401 MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
1402 MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1403
1404 /* TPT attributes */
1405
1406 MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
1407 if (!mthca_is_memfree(dev))
1408 MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
1409 MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1410 MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1411
1412 /* UAR attributes */
1413 {
1414 u8 uar_page_sz = PAGE_SHIFT - 12;
1415 MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1416 }
1417
1418 MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
1419
1420 if (mthca_is_memfree(dev)) {
1421 MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
1422 MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1423 MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
1424 }
1425
1426 err = mthca_cmd(dev, mailbox->dma, 0, 0,
1427 CMD_INIT_HCA, CMD_TIME_CLASS_D);
1428
1429 mthca_free_mailbox(dev, mailbox);
1430 return err;
1431 }
1432
1433 int mthca_INIT_IB(struct mthca_dev *dev,
1434 struct mthca_init_ib_param *param,
1435 int port)
1436 {
1437 struct mthca_mailbox *mailbox;
1438 u32 *inbox;
1439 int err;
1440 u32 flags;
1441
1442 #define INIT_IB_IN_SIZE 56
1443 #define INIT_IB_FLAGS_OFFSET 0x00
1444 #define INIT_IB_FLAG_SIG (1 << 18)
1445 #define INIT_IB_FLAG_NG (1 << 17)
1446 #define INIT_IB_FLAG_G0 (1 << 16)
1447 #define INIT_IB_VL_SHIFT 4
1448 #define INIT_IB_PORT_WIDTH_SHIFT 8
1449 #define INIT_IB_MTU_SHIFT 12
1450 #define INIT_IB_MAX_GID_OFFSET 0x06
1451 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1452 #define INIT_IB_GUID0_OFFSET 0x10
1453 #define INIT_IB_NODE_GUID_OFFSET 0x18
1454 #define INIT_IB_SI_GUID_OFFSET 0x20
1455
1456 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1457 if (IS_ERR(mailbox))
1458 return PTR_ERR(mailbox);
1459 inbox = mailbox->buf;
1460
1461 memset(inbox, 0, INIT_IB_IN_SIZE);
1462
1463 flags = 0;
1464 flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
1465 flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
1466 flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
1467 flags |= param->vl_cap << INIT_IB_VL_SHIFT;
1468 flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
1469 flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
1470 MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
1471
1472 MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
1473 MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
1474 MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
1475 MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
1476 MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
1477
1478 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
1479 CMD_TIME_CLASS_A);
1480
1481 mthca_free_mailbox(dev, mailbox);
1482 return err;
1483 }
1484
1485 int mthca_CLOSE_IB(struct mthca_dev *dev, int port)
1486 {
1487 return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A);
1488 }
1489
1490 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic)
1491 {
1492 return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C);
1493 }
1494
1495 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
1496 int port)
1497 {
1498 struct mthca_mailbox *mailbox;
1499 u32 *inbox;
1500 int err;
1501 u32 flags = 0;
1502
1503 #define SET_IB_IN_SIZE 0x40
1504 #define SET_IB_FLAGS_OFFSET 0x00
1505 #define SET_IB_FLAG_SIG (1 << 18)
1506 #define SET_IB_FLAG_RQK (1 << 0)
1507 #define SET_IB_CAP_MASK_OFFSET 0x04
1508 #define SET_IB_SI_GUID_OFFSET 0x08
1509
1510 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1511 if (IS_ERR(mailbox))
1512 return PTR_ERR(mailbox);
1513 inbox = mailbox->buf;
1514
1515 memset(inbox, 0, SET_IB_IN_SIZE);
1516
1517 flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
1518 flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
1519 MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
1520
1521 MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
1522 MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
1523
1524 err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
1525 CMD_TIME_CLASS_B);
1526
1527 mthca_free_mailbox(dev, mailbox);
1528 return err;
1529 }
1530
1531 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt)
1532 {
1533 return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt);
1534 }
1535
1536 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt)
1537 {
1538 struct mthca_mailbox *mailbox;
1539 __be64 *inbox;
1540 int err;
1541
1542 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1543 if (IS_ERR(mailbox))
1544 return PTR_ERR(mailbox);
1545 inbox = mailbox->buf;
1546
1547 inbox[0] = cpu_to_be64(virt);
1548 inbox[1] = cpu_to_be64(dma_addr);
1549
1550 err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
1551 CMD_TIME_CLASS_B);
1552
1553 mthca_free_mailbox(dev, mailbox);
1554
1555 if (!err)
1556 mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
1557 (unsigned long long) dma_addr, (unsigned long long) virt);
1558
1559 return err;
1560 }
1561
1562 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count)
1563 {
1564 mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
1565 page_count, (unsigned long long) virt);
1566
1567 return mthca_cmd(dev, virt, page_count, 0,
1568 CMD_UNMAP_ICM, CMD_TIME_CLASS_B);
1569 }
1570
1571 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm)
1572 {
1573 return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1);
1574 }
1575
1576 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev)
1577 {
1578 return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B);
1579 }
1580
1581 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages)
1582 {
1583 int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0,
1584 0, CMD_SET_ICM_SIZE, CMD_TIME_CLASS_A);
1585
1586 if (ret)
1587 return ret;
1588
1589 /*
1590 * Round up number of system pages needed in case
1591 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1592 */
1593 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
1594 (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
1595
1596 return 0;
1597 }
1598
1599 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1600 int mpt_index)
1601 {
1602 return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
1603 CMD_TIME_CLASS_B);
1604 }
1605
1606 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1607 int mpt_index)
1608 {
1609 return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
1610 !mailbox, CMD_HW2SW_MPT,
1611 CMD_TIME_CLASS_B);
1612 }
1613
1614 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1615 int num_mtt)
1616 {
1617 return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
1618 CMD_TIME_CLASS_B);
1619 }
1620
1621 int mthca_SYNC_TPT(struct mthca_dev *dev)
1622 {
1623 return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B);
1624 }
1625
1626 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
1627 int eq_num)
1628 {
1629 mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
1630 unmap ? "Clearing" : "Setting",
1631 (unsigned long long) event_mask, eq_num);
1632 return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
1633 0, CMD_MAP_EQ, CMD_TIME_CLASS_B);
1634 }
1635
1636 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1637 int eq_num)
1638 {
1639 return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
1640 CMD_TIME_CLASS_A);
1641 }
1642
1643 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1644 int eq_num)
1645 {
1646 return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
1647 CMD_HW2SW_EQ,
1648 CMD_TIME_CLASS_A);
1649 }
1650
1651 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1652 int cq_num)
1653 {
1654 return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
1655 CMD_TIME_CLASS_A);
1656 }
1657
1658 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1659 int cq_num)
1660 {
1661 return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
1662 CMD_HW2SW_CQ,
1663 CMD_TIME_CLASS_A);
1664 }
1665
1666 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size)
1667 {
1668 struct mthca_mailbox *mailbox;
1669 __be32 *inbox;
1670 int err;
1671
1672 #define RESIZE_CQ_IN_SIZE 0x40
1673 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1674 #define RESIZE_CQ_LKEY_OFFSET 0x1c
1675
1676 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1677 if (IS_ERR(mailbox))
1678 return PTR_ERR(mailbox);
1679 inbox = mailbox->buf;
1680
1681 memset(inbox, 0, RESIZE_CQ_IN_SIZE);
1682 /*
1683 * Leave start address fields zeroed out -- mthca assumes that
1684 * MRs for CQs always start at virtual address 0.
1685 */
1686 MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
1687 MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
1688
1689 err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
1690 CMD_TIME_CLASS_B);
1691
1692 mthca_free_mailbox(dev, mailbox);
1693 return err;
1694 }
1695
1696 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1697 int srq_num)
1698 {
1699 return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
1700 CMD_TIME_CLASS_A);
1701 }
1702
1703 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1704 int srq_num)
1705 {
1706 return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
1707 CMD_HW2SW_SRQ,
1708 CMD_TIME_CLASS_A);
1709 }
1710
1711 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
1712 struct mthca_mailbox *mailbox)
1713 {
1714 return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
1715 CMD_QUERY_SRQ, CMD_TIME_CLASS_A);
1716 }
1717
1718 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit)
1719 {
1720 return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
1721 CMD_TIME_CLASS_B);
1722 }
1723
1724 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
1725 enum ib_qp_state next, u32 num, int is_ee,
1726 struct mthca_mailbox *mailbox, u32 optmask)
1727 {
1728 static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
1729 [IB_QPS_RESET] = {
1730 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1731 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1732 [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
1733 },
1734 [IB_QPS_INIT] = {
1735 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1736 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1737 [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
1738 [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
1739 },
1740 [IB_QPS_RTR] = {
1741 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1742 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1743 [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
1744 },
1745 [IB_QPS_RTS] = {
1746 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1747 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1748 [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
1749 [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
1750 },
1751 [IB_QPS_SQD] = {
1752 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1753 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1754 [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
1755 [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
1756 },
1757 [IB_QPS_SQE] = {
1758 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1759 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1760 [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
1761 },
1762 [IB_QPS_ERR] = {
1763 [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
1764 [IB_QPS_ERR] = CMD_2ERR_QPEE,
1765 }
1766 };
1767
1768 u8 op_mod = 0;
1769 int my_mailbox = 0;
1770 int err;
1771
1772 if (op[cur][next] == CMD_ERR2RST_QPEE) {
1773 op_mod = 3; /* don't write outbox, any->reset */
1774
1775 /* For debugging */
1776 if (!mailbox) {
1777 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1778 if (!IS_ERR(mailbox)) {
1779 my_mailbox = 1;
1780 op_mod = 2; /* write outbox, any->reset */
1781 } else
1782 mailbox = NULL;
1783 }
1784
1785 err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
1786 (!!is_ee << 24) | num, op_mod,
1787 op[cur][next], CMD_TIME_CLASS_C);
1788
1789 if (0 && mailbox) {
1790 int i;
1791 mthca_dbg(dev, "Dumping QP context:\n");
1792 printk(" %08x\n", be32_to_cpup(mailbox->buf));
1793 for (i = 0; i < 0x100 / 4; ++i) {
1794 if (i % 8 == 0)
1795 printk("[%02x] ", i * 4);
1796 printk(" %08x",
1797 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1798 if ((i + 1) % 8 == 0)
1799 printk("\n");
1800 }
1801 }
1802
1803 if (my_mailbox)
1804 mthca_free_mailbox(dev, mailbox);
1805 } else {
1806 if (0) {
1807 int i;
1808 mthca_dbg(dev, "Dumping QP context:\n");
1809 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
1810 for (i = 0; i < 0x100 / 4; ++i) {
1811 if (i % 8 == 0)
1812 printk(" [%02x] ", i * 4);
1813 printk(" %08x",
1814 be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
1815 if ((i + 1) % 8 == 0)
1816 printk("\n");
1817 }
1818 }
1819
1820 err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
1821 op_mod, op[cur][next], CMD_TIME_CLASS_C);
1822 }
1823
1824 return err;
1825 }
1826
1827 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
1828 struct mthca_mailbox *mailbox)
1829 {
1830 return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
1831 CMD_QUERY_QPEE, CMD_TIME_CLASS_A);
1832 }
1833
1834 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn)
1835 {
1836 u8 op_mod;
1837
1838 switch (type) {
1839 case IB_QPT_SMI:
1840 op_mod = 0;
1841 break;
1842 case IB_QPT_GSI:
1843 op_mod = 1;
1844 break;
1845 case IB_QPT_RAW_IPV6:
1846 op_mod = 2;
1847 break;
1848 case IB_QPT_RAW_ETHERTYPE:
1849 op_mod = 3;
1850 break;
1851 default:
1852 return -EINVAL;
1853 }
1854
1855 return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
1856 CMD_TIME_CLASS_B);
1857 }
1858
1859 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
1860 int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
1861 void *in_mad, void *response_mad)
1862 {
1863 struct mthca_mailbox *inmailbox, *outmailbox;
1864 void *inbox;
1865 int err;
1866 u32 in_modifier = port;
1867 u8 op_modifier = 0;
1868
1869 #define MAD_IFC_BOX_SIZE 0x400
1870 #define MAD_IFC_MY_QPN_OFFSET 0x100
1871 #define MAD_IFC_RQPN_OFFSET 0x108
1872 #define MAD_IFC_SL_OFFSET 0x10c
1873 #define MAD_IFC_G_PATH_OFFSET 0x10d
1874 #define MAD_IFC_RLID_OFFSET 0x10e
1875 #define MAD_IFC_PKEY_OFFSET 0x112
1876 #define MAD_IFC_GRH_OFFSET 0x140
1877
1878 inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1879 if (IS_ERR(inmailbox))
1880 return PTR_ERR(inmailbox);
1881 inbox = inmailbox->buf;
1882
1883 outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
1884 if (IS_ERR(outmailbox)) {
1885 mthca_free_mailbox(dev, inmailbox);
1886 return PTR_ERR(outmailbox);
1887 }
1888
1889 memcpy(inbox, in_mad, 256);
1890
1891 /*
1892 * Key check traps can't be generated unless we have in_wc to
1893 * tell us where to send the trap.
1894 */
1895 if (ignore_mkey || !in_wc)
1896 op_modifier |= 0x1;
1897 if (ignore_bkey || !in_wc)
1898 op_modifier |= 0x2;
1899
1900 if (in_wc) {
1901 u8 val;
1902
1903 memset(inbox + 256, 0, 256);
1904
1905 MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET);
1906 MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
1907
1908 val = in_wc->sl << 4;
1909 MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
1910
1911 val = in_wc->dlid_path_bits |
1912 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
1913 MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET);
1914
1915 MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET);
1916 MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
1917
1918 if (in_grh)
1919 memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
1920
1921 op_modifier |= 0x4;
1922
1923 in_modifier |= in_wc->slid << 16;
1924 }
1925
1926 err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
1927 in_modifier, op_modifier,
1928 CMD_MAD_IFC, CMD_TIME_CLASS_C);
1929
1930 if (!err)
1931 memcpy(response_mad, outmailbox->buf, 256);
1932
1933 mthca_free_mailbox(dev, inmailbox);
1934 mthca_free_mailbox(dev, outmailbox);
1935 return err;
1936 }
1937
1938 int mthca_READ_MGM(struct mthca_dev *dev, int index,
1939 struct mthca_mailbox *mailbox)
1940 {
1941 return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
1942 CMD_READ_MGM, CMD_TIME_CLASS_A);
1943 }
1944
1945 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
1946 struct mthca_mailbox *mailbox)
1947 {
1948 return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
1949 CMD_TIME_CLASS_A);
1950 }
1951
1952 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
1953 u16 *hash)
1954 {
1955 u64 imm;
1956 int err;
1957
1958 err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
1959 CMD_TIME_CLASS_A);
1960
1961 *hash = imm;
1962 return err;
1963 }
1964
1965 int mthca_NOP(struct mthca_dev *dev)
1966 {
1967 return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100));
1968 }
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