2 * drxk_hard: DRX-K DVB-C/T demodulator driver
4 * Copyright (C) 2010-2011 Digital Devices GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <linux/version.h>
32 #include <asm/div64.h>
34 #include "dvb_frontend.h"
36 #include "drxk_hard.h"
38 static int PowerDownDVBT(struct drxk_state
*state
, bool setPowerMode
);
39 static int PowerDownQAM(struct drxk_state
*state
);
40 static int SetDVBTStandard(struct drxk_state
*state
,
41 enum OperationMode oMode
);
42 static int SetQAMStandard(struct drxk_state
*state
,
43 enum OperationMode oMode
);
44 static int SetQAM(struct drxk_state
*state
, u16 IntermediateFreqkHz
,
46 static int SetDVBTStandard(struct drxk_state
*state
,
47 enum OperationMode oMode
);
48 static int DVBTStart(struct drxk_state
*state
);
49 static int SetDVBT(struct drxk_state
*state
, u16 IntermediateFreqkHz
,
51 static int GetQAMLockStatus(struct drxk_state
*state
, u32
*pLockStatus
);
52 static int GetDVBTLockStatus(struct drxk_state
*state
, u32
*pLockStatus
);
53 static int SwitchAntennaToQAM(struct drxk_state
*state
);
54 static int SwitchAntennaToDVBT(struct drxk_state
*state
);
56 static bool IsDVBT(struct drxk_state
*state
)
58 return state
->m_OperationMode
== OM_DVBT
;
61 static bool IsQAM(struct drxk_state
*state
)
63 return state
->m_OperationMode
== OM_QAM_ITU_A
||
64 state
->m_OperationMode
== OM_QAM_ITU_B
||
65 state
->m_OperationMode
== OM_QAM_ITU_C
;
68 bool IsA1WithPatchCode(struct drxk_state
*state
)
70 return state
->m_DRXK_A1_PATCH_CODE
;
73 bool IsA1WithRomCode(struct drxk_state
*state
)
75 return state
->m_DRXK_A1_ROM_CODE
;
80 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
81 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
83 #define DEFAULT_MER_83 165
84 #define DEFAULT_MER_93 250
86 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
87 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
90 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
91 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
94 #ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
95 #define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
98 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
99 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
101 #ifndef DRXK_KI_RAGC_ATV
102 #define DRXK_KI_RAGC_ATV 4
104 #ifndef DRXK_KI_IAGC_ATV
105 #define DRXK_KI_IAGC_ATV 6
107 #ifndef DRXK_KI_DAGC_ATV
108 #define DRXK_KI_DAGC_ATV 7
111 #ifndef DRXK_KI_RAGC_QAM
112 #define DRXK_KI_RAGC_QAM 3
114 #ifndef DRXK_KI_IAGC_QAM
115 #define DRXK_KI_IAGC_QAM 4
117 #ifndef DRXK_KI_DAGC_QAM
118 #define DRXK_KI_DAGC_QAM 7
120 #ifndef DRXK_KI_RAGC_DVBT
121 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
123 #ifndef DRXK_KI_IAGC_DVBT
124 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
126 #ifndef DRXK_KI_DAGC_DVBT
127 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
130 #ifndef DRXK_AGC_DAC_OFFSET
131 #define DRXK_AGC_DAC_OFFSET (0x800)
134 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
135 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
138 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
139 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
142 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
143 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
146 #ifndef DRXK_QAM_SYMBOLRATE_MAX
147 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
150 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
151 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
152 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
153 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
154 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
155 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
156 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
157 #define DRXK_BL_ROM_OFFSET_UCODE 0
159 #define DRXK_BLC_TIMEOUT 100
161 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
162 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
164 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
166 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
167 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
170 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
171 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
172 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
173 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
174 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
176 static unsigned int debug
;
177 module_param(debug
, int, 0644);
178 MODULE_PARM_DESC(debug
, "enable debug messages");
180 #define dprintk(level, fmt, arg...) do { \
181 if (debug >= level) \
182 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
186 static inline u32
MulDiv32(u32 a
, u32 b
, u32 c
)
190 tmp64
= (u64
) a
* (u64
) b
;
196 inline u32
Frac28a(u32 a
, u32 c
)
202 R0
= (a
% c
) << 4; /* 32-28 == 4 shifts possible at max */
203 Q1
= a
/ c
; /* integer part, only the 4 least significant bits
204 will be visible in the result */
206 /* division using radix 16, 7 nibbles in the result */
207 for (i
= 0; i
< 7; i
++) {
208 Q1
= (Q1
<< 4) | (R0
/ c
);
218 static u32
Log10Times100(u32 x
)
220 static const u8 scale
= 15;
221 static const u8 indexWidth
= 5;
228 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
229 0 <= n < ((1<<INDEXWIDTH)+1)
232 static const u32 log2lut
[] = {
234 290941, /* 290941.300628 */
235 573196, /* 573196.476418 */
236 847269, /* 847269.179851 */
237 1113620, /* 1113620.489452 */
238 1372674, /* 1372673.576986 */
239 1624818, /* 1624817.752104 */
240 1870412, /* 1870411.981536 */
241 2109788, /* 2109787.962654 */
242 2343253, /* 2343252.817465 */
243 2571091, /* 2571091.461923 */
244 2793569, /* 2793568.696416 */
245 3010931, /* 3010931.055901 */
246 3223408, /* 3223408.452106 */
247 3431216, /* 3431215.635215 */
248 3634553, /* 3634553.498355 */
249 3833610, /* 3833610.244726 */
250 4028562, /* 4028562.434393 */
251 4219576, /* 4219575.925308 */
252 4406807, /* 4406806.721144 */
253 4590402, /* 4590401.736809 */
254 4770499, /* 4770499.491025 */
255 4947231, /* 4947230.734179 */
256 5120719, /* 5120719.018555 */
257 5291081, /* 5291081.217197 */
258 5458428, /* 5458427.996830 */
259 5622864, /* 5622864.249668 */
260 5784489, /* 5784489.488298 */
261 5943398, /* 5943398.207380 */
262 6099680, /* 6099680.215452 */
263 6253421, /* 6253420.939751 */
264 6404702, /* 6404701.706649 */
265 6553600, /* 6553600.000000 */
272 /* Scale x (normalize) */
273 /* computing y in log(x/y) = log(x) - log(y) */
274 if ((x
& ((0xffffffff) << (scale
+ 1))) == 0) {
275 for (k
= scale
; k
> 0; k
--) {
276 if (x
& (((u32
) 1) << scale
))
281 for (k
= scale
; k
< 31; k
++) {
282 if ((x
& (((u32
) (-1)) << (scale
+ 1))) == 0)
288 Now x has binary point between bit[scale] and bit[scale-1]
289 and 1.0 <= x < 2.0 */
291 /* correction for divison: log(x) = log(x/y)+log(y) */
292 y
= k
* ((((u32
) 1) << scale
) * 200);
294 /* remove integer part */
295 x
&= ((((u32
) 1) << scale
) - 1);
297 i
= (u8
) (x
>> (scale
- indexWidth
));
298 /* compute delta (x - a) */
299 d
= x
& ((((u32
) 1) << (scale
- indexWidth
)) - 1);
300 /* compute log, multiplication (d* (..)) must be within range ! */
302 ((d
* (log2lut
[i
+ 1] - log2lut
[i
])) >> (scale
- indexWidth
));
303 /* Conver to log10() */
304 y
/= 108853; /* (log2(10) << scale) */
312 /****************************************************************************/
313 /* I2C **********************************************************************/
314 /****************************************************************************/
316 static int i2c_read1(struct i2c_adapter
*adapter
, u8 adr
, u8
*val
)
318 struct i2c_msg msgs
[1] = { {.addr
= adr
, .flags
= I2C_M_RD
,
319 .buf
= val
, .len
= 1}
322 return i2c_transfer(adapter
, msgs
, 1);
325 static int i2c_write(struct i2c_adapter
*adap
, u8 adr
, u8
*data
, int len
)
328 struct i2c_msg msg
= {
329 .addr
= adr
, .flags
= 0, .buf
= data
, .len
= len
};
334 for (i
= 0; i
< len
; i
++)
335 printk(KERN_CONT
" %02x", data
[i
]);
336 printk(KERN_CONT
"\n");
338 status
= i2c_transfer(adap
, &msg
, 1);
339 if (status
>= 0 && status
!= 1)
343 printk(KERN_ERR
"drxk: i2c write error at addr 0x%02x\n", adr
);
348 static int i2c_read(struct i2c_adapter
*adap
,
349 u8 adr
, u8
*msg
, int len
, u8
*answ
, int alen
)
352 struct i2c_msg msgs
[2] = {
353 {.addr
= adr
, .flags
= 0,
354 .buf
= msg
, .len
= len
},
355 {.addr
= adr
, .flags
= I2C_M_RD
,
356 .buf
= answ
, .len
= alen
}
359 status
= i2c_transfer(adap
, msgs
, 2);
362 printk(KERN_CONT
": ERROR!\n");
366 printk(KERN_ERR
"drxk: i2c read error at addr 0x%02x\n", adr
);
371 dprintk(2, ": read from ");
372 for (i
= 0; i
< len
; i
++)
373 printk(KERN_CONT
" %02x", msg
[i
]);
374 printk(KERN_CONT
"Value = ");
375 for (i
= 0; i
< alen
; i
++)
376 printk(KERN_CONT
" %02x", answ
[i
]);
377 printk(KERN_CONT
"\n");
382 static int read16_flags(struct drxk_state
*state
, u32 reg
, u16
*data
, u8 flags
)
385 u8 adr
= state
->demod_address
, mm1
[4], mm2
[2], len
;
387 if (state
->single_master
)
390 if (DRXDAP_FASI_LONG_FORMAT(reg
) || (flags
!= 0)) {
391 mm1
[0] = (((reg
<< 1) & 0xFF) | 0x01);
392 mm1
[1] = ((reg
>> 16) & 0xFF);
393 mm1
[2] = ((reg
>> 24) & 0xFF) | flags
;
394 mm1
[3] = ((reg
>> 7) & 0xFF);
397 mm1
[0] = ((reg
<< 1) & 0xFF);
398 mm1
[1] = (((reg
>> 16) & 0x0F) | ((reg
>> 18) & 0xF0));
401 dprintk(2, "(0x%08x, 0x%02x)\n", reg
, flags
);
402 status
= i2c_read(state
->i2c
, adr
, mm1
, len
, mm2
, 2);
406 *data
= mm2
[0] | (mm2
[1] << 8);
411 static int read16(struct drxk_state
*state
, u32 reg
, u16
*data
)
413 return read16_flags(state
, reg
, data
, 0);
416 static int read32_flags(struct drxk_state
*state
, u32 reg
, u32
*data
, u8 flags
)
419 u8 adr
= state
->demod_address
, mm1
[4], mm2
[4], len
;
421 if (state
->single_master
)
424 if (DRXDAP_FASI_LONG_FORMAT(reg
) || (flags
!= 0)) {
425 mm1
[0] = (((reg
<< 1) & 0xFF) | 0x01);
426 mm1
[1] = ((reg
>> 16) & 0xFF);
427 mm1
[2] = ((reg
>> 24) & 0xFF) | flags
;
428 mm1
[3] = ((reg
>> 7) & 0xFF);
431 mm1
[0] = ((reg
<< 1) & 0xFF);
432 mm1
[1] = (((reg
>> 16) & 0x0F) | ((reg
>> 18) & 0xF0));
435 dprintk(2, "(0x%08x, 0x%02x)\n", reg
, flags
);
436 status
= i2c_read(state
->i2c
, adr
, mm1
, len
, mm2
, 4);
440 *data
= mm2
[0] | (mm2
[1] << 8) |
441 (mm2
[2] << 16) | (mm2
[3] << 24);
446 static int read32(struct drxk_state
*state
, u32 reg
, u32
*data
)
448 return read32_flags(state
, reg
, data
, 0);
451 static int write16_flags(struct drxk_state
*state
, u32 reg
, u16 data
, u8 flags
)
453 u8 adr
= state
->demod_address
, mm
[6], len
;
455 if (state
->single_master
)
457 if (DRXDAP_FASI_LONG_FORMAT(reg
) || (flags
!= 0)) {
458 mm
[0] = (((reg
<< 1) & 0xFF) | 0x01);
459 mm
[1] = ((reg
>> 16) & 0xFF);
460 mm
[2] = ((reg
>> 24) & 0xFF) | flags
;
461 mm
[3] = ((reg
>> 7) & 0xFF);
464 mm
[0] = ((reg
<< 1) & 0xFF);
465 mm
[1] = (((reg
>> 16) & 0x0F) | ((reg
>> 18) & 0xF0));
468 mm
[len
] = data
& 0xff;
469 mm
[len
+ 1] = (data
>> 8) & 0xff;
471 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg
, data
, flags
);
472 return i2c_write(state
->i2c
, adr
, mm
, len
+ 2);
475 static int write16(struct drxk_state
*state
, u32 reg
, u16 data
)
477 return write16_flags(state
, reg
, data
, 0);
480 static int write32_flags(struct drxk_state
*state
, u32 reg
, u32 data
, u8 flags
)
482 u8 adr
= state
->demod_address
, mm
[8], len
;
484 if (state
->single_master
)
486 if (DRXDAP_FASI_LONG_FORMAT(reg
) || (flags
!= 0)) {
487 mm
[0] = (((reg
<< 1) & 0xFF) | 0x01);
488 mm
[1] = ((reg
>> 16) & 0xFF);
489 mm
[2] = ((reg
>> 24) & 0xFF) | flags
;
490 mm
[3] = ((reg
>> 7) & 0xFF);
493 mm
[0] = ((reg
<< 1) & 0xFF);
494 mm
[1] = (((reg
>> 16) & 0x0F) | ((reg
>> 18) & 0xF0));
497 mm
[len
] = data
& 0xff;
498 mm
[len
+ 1] = (data
>> 8) & 0xff;
499 mm
[len
+ 2] = (data
>> 16) & 0xff;
500 mm
[len
+ 3] = (data
>> 24) & 0xff;
501 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg
, data
, flags
);
503 return i2c_write(state
->i2c
, adr
, mm
, len
+ 4);
506 static int write32(struct drxk_state
*state
, u32 reg
, u32 data
)
508 return write32_flags(state
, reg
, data
, 0);
511 static int write_block(struct drxk_state
*state
, u32 Address
,
512 const int BlockSize
, const u8 pBlock
[])
514 int status
= 0, BlkSize
= BlockSize
;
517 if (state
->single_master
)
520 while (BlkSize
> 0) {
521 int Chunk
= BlkSize
> state
->m_ChunkSize
?
522 state
->m_ChunkSize
: BlkSize
;
523 u8
*AdrBuf
= &state
->Chunk
[0];
526 if (DRXDAP_FASI_LONG_FORMAT(Address
) || (Flags
!= 0)) {
527 AdrBuf
[0] = (((Address
<< 1) & 0xFF) | 0x01);
528 AdrBuf
[1] = ((Address
>> 16) & 0xFF);
529 AdrBuf
[2] = ((Address
>> 24) & 0xFF);
530 AdrBuf
[3] = ((Address
>> 7) & 0xFF);
533 if (Chunk
== state
->m_ChunkSize
)
536 AdrBuf
[0] = ((Address
<< 1) & 0xFF);
537 AdrBuf
[1] = (((Address
>> 16) & 0x0F) |
538 ((Address
>> 18) & 0xF0));
541 memcpy(&state
->Chunk
[AdrLength
], pBlock
, Chunk
);
542 dprintk(2, "(0x%08x, 0x%02x)\n", Address
, Flags
);
546 for (i
= 0; i
< Chunk
; i
++)
547 printk(KERN_CONT
" %02x", pBlock
[i
]);
548 printk(KERN_CONT
"\n");
550 status
= i2c_write(state
->i2c
, state
->demod_address
,
551 &state
->Chunk
[0], Chunk
+ AdrLength
);
553 printk(KERN_ERR
"drxk: %s: i2c write error at addr 0x%02x\n",
558 Address
+= (Chunk
>> 1);
564 #ifndef DRXK_MAX_RETRIES_POWERUP
565 #define DRXK_MAX_RETRIES_POWERUP 20
568 int PowerUpDevice(struct drxk_state
*state
)
576 status
= i2c_read1(state
->i2c
, state
->demod_address
, &data
);
580 status
= i2c_write(state
->i2c
, state
->demod_address
,
586 status
= i2c_read1(state
->i2c
, state
->demod_address
,
588 } while (status
< 0 &&
589 (retryCount
< DRXK_MAX_RETRIES_POWERUP
));
590 if (status
< 0 && retryCount
>= DRXK_MAX_RETRIES_POWERUP
)
594 /* Make sure all clk domains are active */
595 status
= write16(state
, SIO_CC_PWD_MODE__A
, SIO_CC_PWD_MODE_LEVEL_NONE
);
598 status
= write16(state
, SIO_CC_UPDATE__A
, SIO_CC_UPDATE_KEY
);
601 /* Enable pll lock tests */
602 status
= write16(state
, SIO_CC_PLL_LOCK__A
, 1);
606 state
->m_currentPowerMode
= DRX_POWER_UP
;
610 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
616 static int init_state(struct drxk_state
*state
)
619 * FIXME: most (all?) of the values bellow should be moved into
620 * struct drxk_config, as they are probably board-specific
622 u32 ulVSBIfAgcMode
= DRXK_AGC_CTRL_AUTO
;
623 u32 ulVSBIfAgcOutputLevel
= 0;
624 u32 ulVSBIfAgcMinLevel
= 0;
625 u32 ulVSBIfAgcMaxLevel
= 0x7FFF;
626 u32 ulVSBIfAgcSpeed
= 3;
628 u32 ulVSBRfAgcMode
= DRXK_AGC_CTRL_AUTO
;
629 u32 ulVSBRfAgcOutputLevel
= 0;
630 u32 ulVSBRfAgcMinLevel
= 0;
631 u32 ulVSBRfAgcMaxLevel
= 0x7FFF;
632 u32 ulVSBRfAgcSpeed
= 3;
633 u32 ulVSBRfAgcTop
= 9500;
634 u32 ulVSBRfAgcCutOffCurrent
= 4000;
636 u32 ulATVIfAgcMode
= DRXK_AGC_CTRL_AUTO
;
637 u32 ulATVIfAgcOutputLevel
= 0;
638 u32 ulATVIfAgcMinLevel
= 0;
639 u32 ulATVIfAgcMaxLevel
= 0;
640 u32 ulATVIfAgcSpeed
= 3;
642 u32 ulATVRfAgcMode
= DRXK_AGC_CTRL_OFF
;
643 u32 ulATVRfAgcOutputLevel
= 0;
644 u32 ulATVRfAgcMinLevel
= 0;
645 u32 ulATVRfAgcMaxLevel
= 0;
646 u32 ulATVRfAgcTop
= 9500;
647 u32 ulATVRfAgcCutOffCurrent
= 4000;
648 u32 ulATVRfAgcSpeed
= 3;
650 u32 ulQual83
= DEFAULT_MER_83
;
651 u32 ulQual93
= DEFAULT_MER_93
;
653 u32 ulDVBTStaticTSClock
= 1;
654 u32 ulDVBCStaticTSClock
= 1;
656 u32 ulMpegLockTimeOut
= DEFAULT_DRXK_MPEG_LOCK_TIMEOUT
;
657 u32 ulDemodLockTimeOut
= DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT
;
659 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
660 /* io_pad_cfg_mode output mode is drive always */
661 /* io_pad_cfg_drive is set to power 2 (23 mA) */
662 u32 ulGPIOCfg
= 0x0113;
663 u32 ulSerialMode
= 1;
664 u32 ulInvertTSClock
= 0;
665 u32 ulTSDataStrength
= DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
;
666 u32 ulTSClockkStrength
= DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
;
667 u32 ulDVBTBitrate
= 50000000;
668 u32 ulDVBCBitrate
= DRXK_QAM_SYMBOLRATE_MAX
* 8;
670 u32 ulInsertRSByte
= 0;
677 state
->m_hasLNA
= false;
678 state
->m_hasDVBT
= false;
679 state
->m_hasDVBC
= false;
680 state
->m_hasATV
= false;
681 state
->m_hasOOB
= false;
682 state
->m_hasAudio
= false;
684 state
->m_ChunkSize
= 124;
686 state
->m_oscClockFreq
= 0;
687 state
->m_smartAntInverted
= false;
688 state
->m_bPDownOpenBridge
= false;
690 /* real system clock frequency in kHz */
691 state
->m_sysClockFreq
= 151875;
692 /* Timing div, 250ns/Psys */
693 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
694 state
->m_HICfgTimingDiv
= ((state
->m_sysClockFreq
/ 1000) *
695 HI_I2C_DELAY
) / 1000;
697 if (state
->m_HICfgTimingDiv
> SIO_HI_RA_RAM_PAR_2_CFG_DIV__M
)
698 state
->m_HICfgTimingDiv
= SIO_HI_RA_RAM_PAR_2_CFG_DIV__M
;
699 state
->m_HICfgWakeUpKey
= (state
->demod_address
<< 1);
700 /* port/bridge/power down ctrl */
701 state
->m_HICfgCtrl
= SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE
;
703 state
->m_bPowerDown
= (ulPowerDown
!= 0);
705 state
->m_DRXK_A1_PATCH_CODE
= false;
706 state
->m_DRXK_A1_ROM_CODE
= false;
707 state
->m_DRXK_A2_ROM_CODE
= false;
708 state
->m_DRXK_A3_ROM_CODE
= false;
709 state
->m_DRXK_A2_PATCH_CODE
= false;
710 state
->m_DRXK_A3_PATCH_CODE
= false;
712 /* Init AGC and PGA parameters */
714 state
->m_vsbIfAgcCfg
.ctrlMode
= (ulVSBIfAgcMode
);
715 state
->m_vsbIfAgcCfg
.outputLevel
= (ulVSBIfAgcOutputLevel
);
716 state
->m_vsbIfAgcCfg
.minOutputLevel
= (ulVSBIfAgcMinLevel
);
717 state
->m_vsbIfAgcCfg
.maxOutputLevel
= (ulVSBIfAgcMaxLevel
);
718 state
->m_vsbIfAgcCfg
.speed
= (ulVSBIfAgcSpeed
);
719 state
->m_vsbPgaCfg
= 140;
722 state
->m_vsbRfAgcCfg
.ctrlMode
= (ulVSBRfAgcMode
);
723 state
->m_vsbRfAgcCfg
.outputLevel
= (ulVSBRfAgcOutputLevel
);
724 state
->m_vsbRfAgcCfg
.minOutputLevel
= (ulVSBRfAgcMinLevel
);
725 state
->m_vsbRfAgcCfg
.maxOutputLevel
= (ulVSBRfAgcMaxLevel
);
726 state
->m_vsbRfAgcCfg
.speed
= (ulVSBRfAgcSpeed
);
727 state
->m_vsbRfAgcCfg
.top
= (ulVSBRfAgcTop
);
728 state
->m_vsbRfAgcCfg
.cutOffCurrent
= (ulVSBRfAgcCutOffCurrent
);
729 state
->m_vsbPreSawCfg
.reference
= 0x07;
730 state
->m_vsbPreSawCfg
.usePreSaw
= true;
732 state
->m_Quality83percent
= DEFAULT_MER_83
;
733 state
->m_Quality93percent
= DEFAULT_MER_93
;
734 if (ulQual93
<= 500 && ulQual83
< ulQual93
) {
735 state
->m_Quality83percent
= ulQual83
;
736 state
->m_Quality93percent
= ulQual93
;
740 state
->m_atvIfAgcCfg
.ctrlMode
= (ulATVIfAgcMode
);
741 state
->m_atvIfAgcCfg
.outputLevel
= (ulATVIfAgcOutputLevel
);
742 state
->m_atvIfAgcCfg
.minOutputLevel
= (ulATVIfAgcMinLevel
);
743 state
->m_atvIfAgcCfg
.maxOutputLevel
= (ulATVIfAgcMaxLevel
);
744 state
->m_atvIfAgcCfg
.speed
= (ulATVIfAgcSpeed
);
747 state
->m_atvRfAgcCfg
.ctrlMode
= (ulATVRfAgcMode
);
748 state
->m_atvRfAgcCfg
.outputLevel
= (ulATVRfAgcOutputLevel
);
749 state
->m_atvRfAgcCfg
.minOutputLevel
= (ulATVRfAgcMinLevel
);
750 state
->m_atvRfAgcCfg
.maxOutputLevel
= (ulATVRfAgcMaxLevel
);
751 state
->m_atvRfAgcCfg
.speed
= (ulATVRfAgcSpeed
);
752 state
->m_atvRfAgcCfg
.top
= (ulATVRfAgcTop
);
753 state
->m_atvRfAgcCfg
.cutOffCurrent
= (ulATVRfAgcCutOffCurrent
);
754 state
->m_atvPreSawCfg
.reference
= 0x04;
755 state
->m_atvPreSawCfg
.usePreSaw
= true;
759 state
->m_dvbtRfAgcCfg
.ctrlMode
= DRXK_AGC_CTRL_OFF
;
760 state
->m_dvbtRfAgcCfg
.outputLevel
= 0;
761 state
->m_dvbtRfAgcCfg
.minOutputLevel
= 0;
762 state
->m_dvbtRfAgcCfg
.maxOutputLevel
= 0xFFFF;
763 state
->m_dvbtRfAgcCfg
.top
= 0x2100;
764 state
->m_dvbtRfAgcCfg
.cutOffCurrent
= 4000;
765 state
->m_dvbtRfAgcCfg
.speed
= 1;
769 state
->m_dvbtIfAgcCfg
.ctrlMode
= DRXK_AGC_CTRL_AUTO
;
770 state
->m_dvbtIfAgcCfg
.outputLevel
= 0;
771 state
->m_dvbtIfAgcCfg
.minOutputLevel
= 0;
772 state
->m_dvbtIfAgcCfg
.maxOutputLevel
= 9000;
773 state
->m_dvbtIfAgcCfg
.top
= 13424;
774 state
->m_dvbtIfAgcCfg
.cutOffCurrent
= 0;
775 state
->m_dvbtIfAgcCfg
.speed
= 3;
776 state
->m_dvbtIfAgcCfg
.FastClipCtrlDelay
= 30;
777 state
->m_dvbtIfAgcCfg
.IngainTgtMax
= 30000;
778 /* state->m_dvbtPgaCfg = 140; */
780 state
->m_dvbtPreSawCfg
.reference
= 4;
781 state
->m_dvbtPreSawCfg
.usePreSaw
= false;
784 state
->m_qamRfAgcCfg
.ctrlMode
= DRXK_AGC_CTRL_OFF
;
785 state
->m_qamRfAgcCfg
.outputLevel
= 0;
786 state
->m_qamRfAgcCfg
.minOutputLevel
= 6023;
787 state
->m_qamRfAgcCfg
.maxOutputLevel
= 27000;
788 state
->m_qamRfAgcCfg
.top
= 0x2380;
789 state
->m_qamRfAgcCfg
.cutOffCurrent
= 4000;
790 state
->m_qamRfAgcCfg
.speed
= 3;
793 state
->m_qamIfAgcCfg
.ctrlMode
= DRXK_AGC_CTRL_AUTO
;
794 state
->m_qamIfAgcCfg
.outputLevel
= 0;
795 state
->m_qamIfAgcCfg
.minOutputLevel
= 0;
796 state
->m_qamIfAgcCfg
.maxOutputLevel
= 9000;
797 state
->m_qamIfAgcCfg
.top
= 0x0511;
798 state
->m_qamIfAgcCfg
.cutOffCurrent
= 0;
799 state
->m_qamIfAgcCfg
.speed
= 3;
800 state
->m_qamIfAgcCfg
.IngainTgtMax
= 5119;
801 state
->m_qamIfAgcCfg
.FastClipCtrlDelay
= 50;
803 state
->m_qamPgaCfg
= 140;
804 state
->m_qamPreSawCfg
.reference
= 4;
805 state
->m_qamPreSawCfg
.usePreSaw
= false;
807 state
->m_OperationMode
= OM_NONE
;
808 state
->m_DrxkState
= DRXK_UNINITIALIZED
;
810 /* MPEG output configuration */
811 state
->m_enableMPEGOutput
= true; /* If TRUE; enable MPEG ouput */
812 state
->m_insertRSByte
= false; /* If TRUE; insert RS byte */
813 state
->m_enableParallel
= true; /* If TRUE;
814 parallel out otherwise serial */
815 state
->m_invertDATA
= false; /* If TRUE; invert DATA signals */
816 state
->m_invertERR
= false; /* If TRUE; invert ERR signal */
817 state
->m_invertSTR
= false; /* If TRUE; invert STR signals */
818 state
->m_invertVAL
= false; /* If TRUE; invert VAL signals */
819 state
->m_invertCLK
= (ulInvertTSClock
!= 0); /* If TRUE; invert CLK signals */
820 state
->m_DVBTStaticCLK
= (ulDVBTStaticTSClock
!= 0);
821 state
->m_DVBCStaticCLK
= (ulDVBCStaticTSClock
!= 0);
822 /* If TRUE; static MPEG clockrate will be used;
823 otherwise clockrate will adapt to the bitrate of the TS */
825 state
->m_DVBTBitrate
= ulDVBTBitrate
;
826 state
->m_DVBCBitrate
= ulDVBCBitrate
;
828 state
->m_TSDataStrength
= (ulTSDataStrength
& 0x07);
829 state
->m_TSClockkStrength
= (ulTSClockkStrength
& 0x07);
831 /* Maximum bitrate in b/s in case static clockrate is selected */
832 state
->m_mpegTsStaticBitrate
= 19392658;
833 state
->m_disableTEIhandling
= false;
836 state
->m_insertRSByte
= true;
838 state
->m_MpegLockTimeOut
= DEFAULT_DRXK_MPEG_LOCK_TIMEOUT
;
839 if (ulMpegLockTimeOut
< 10000)
840 state
->m_MpegLockTimeOut
= ulMpegLockTimeOut
;
841 state
->m_DemodLockTimeOut
= DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT
;
842 if (ulDemodLockTimeOut
< 10000)
843 state
->m_DemodLockTimeOut
= ulDemodLockTimeOut
;
846 state
->m_Constellation
= DRX_CONSTELLATION_AUTO
;
847 state
->m_qamInterleaveMode
= DRXK_QAM_I12_J17
;
848 state
->m_fecRsPlen
= 204 * 8; /* fecRsPlen annex A */
849 state
->m_fecRsPrescale
= 1;
851 state
->m_sqiSpeed
= DRXK_DVBT_SQI_SPEED_MEDIUM
;
852 state
->m_agcFastClipCtrlDelay
= 0;
854 state
->m_GPIOCfg
= (ulGPIOCfg
);
856 state
->m_bPowerDown
= false;
857 state
->m_currentPowerMode
= DRX_POWER_DOWN
;
859 state
->m_enableParallel
= (ulSerialMode
== 0);
861 state
->m_rfmirror
= (ulRfMirror
== 0);
862 state
->m_IfAgcPol
= false;
866 static int DRXX_Open(struct drxk_state
*state
)
874 /* stop lock indicator process */
875 status
= write16(state
, SCU_RAM_GPIO__A
, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE
);
878 /* Check device id */
879 status
= read16(state
, SIO_TOP_COMM_KEY__A
, &key
);
882 status
= write16(state
, SIO_TOP_COMM_KEY__A
, SIO_TOP_COMM_KEY_KEY
);
885 status
= read32(state
, SIO_TOP_JTAGID_LO__A
, &jtag
);
888 status
= read16(state
, SIO_PDR_UIO_IN_HI__A
, &bid
);
891 status
= write16(state
, SIO_TOP_COMM_KEY__A
, key
);
894 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
898 static int GetDeviceCapabilities(struct drxk_state
*state
)
900 u16 sioPdrOhwCfg
= 0;
901 u32 sioTopJtagidLo
= 0;
903 const char *spin
= "";
908 /* stop lock indicator process */
909 status
= write16(state
, SCU_RAM_GPIO__A
, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE
);
912 status
= write16(state
, SIO_TOP_COMM_KEY__A
, 0xFABA);
915 status
= read16(state
, SIO_PDR_OHW_CFG__A
, &sioPdrOhwCfg
);
918 status
= write16(state
, SIO_TOP_COMM_KEY__A
, 0x0000);
922 switch ((sioPdrOhwCfg
& SIO_PDR_OHW_CFG_FREF_SEL__M
)) {
924 /* ignore (bypass ?) */
928 state
->m_oscClockFreq
= 27000;
932 state
->m_oscClockFreq
= 20250;
936 state
->m_oscClockFreq
= 20250;
939 printk(KERN_ERR
"drxk: Clock Frequency is unkonwn\n");
943 Determine device capabilities
946 status
= read32(state
, SIO_TOP_JTAGID_LO__A
, &sioTopJtagidLo
);
950 switch ((sioTopJtagidLo
>> 29) & 0xF) {
952 state
->m_deviceSpin
= DRXK_SPIN_A1
;
956 state
->m_deviceSpin
= DRXK_SPIN_A2
;
960 state
->m_deviceSpin
= DRXK_SPIN_A3
;
964 state
->m_deviceSpin
= DRXK_SPIN_UNKNOWN
;
966 printk(KERN_ERR
"drxk: Spin unknown\n");
969 switch ((sioTopJtagidLo
>> 12) & 0xFF) {
971 /* typeId = DRX3913K_TYPE_ID */
972 state
->m_hasLNA
= false;
973 state
->m_hasOOB
= false;
974 state
->m_hasATV
= false;
975 state
->m_hasAudio
= false;
976 state
->m_hasDVBT
= true;
977 state
->m_hasDVBC
= true;
978 state
->m_hasSAWSW
= true;
979 state
->m_hasGPIO2
= false;
980 state
->m_hasGPIO1
= false;
981 state
->m_hasIRQN
= false;
984 /* typeId = DRX3915K_TYPE_ID */
985 state
->m_hasLNA
= false;
986 state
->m_hasOOB
= false;
987 state
->m_hasATV
= true;
988 state
->m_hasAudio
= false;
989 state
->m_hasDVBT
= true;
990 state
->m_hasDVBC
= false;
991 state
->m_hasSAWSW
= true;
992 state
->m_hasGPIO2
= true;
993 state
->m_hasGPIO1
= true;
994 state
->m_hasIRQN
= false;
997 /* typeId = DRX3916K_TYPE_ID */
998 state
->m_hasLNA
= false;
999 state
->m_hasOOB
= false;
1000 state
->m_hasATV
= true;
1001 state
->m_hasAudio
= false;
1002 state
->m_hasDVBT
= true;
1003 state
->m_hasDVBC
= false;
1004 state
->m_hasSAWSW
= true;
1005 state
->m_hasGPIO2
= true;
1006 state
->m_hasGPIO1
= true;
1007 state
->m_hasIRQN
= false;
1010 /* typeId = DRX3918K_TYPE_ID */
1011 state
->m_hasLNA
= false;
1012 state
->m_hasOOB
= false;
1013 state
->m_hasATV
= true;
1014 state
->m_hasAudio
= true;
1015 state
->m_hasDVBT
= true;
1016 state
->m_hasDVBC
= false;
1017 state
->m_hasSAWSW
= true;
1018 state
->m_hasGPIO2
= true;
1019 state
->m_hasGPIO1
= true;
1020 state
->m_hasIRQN
= false;
1023 /* typeId = DRX3921K_TYPE_ID */
1024 state
->m_hasLNA
= false;
1025 state
->m_hasOOB
= false;
1026 state
->m_hasATV
= true;
1027 state
->m_hasAudio
= true;
1028 state
->m_hasDVBT
= true;
1029 state
->m_hasDVBC
= true;
1030 state
->m_hasSAWSW
= true;
1031 state
->m_hasGPIO2
= true;
1032 state
->m_hasGPIO1
= true;
1033 state
->m_hasIRQN
= false;
1036 /* typeId = DRX3923K_TYPE_ID */
1037 state
->m_hasLNA
= false;
1038 state
->m_hasOOB
= false;
1039 state
->m_hasATV
= true;
1040 state
->m_hasAudio
= true;
1041 state
->m_hasDVBT
= true;
1042 state
->m_hasDVBC
= true;
1043 state
->m_hasSAWSW
= true;
1044 state
->m_hasGPIO2
= true;
1045 state
->m_hasGPIO1
= true;
1046 state
->m_hasIRQN
= false;
1049 /* typeId = DRX3925K_TYPE_ID */
1050 state
->m_hasLNA
= false;
1051 state
->m_hasOOB
= false;
1052 state
->m_hasATV
= true;
1053 state
->m_hasAudio
= true;
1054 state
->m_hasDVBT
= true;
1055 state
->m_hasDVBC
= true;
1056 state
->m_hasSAWSW
= true;
1057 state
->m_hasGPIO2
= true;
1058 state
->m_hasGPIO1
= true;
1059 state
->m_hasIRQN
= false;
1062 /* typeId = DRX3926K_TYPE_ID */
1063 state
->m_hasLNA
= false;
1064 state
->m_hasOOB
= false;
1065 state
->m_hasATV
= true;
1066 state
->m_hasAudio
= false;
1067 state
->m_hasDVBT
= true;
1068 state
->m_hasDVBC
= true;
1069 state
->m_hasSAWSW
= true;
1070 state
->m_hasGPIO2
= true;
1071 state
->m_hasGPIO1
= true;
1072 state
->m_hasIRQN
= false;
1075 printk(KERN_ERR
"drxk: DeviceID 0x%02x not supported\n",
1076 ((sioTopJtagidLo
>> 12) & 0xFF));
1082 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1083 ((sioTopJtagidLo
>> 12) & 0xFF), spin
,
1084 state
->m_oscClockFreq
/ 1000,
1085 state
->m_oscClockFreq
% 1000);
1089 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1095 static int HI_Command(struct drxk_state
*state
, u16 cmd
, u16
*pResult
)
1103 status
= write16(state
, SIO_HI_RA_RAM_CMD__A
, cmd
);
1106 if (cmd
== SIO_HI_RA_RAM_CMD_RESET
)
1110 (bool) ((cmd
== SIO_HI_RA_RAM_CMD_CONFIG
) &&
1111 ((state
->m_HICfgCtrl
) &
1112 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M
) ==
1113 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ
);
1114 if (powerdown_cmd
== false) {
1115 /* Wait until command rdy */
1122 status
= read16(state
, SIO_HI_RA_RAM_CMD__A
,
1124 } while ((status
< 0) && (retryCount
< DRXK_MAX_RETRIES
)
1128 status
= read16(state
, SIO_HI_RA_RAM_RES__A
, pResult
);
1132 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1137 static int HI_CfgCommand(struct drxk_state
*state
)
1143 mutex_lock(&state
->mutex
);
1145 status
= write16(state
, SIO_HI_RA_RAM_PAR_6__A
, state
->m_HICfgTimeout
);
1148 status
= write16(state
, SIO_HI_RA_RAM_PAR_5__A
, state
->m_HICfgCtrl
);
1151 status
= write16(state
, SIO_HI_RA_RAM_PAR_4__A
, state
->m_HICfgWakeUpKey
);
1154 status
= write16(state
, SIO_HI_RA_RAM_PAR_3__A
, state
->m_HICfgBridgeDelay
);
1157 status
= write16(state
, SIO_HI_RA_RAM_PAR_2__A
, state
->m_HICfgTimingDiv
);
1160 status
= write16(state
, SIO_HI_RA_RAM_PAR_1__A
, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY
);
1163 status
= HI_Command(state
, SIO_HI_RA_RAM_CMD_CONFIG
, 0);
1167 state
->m_HICfgCtrl
&= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ
;
1169 mutex_unlock(&state
->mutex
);
1171 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1175 static int InitHI(struct drxk_state
*state
)
1179 state
->m_HICfgWakeUpKey
= (state
->demod_address
<< 1);
1180 state
->m_HICfgTimeout
= 0x96FF;
1181 /* port/bridge/power down ctrl */
1182 state
->m_HICfgCtrl
= SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE
;
1184 return HI_CfgCommand(state
);
1187 static int MPEGTSConfigurePins(struct drxk_state
*state
, bool mpegEnable
)
1190 u16 sioPdrMclkCfg
= 0;
1191 u16 sioPdrMdxCfg
= 0;
1195 /* stop lock indicator process */
1196 status
= write16(state
, SCU_RAM_GPIO__A
, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE
);
1200 /* MPEG TS pad configuration */
1201 status
= write16(state
, SIO_TOP_COMM_KEY__A
, 0xFABA);
1205 if (mpegEnable
== false) {
1206 /* Set MPEG TS pads to inputmode */
1207 status
= write16(state
, SIO_PDR_MSTRT_CFG__A
, 0x0000);
1210 status
= write16(state
, SIO_PDR_MERR_CFG__A
, 0x0000);
1213 status
= write16(state
, SIO_PDR_MCLK_CFG__A
, 0x0000);
1216 status
= write16(state
, SIO_PDR_MVAL_CFG__A
, 0x0000);
1219 status
= write16(state
, SIO_PDR_MD0_CFG__A
, 0x0000);
1222 status
= write16(state
, SIO_PDR_MD1_CFG__A
, 0x0000);
1225 status
= write16(state
, SIO_PDR_MD2_CFG__A
, 0x0000);
1228 status
= write16(state
, SIO_PDR_MD3_CFG__A
, 0x0000);
1231 status
= write16(state
, SIO_PDR_MD4_CFG__A
, 0x0000);
1234 status
= write16(state
, SIO_PDR_MD5_CFG__A
, 0x0000);
1237 status
= write16(state
, SIO_PDR_MD6_CFG__A
, 0x0000);
1240 status
= write16(state
, SIO_PDR_MD7_CFG__A
, 0x0000);
1244 /* Enable MPEG output */
1246 ((state
->m_TSDataStrength
<<
1247 SIO_PDR_MD0_CFG_DRIVE__B
) | 0x0003);
1248 sioPdrMclkCfg
= ((state
->m_TSClockkStrength
<<
1249 SIO_PDR_MCLK_CFG_DRIVE__B
) |
1252 status
= write16(state
, SIO_PDR_MSTRT_CFG__A
, sioPdrMdxCfg
);
1255 status
= write16(state
, SIO_PDR_MERR_CFG__A
, 0x0000); /* Disable */
1258 status
= write16(state
, SIO_PDR_MVAL_CFG__A
, 0x0000); /* Disable */
1261 if (state
->m_enableParallel
== true) {
1262 /* paralel -> enable MD1 to MD7 */
1263 status
= write16(state
, SIO_PDR_MD1_CFG__A
, sioPdrMdxCfg
);
1266 status
= write16(state
, SIO_PDR_MD2_CFG__A
, sioPdrMdxCfg
);
1269 status
= write16(state
, SIO_PDR_MD3_CFG__A
, sioPdrMdxCfg
);
1272 status
= write16(state
, SIO_PDR_MD4_CFG__A
, sioPdrMdxCfg
);
1275 status
= write16(state
, SIO_PDR_MD5_CFG__A
, sioPdrMdxCfg
);
1278 status
= write16(state
, SIO_PDR_MD6_CFG__A
, sioPdrMdxCfg
);
1281 status
= write16(state
, SIO_PDR_MD7_CFG__A
, sioPdrMdxCfg
);
1285 sioPdrMdxCfg
= ((state
->m_TSDataStrength
<<
1286 SIO_PDR_MD0_CFG_DRIVE__B
)
1288 /* serial -> disable MD1 to MD7 */
1289 status
= write16(state
, SIO_PDR_MD1_CFG__A
, 0x0000);
1292 status
= write16(state
, SIO_PDR_MD2_CFG__A
, 0x0000);
1295 status
= write16(state
, SIO_PDR_MD3_CFG__A
, 0x0000);
1298 status
= write16(state
, SIO_PDR_MD4_CFG__A
, 0x0000);
1301 status
= write16(state
, SIO_PDR_MD5_CFG__A
, 0x0000);
1304 status
= write16(state
, SIO_PDR_MD6_CFG__A
, 0x0000);
1307 status
= write16(state
, SIO_PDR_MD7_CFG__A
, 0x0000);
1311 status
= write16(state
, SIO_PDR_MCLK_CFG__A
, sioPdrMclkCfg
);
1314 status
= write16(state
, SIO_PDR_MD0_CFG__A
, sioPdrMdxCfg
);
1318 /* Enable MB output over MPEG pads and ctl input */
1319 status
= write16(state
, SIO_PDR_MON_CFG__A
, 0x0000);
1322 /* Write nomagic word to enable pdr reg write */
1323 status
= write16(state
, SIO_TOP_COMM_KEY__A
, 0x0000);
1326 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1330 static int MPEGTSDisable(struct drxk_state
*state
)
1334 return MPEGTSConfigurePins(state
, false);
1337 static int BLChainCmd(struct drxk_state
*state
,
1338 u16 romOffset
, u16 nrOfElements
, u32 timeOut
)
1345 mutex_lock(&state
->mutex
);
1346 status
= write16(state
, SIO_BL_MODE__A
, SIO_BL_MODE_CHAIN
);
1349 status
= write16(state
, SIO_BL_CHAIN_ADDR__A
, romOffset
);
1352 status
= write16(state
, SIO_BL_CHAIN_LEN__A
, nrOfElements
);
1355 status
= write16(state
, SIO_BL_ENABLE__A
, SIO_BL_ENABLE_ON
);
1359 end
= jiffies
+ msecs_to_jiffies(timeOut
);
1362 status
= read16(state
, SIO_BL_STATUS__A
, &blStatus
);
1365 } while ((blStatus
== 0x1) &&
1366 ((time_is_after_jiffies(end
))));
1368 if (blStatus
== 0x1) {
1369 printk(KERN_ERR
"drxk: SIO not ready\n");
1375 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1377 mutex_unlock(&state
->mutex
);
1382 static int DownloadMicrocode(struct drxk_state
*state
,
1383 const u8 pMCImage
[], u32 Length
)
1385 const u8
*pSrc
= pMCImage
;
1398 /* down the drain (we don care about MAGIC_WORD) */
1399 Drain
= (pSrc
[0] << 8) | pSrc
[1];
1400 pSrc
+= sizeof(u16
);
1401 offset
+= sizeof(u16
);
1402 nBlocks
= (pSrc
[0] << 8) | pSrc
[1];
1403 pSrc
+= sizeof(u16
);
1404 offset
+= sizeof(u16
);
1406 for (i
= 0; i
< nBlocks
; i
+= 1) {
1407 Address
= (pSrc
[0] << 24) | (pSrc
[1] << 16) |
1408 (pSrc
[2] << 8) | pSrc
[3];
1409 pSrc
+= sizeof(u32
);
1410 offset
+= sizeof(u32
);
1412 BlockSize
= ((pSrc
[0] << 8) | pSrc
[1]) * sizeof(u16
);
1413 pSrc
+= sizeof(u16
);
1414 offset
+= sizeof(u16
);
1416 Flags
= (pSrc
[0] << 8) | pSrc
[1];
1417 pSrc
+= sizeof(u16
);
1418 offset
+= sizeof(u16
);
1420 BlockCRC
= (pSrc
[0] << 8) | pSrc
[1];
1421 pSrc
+= sizeof(u16
);
1422 offset
+= sizeof(u16
);
1424 if (offset
+ BlockSize
> Length
) {
1425 printk(KERN_ERR
"drxk: Firmware is corrupted.\n");
1429 status
= write_block(state
, Address
, BlockSize
, pSrc
);
1431 printk(KERN_ERR
"drxk: Error %d while loading firmware\n", status
);
1435 offset
+= BlockSize
;
1440 static int DVBTEnableOFDMTokenRing(struct drxk_state
*state
, bool enable
)
1444 u16 desiredCtrl
= SIO_OFDM_SH_OFDM_RING_ENABLE_ON
;
1445 u16 desiredStatus
= SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED
;
1450 if (enable
== false) {
1451 desiredCtrl
= SIO_OFDM_SH_OFDM_RING_ENABLE_OFF
;
1452 desiredStatus
= SIO_OFDM_SH_OFDM_RING_STATUS_DOWN
;
1455 status
= read16(state
, SIO_OFDM_SH_OFDM_RING_STATUS__A
, &data
);
1456 if (status
>= 0 && data
== desiredStatus
) {
1457 /* tokenring already has correct status */
1460 /* Disable/enable dvbt tokenring bridge */
1461 status
= write16(state
, SIO_OFDM_SH_OFDM_RING_ENABLE__A
, desiredCtrl
);
1463 end
= jiffies
+ msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
);
1465 status
= read16(state
, SIO_OFDM_SH_OFDM_RING_STATUS__A
, &data
);
1466 if ((status
>= 0 && data
== desiredStatus
) || time_is_after_jiffies(end
))
1470 if (data
!= desiredStatus
) {
1471 printk(KERN_ERR
"drxk: SIO not ready\n");
1477 static int MPEGTSStop(struct drxk_state
*state
)
1480 u16 fecOcSncMode
= 0;
1481 u16 fecOcIprMode
= 0;
1485 /* Gracefull shutdown (byte boundaries) */
1486 status
= read16(state
, FEC_OC_SNC_MODE__A
, &fecOcSncMode
);
1489 fecOcSncMode
|= FEC_OC_SNC_MODE_SHUTDOWN__M
;
1490 status
= write16(state
, FEC_OC_SNC_MODE__A
, fecOcSncMode
);
1494 /* Suppress MCLK during absence of data */
1495 status
= read16(state
, FEC_OC_IPR_MODE__A
, &fecOcIprMode
);
1498 fecOcIprMode
|= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M
;
1499 status
= write16(state
, FEC_OC_IPR_MODE__A
, fecOcIprMode
);
1503 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1508 static int scu_command(struct drxk_state
*state
,
1509 u16 cmd
, u8 parameterLen
,
1510 u16
*parameter
, u8 resultLen
, u16
*result
)
1512 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1513 #error DRXK register mapping no longer compatible with this routine!
1516 int status
= -EINVAL
;
1525 if ((cmd
== 0) || ((parameterLen
> 0) && (parameter
== NULL
)) ||
1526 ((resultLen
> 0) && (result
== NULL
)))
1529 mutex_lock(&state
->mutex
);
1531 /* assume that the command register is ready
1532 since it is checked afterwards */
1533 for (ii
= parameterLen
- 1; ii
>= 0; ii
-= 1) {
1534 buffer
[cnt
++] = (parameter
[ii
] & 0xFF);
1535 buffer
[cnt
++] = ((parameter
[ii
] >> 8) & 0xFF);
1537 buffer
[cnt
++] = (cmd
& 0xFF);
1538 buffer
[cnt
++] = ((cmd
>> 8) & 0xFF);
1540 write_block(state
, SCU_RAM_PARAM_0__A
-
1541 (parameterLen
- 1), cnt
, buffer
);
1542 /* Wait until SCU has processed command */
1543 end
= jiffies
+ msecs_to_jiffies(DRXK_MAX_WAITTIME
);
1546 status
= read16(state
, SCU_RAM_COMMAND__A
, &curCmd
);
1549 } while (!(curCmd
== DRX_SCU_READY
) && (time_is_after_jiffies(end
)));
1550 if (curCmd
!= DRX_SCU_READY
) {
1551 printk(KERN_ERR
"drxk: SCU not ready\n");
1556 if ((resultLen
> 0) && (result
!= NULL
)) {
1560 for (ii
= resultLen
- 1; ii
>= 0; ii
-= 1) {
1561 status
= read16(state
, SCU_RAM_PARAM_0__A
- ii
, &result
[ii
]);
1566 /* Check if an error was reported by SCU */
1567 err
= (s16
)result
[0];
1571 /* check for the known error codes */
1573 case SCU_RESULT_UNKCMD
:
1574 p
= "SCU_RESULT_UNKCMD";
1576 case SCU_RESULT_UNKSTD
:
1577 p
= "SCU_RESULT_UNKSTD";
1579 case SCU_RESULT_SIZE
:
1580 p
= "SCU_RESULT_SIZE";
1582 case SCU_RESULT_INVPAR
:
1583 p
= "SCU_RESULT_INVPAR";
1585 default: /* Other negative values are errors */
1586 sprintf(errname
, "ERROR: %d\n", err
);
1589 printk(KERN_ERR
"drxk: %s while sending cmd 0x%04x with params:", p
, cmd
);
1590 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE
, buffer
, cnt
);
1597 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1599 mutex_unlock(&state
->mutex
);
1603 static int SetIqmAf(struct drxk_state
*state
, bool active
)
1611 status
= read16(state
, IQM_AF_STDBY__A
, &data
);
1616 data
|= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1617 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1618 | IQM_AF_STDBY_STDBY_PD_STANDBY
1619 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1620 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY
);
1622 data
&= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY
)
1623 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY
)
1624 & (~IQM_AF_STDBY_STDBY_PD_STANDBY
)
1625 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
)
1626 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY
)
1629 status
= write16(state
, IQM_AF_STDBY__A
, data
);
1633 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1637 static int CtrlPowerMode(struct drxk_state
*state
, enum DRXPowerMode
*mode
)
1640 u16 sioCcPwdMode
= 0;
1644 /* Check arguments */
1650 sioCcPwdMode
= SIO_CC_PWD_MODE_LEVEL_NONE
;
1652 case DRXK_POWER_DOWN_OFDM
:
1653 sioCcPwdMode
= SIO_CC_PWD_MODE_LEVEL_OFDM
;
1655 case DRXK_POWER_DOWN_CORE
:
1656 sioCcPwdMode
= SIO_CC_PWD_MODE_LEVEL_CLOCK
;
1658 case DRXK_POWER_DOWN_PLL
:
1659 sioCcPwdMode
= SIO_CC_PWD_MODE_LEVEL_PLL
;
1661 case DRX_POWER_DOWN
:
1662 sioCcPwdMode
= SIO_CC_PWD_MODE_LEVEL_OSC
;
1665 /* Unknow sleep mode */
1669 /* If already in requested power mode, do nothing */
1670 if (state
->m_currentPowerMode
== *mode
)
1673 /* For next steps make sure to start from DRX_POWER_UP mode */
1674 if (state
->m_currentPowerMode
!= DRX_POWER_UP
) {
1675 status
= PowerUpDevice(state
);
1678 status
= DVBTEnableOFDMTokenRing(state
, true);
1683 if (*mode
== DRX_POWER_UP
) {
1684 /* Restore analog & pin configuartion */
1686 /* Power down to requested mode */
1687 /* Backup some register settings */
1688 /* Set pins with possible pull-ups connected
1689 to them in input mode */
1690 /* Analog power down */
1691 /* ADC power down */
1692 /* Power down device */
1693 /* stop all comm_exec */
1694 /* Stop and power down previous standard */
1695 switch (state
->m_OperationMode
) {
1697 status
= MPEGTSStop(state
);
1700 status
= PowerDownDVBT(state
, false);
1706 status
= MPEGTSStop(state
);
1709 status
= PowerDownQAM(state
);
1716 status
= DVBTEnableOFDMTokenRing(state
, false);
1719 status
= write16(state
, SIO_CC_PWD_MODE__A
, sioCcPwdMode
);
1722 status
= write16(state
, SIO_CC_UPDATE__A
, SIO_CC_UPDATE_KEY
);
1726 if (*mode
!= DRXK_POWER_DOWN_OFDM
) {
1727 state
->m_HICfgCtrl
|=
1728 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ
;
1729 status
= HI_CfgCommand(state
);
1734 state
->m_currentPowerMode
= *mode
;
1738 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1743 static int PowerDownDVBT(struct drxk_state
*state
, bool setPowerMode
)
1745 enum DRXPowerMode powerMode
= DRXK_POWER_DOWN_OFDM
;
1752 status
= read16(state
, SCU_COMM_EXEC__A
, &data
);
1755 if (data
== SCU_COMM_EXEC_ACTIVE
) {
1756 /* Send OFDM stop command */
1757 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_STOP
, 0, NULL
, 1, &cmdResult
);
1760 /* Send OFDM reset command */
1761 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_RESET
, 0, NULL
, 1, &cmdResult
);
1766 /* Reset datapath for OFDM, processors first */
1767 status
= write16(state
, OFDM_SC_COMM_EXEC__A
, OFDM_SC_COMM_EXEC_STOP
);
1770 status
= write16(state
, OFDM_LC_COMM_EXEC__A
, OFDM_LC_COMM_EXEC_STOP
);
1773 status
= write16(state
, IQM_COMM_EXEC__A
, IQM_COMM_EXEC_B_STOP
);
1778 status
= SetIqmAf(state
, false);
1782 /* powerdown to OFDM mode */
1784 status
= CtrlPowerMode(state
, &powerMode
);
1790 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1794 static int SetOperationMode(struct drxk_state
*state
,
1795 enum OperationMode oMode
)
1801 Stop and power down previous standard
1802 TODO investigate total power down instead of partial
1803 power down depending on "previous" standard.
1806 /* disable HW lock indicator */
1807 status
= write16(state
, SCU_RAM_GPIO__A
, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE
);
1811 /* Device is already at the required mode */
1812 if (state
->m_OperationMode
== oMode
)
1815 switch (state
->m_OperationMode
) {
1816 /* OM_NONE was added for start up */
1820 status
= MPEGTSStop(state
);
1823 status
= PowerDownDVBT(state
, true);
1826 state
->m_OperationMode
= OM_NONE
;
1828 case OM_QAM_ITU_A
: /* fallthrough */
1830 status
= MPEGTSStop(state
);
1833 status
= PowerDownQAM(state
);
1836 state
->m_OperationMode
= OM_NONE
;
1845 Power up new standard
1849 state
->m_OperationMode
= oMode
;
1850 status
= SetDVBTStandard(state
, oMode
);
1854 case OM_QAM_ITU_A
: /* fallthrough */
1856 state
->m_OperationMode
= oMode
;
1857 status
= SetQAMStandard(state
, oMode
);
1867 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1871 static int Start(struct drxk_state
*state
, s32 offsetFreq
,
1872 s32 IntermediateFrequency
)
1874 int status
= -EINVAL
;
1877 s32 OffsetkHz
= offsetFreq
/ 1000;
1880 if (state
->m_DrxkState
!= DRXK_STOPPED
&&
1881 state
->m_DrxkState
!= DRXK_DTV_STARTED
)
1884 state
->m_bMirrorFreqSpect
= (state
->param
.inversion
== INVERSION_ON
);
1886 if (IntermediateFrequency
< 0) {
1887 state
->m_bMirrorFreqSpect
= !state
->m_bMirrorFreqSpect
;
1888 IntermediateFrequency
= -IntermediateFrequency
;
1891 switch (state
->m_OperationMode
) {
1894 IFreqkHz
= (IntermediateFrequency
/ 1000);
1895 status
= SetQAM(state
, IFreqkHz
, OffsetkHz
);
1898 state
->m_DrxkState
= DRXK_DTV_STARTED
;
1901 IFreqkHz
= (IntermediateFrequency
/ 1000);
1902 status
= MPEGTSStop(state
);
1905 status
= SetDVBT(state
, IFreqkHz
, OffsetkHz
);
1908 status
= DVBTStart(state
);
1911 state
->m_DrxkState
= DRXK_DTV_STARTED
;
1918 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1922 static int ShutDown(struct drxk_state
*state
)
1930 static int GetLockStatus(struct drxk_state
*state
, u32
*pLockStatus
,
1933 int status
= -EINVAL
;
1937 if (pLockStatus
== NULL
)
1940 *pLockStatus
= NOT_LOCKED
;
1942 /* define the SCU command code */
1943 switch (state
->m_OperationMode
) {
1947 status
= GetQAMLockStatus(state
, pLockStatus
);
1950 status
= GetDVBTLockStatus(state
, pLockStatus
);
1957 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1961 static int MPEGTSStart(struct drxk_state
*state
)
1965 u16 fecOcSncMode
= 0;
1967 /* Allow OC to sync again */
1968 status
= read16(state
, FEC_OC_SNC_MODE__A
, &fecOcSncMode
);
1971 fecOcSncMode
&= ~FEC_OC_SNC_MODE_SHUTDOWN__M
;
1972 status
= write16(state
, FEC_OC_SNC_MODE__A
, fecOcSncMode
);
1975 status
= write16(state
, FEC_OC_SNC_UNLOCK__A
, 1);
1978 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
1982 static int MPEGTSDtoInit(struct drxk_state
*state
)
1988 /* Rate integration settings */
1989 status
= write16(state
, FEC_OC_RCN_CTL_STEP_LO__A
, 0x0000);
1992 status
= write16(state
, FEC_OC_RCN_CTL_STEP_HI__A
, 0x000C);
1995 status
= write16(state
, FEC_OC_RCN_GAIN__A
, 0x000A);
1998 status
= write16(state
, FEC_OC_AVR_PARM_A__A
, 0x0008);
2001 status
= write16(state
, FEC_OC_AVR_PARM_B__A
, 0x0006);
2004 status
= write16(state
, FEC_OC_TMD_HI_MARGIN__A
, 0x0680);
2007 status
= write16(state
, FEC_OC_TMD_LO_MARGIN__A
, 0x0080);
2010 status
= write16(state
, FEC_OC_TMD_COUNT__A
, 0x03F4);
2014 /* Additional configuration */
2015 status
= write16(state
, FEC_OC_OCR_INVERT__A
, 0);
2018 status
= write16(state
, FEC_OC_SNC_LWM__A
, 2);
2021 status
= write16(state
, FEC_OC_SNC_HWM__A
, 12);
2024 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2029 static int MPEGTSDtoSetup(struct drxk_state
*state
,
2030 enum OperationMode oMode
)
2034 u16 fecOcRegMode
= 0; /* FEC_OC_MODE register value */
2035 u16 fecOcRegIprMode
= 0; /* FEC_OC_IPR_MODE register value */
2036 u16 fecOcDtoMode
= 0; /* FEC_OC_IPR_INVERT register value */
2037 u16 fecOcFctMode
= 0; /* FEC_OC_IPR_INVERT register value */
2038 u16 fecOcDtoPeriod
= 2; /* FEC_OC_IPR_INVERT register value */
2039 u16 fecOcDtoBurstLen
= 188; /* FEC_OC_IPR_INVERT register value */
2040 u32 fecOcRcnCtlRate
= 0; /* FEC_OC_IPR_INVERT register value */
2041 u16 fecOcTmdMode
= 0;
2042 u16 fecOcTmdIntUpdRate
= 0;
2044 bool staticCLK
= false;
2048 /* Check insertion of the Reed-Solomon parity bytes */
2049 status
= read16(state
, FEC_OC_MODE__A
, &fecOcRegMode
);
2052 status
= read16(state
, FEC_OC_IPR_MODE__A
, &fecOcRegIprMode
);
2055 fecOcRegMode
&= (~FEC_OC_MODE_PARITY__M
);
2056 fecOcRegIprMode
&= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M
);
2057 if (state
->m_insertRSByte
== true) {
2058 /* enable parity symbol forward */
2059 fecOcRegMode
|= FEC_OC_MODE_PARITY__M
;
2060 /* MVAL disable during parity bytes */
2061 fecOcRegIprMode
|= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M
;
2062 /* TS burst length to 204 */
2063 fecOcDtoBurstLen
= 204;
2066 /* Check serial or parrallel output */
2067 fecOcRegIprMode
&= (~(FEC_OC_IPR_MODE_SERIAL__M
));
2068 if (state
->m_enableParallel
== false) {
2069 /* MPEG data output is serial -> set ipr_mode[0] */
2070 fecOcRegIprMode
|= FEC_OC_IPR_MODE_SERIAL__M
;
2075 maxBitRate
= state
->m_DVBTBitrate
;
2077 fecOcRcnCtlRate
= 0xC00000;
2078 staticCLK
= state
->m_DVBTStaticCLK
;
2080 case OM_QAM_ITU_A
: /* fallthrough */
2082 fecOcTmdMode
= 0x0004;
2083 fecOcRcnCtlRate
= 0xD2B4EE; /* good for >63 Mb/s */
2084 maxBitRate
= state
->m_DVBCBitrate
;
2085 staticCLK
= state
->m_DVBCStaticCLK
;
2089 } /* switch (standard) */
2093 /* Configure DTO's */
2097 /* Rational DTO for MCLK source (static MCLK rate),
2098 Dynamic DTO for optimal grouping
2099 (avoid intra-packet gaps),
2100 DTO offset enable to sync TS burst with MSTRT */
2101 fecOcDtoMode
= (FEC_OC_DTO_MODE_DYNAMIC__M
|
2102 FEC_OC_DTO_MODE_OFFSET_ENABLE__M
);
2103 fecOcFctMode
= (FEC_OC_FCT_MODE_RAT_ENA__M
|
2104 FEC_OC_FCT_MODE_VIRT_ENA__M
);
2106 /* Check user defined bitrate */
2107 bitRate
= maxBitRate
;
2108 if (bitRate
> 75900000UL) { /* max is 75.9 Mb/s */
2109 bitRate
= 75900000UL;
2111 /* Rational DTO period:
2112 dto_period = (Fsys / bitrate) - 2
2114 Result should be floored,
2115 to make sure >= requested bitrate
2117 fecOcDtoPeriod
= (u16
) (((state
->m_sysClockFreq
)
2119 if (fecOcDtoPeriod
<= 2)
2122 fecOcDtoPeriod
-= 2;
2123 fecOcTmdIntUpdRate
= 8;
2125 /* (commonAttr->staticCLK == false) => dynamic mode */
2126 fecOcDtoMode
= FEC_OC_DTO_MODE_DYNAMIC__M
;
2127 fecOcFctMode
= FEC_OC_FCT_MODE__PRE
;
2128 fecOcTmdIntUpdRate
= 5;
2131 /* Write appropriate registers with requested configuration */
2132 status
= write16(state
, FEC_OC_DTO_BURST_LEN__A
, fecOcDtoBurstLen
);
2135 status
= write16(state
, FEC_OC_DTO_PERIOD__A
, fecOcDtoPeriod
);
2138 status
= write16(state
, FEC_OC_DTO_MODE__A
, fecOcDtoMode
);
2141 status
= write16(state
, FEC_OC_FCT_MODE__A
, fecOcFctMode
);
2144 status
= write16(state
, FEC_OC_MODE__A
, fecOcRegMode
);
2147 status
= write16(state
, FEC_OC_IPR_MODE__A
, fecOcRegIprMode
);
2151 /* Rate integration settings */
2152 status
= write32(state
, FEC_OC_RCN_CTL_RATE_LO__A
, fecOcRcnCtlRate
);
2155 status
= write16(state
, FEC_OC_TMD_INT_UPD_RATE__A
, fecOcTmdIntUpdRate
);
2158 status
= write16(state
, FEC_OC_TMD_MODE__A
, fecOcTmdMode
);
2161 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2165 static int MPEGTSConfigurePolarity(struct drxk_state
*state
)
2167 u16 fecOcRegIprInvert
= 0;
2169 /* Data mask for the output data byte */
2170 u16 InvertDataMask
=
2171 FEC_OC_IPR_INVERT_MD7__M
| FEC_OC_IPR_INVERT_MD6__M
|
2172 FEC_OC_IPR_INVERT_MD5__M
| FEC_OC_IPR_INVERT_MD4__M
|
2173 FEC_OC_IPR_INVERT_MD3__M
| FEC_OC_IPR_INVERT_MD2__M
|
2174 FEC_OC_IPR_INVERT_MD1__M
| FEC_OC_IPR_INVERT_MD0__M
;
2178 /* Control selective inversion of output bits */
2179 fecOcRegIprInvert
&= (~(InvertDataMask
));
2180 if (state
->m_invertDATA
== true)
2181 fecOcRegIprInvert
|= InvertDataMask
;
2182 fecOcRegIprInvert
&= (~(FEC_OC_IPR_INVERT_MERR__M
));
2183 if (state
->m_invertERR
== true)
2184 fecOcRegIprInvert
|= FEC_OC_IPR_INVERT_MERR__M
;
2185 fecOcRegIprInvert
&= (~(FEC_OC_IPR_INVERT_MSTRT__M
));
2186 if (state
->m_invertSTR
== true)
2187 fecOcRegIprInvert
|= FEC_OC_IPR_INVERT_MSTRT__M
;
2188 fecOcRegIprInvert
&= (~(FEC_OC_IPR_INVERT_MVAL__M
));
2189 if (state
->m_invertVAL
== true)
2190 fecOcRegIprInvert
|= FEC_OC_IPR_INVERT_MVAL__M
;
2191 fecOcRegIprInvert
&= (~(FEC_OC_IPR_INVERT_MCLK__M
));
2192 if (state
->m_invertCLK
== true)
2193 fecOcRegIprInvert
|= FEC_OC_IPR_INVERT_MCLK__M
;
2195 return write16(state
, FEC_OC_IPR_INVERT__A
, fecOcRegIprInvert
);
2198 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2200 static int SetAgcRf(struct drxk_state
*state
,
2201 struct SCfgAgc
*pAgcCfg
, bool isDTV
)
2203 int status
= -EINVAL
;
2205 struct SCfgAgc
*pIfAgcSettings
;
2209 if (pAgcCfg
== NULL
)
2212 switch (pAgcCfg
->ctrlMode
) {
2213 case DRXK_AGC_CTRL_AUTO
:
2214 /* Enable RF AGC DAC */
2215 status
= read16(state
, IQM_AF_STDBY__A
, &data
);
2218 data
&= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY
;
2219 status
= write16(state
, IQM_AF_STDBY__A
, data
);
2222 status
= read16(state
, SCU_RAM_AGC_CONFIG__A
, &data
);
2226 /* Enable SCU RF AGC loop */
2227 data
&= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M
;
2230 if (state
->m_RfAgcPol
)
2231 data
|= SCU_RAM_AGC_CONFIG_INV_RF_POL__M
;
2233 data
&= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M
;
2234 status
= write16(state
, SCU_RAM_AGC_CONFIG__A
, data
);
2238 /* Set speed (using complementary reduction value) */
2239 status
= read16(state
, SCU_RAM_AGC_KI_RED__A
, &data
);
2243 data
&= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M
;
2244 data
|= (~(pAgcCfg
->speed
<<
2245 SCU_RAM_AGC_KI_RED_RAGC_RED__B
)
2246 & SCU_RAM_AGC_KI_RED_RAGC_RED__M
);
2248 status
= write16(state
, SCU_RAM_AGC_KI_RED__A
, data
);
2253 pIfAgcSettings
= &state
->m_dvbtIfAgcCfg
;
2254 else if (IsQAM(state
))
2255 pIfAgcSettings
= &state
->m_qamIfAgcCfg
;
2257 pIfAgcSettings
= &state
->m_atvIfAgcCfg
;
2258 if (pIfAgcSettings
== NULL
) {
2263 /* Set TOP, only if IF-AGC is in AUTO mode */
2264 if (pIfAgcSettings
->ctrlMode
== DRXK_AGC_CTRL_AUTO
)
2265 status
= write16(state
, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A
, pAgcCfg
->top
);
2269 /* Cut-Off current */
2270 status
= write16(state
, SCU_RAM_AGC_RF_IACCU_HI_CO__A
, pAgcCfg
->cutOffCurrent
);
2274 /* Max. output level */
2275 status
= write16(state
, SCU_RAM_AGC_RF_MAX__A
, pAgcCfg
->maxOutputLevel
);
2281 case DRXK_AGC_CTRL_USER
:
2282 /* Enable RF AGC DAC */
2283 status
= read16(state
, IQM_AF_STDBY__A
, &data
);
2286 data
&= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY
;
2287 status
= write16(state
, IQM_AF_STDBY__A
, data
);
2291 /* Disable SCU RF AGC loop */
2292 status
= read16(state
, SCU_RAM_AGC_CONFIG__A
, &data
);
2295 data
|= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M
;
2296 if (state
->m_RfAgcPol
)
2297 data
|= SCU_RAM_AGC_CONFIG_INV_RF_POL__M
;
2299 data
&= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M
;
2300 status
= write16(state
, SCU_RAM_AGC_CONFIG__A
, data
);
2304 /* SCU c.o.c. to 0, enabling full control range */
2305 status
= write16(state
, SCU_RAM_AGC_RF_IACCU_HI_CO__A
, 0);
2309 /* Write value to output pin */
2310 status
= write16(state
, SCU_RAM_AGC_RF_IACCU_HI__A
, pAgcCfg
->outputLevel
);
2315 case DRXK_AGC_CTRL_OFF
:
2316 /* Disable RF AGC DAC */
2317 status
= read16(state
, IQM_AF_STDBY__A
, &data
);
2320 data
|= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY
;
2321 status
= write16(state
, IQM_AF_STDBY__A
, data
);
2325 /* Disable SCU RF AGC loop */
2326 status
= read16(state
, SCU_RAM_AGC_CONFIG__A
, &data
);
2329 data
|= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M
;
2330 status
= write16(state
, SCU_RAM_AGC_CONFIG__A
, data
);
2341 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2345 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2347 static int SetAgcIf(struct drxk_state
*state
,
2348 struct SCfgAgc
*pAgcCfg
, bool isDTV
)
2352 struct SCfgAgc
*pRfAgcSettings
;
2356 switch (pAgcCfg
->ctrlMode
) {
2357 case DRXK_AGC_CTRL_AUTO
:
2359 /* Enable IF AGC DAC */
2360 status
= read16(state
, IQM_AF_STDBY__A
, &data
);
2363 data
&= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
;
2364 status
= write16(state
, IQM_AF_STDBY__A
, data
);
2368 status
= read16(state
, SCU_RAM_AGC_CONFIG__A
, &data
);
2372 /* Enable SCU IF AGC loop */
2373 data
&= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M
;
2376 if (state
->m_IfAgcPol
)
2377 data
|= SCU_RAM_AGC_CONFIG_INV_IF_POL__M
;
2379 data
&= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M
;
2380 status
= write16(state
, SCU_RAM_AGC_CONFIG__A
, data
);
2384 /* Set speed (using complementary reduction value) */
2385 status
= read16(state
, SCU_RAM_AGC_KI_RED__A
, &data
);
2388 data
&= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M
;
2389 data
|= (~(pAgcCfg
->speed
<<
2390 SCU_RAM_AGC_KI_RED_IAGC_RED__B
)
2391 & SCU_RAM_AGC_KI_RED_IAGC_RED__M
);
2393 status
= write16(state
, SCU_RAM_AGC_KI_RED__A
, data
);
2398 pRfAgcSettings
= &state
->m_qamRfAgcCfg
;
2400 pRfAgcSettings
= &state
->m_atvRfAgcCfg
;
2401 if (pRfAgcSettings
== NULL
)
2404 status
= write16(state
, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A
, pRfAgcSettings
->top
);
2409 case DRXK_AGC_CTRL_USER
:
2411 /* Enable IF AGC DAC */
2412 status
= read16(state
, IQM_AF_STDBY__A
, &data
);
2415 data
&= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
;
2416 status
= write16(state
, IQM_AF_STDBY__A
, data
);
2420 status
= read16(state
, SCU_RAM_AGC_CONFIG__A
, &data
);
2424 /* Disable SCU IF AGC loop */
2425 data
|= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M
;
2428 if (state
->m_IfAgcPol
)
2429 data
|= SCU_RAM_AGC_CONFIG_INV_IF_POL__M
;
2431 data
&= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M
;
2432 status
= write16(state
, SCU_RAM_AGC_CONFIG__A
, data
);
2436 /* Write value to output pin */
2437 status
= write16(state
, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A
, pAgcCfg
->outputLevel
);
2442 case DRXK_AGC_CTRL_OFF
:
2444 /* Disable If AGC DAC */
2445 status
= read16(state
, IQM_AF_STDBY__A
, &data
);
2448 data
|= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
;
2449 status
= write16(state
, IQM_AF_STDBY__A
, data
);
2453 /* Disable SCU IF AGC loop */
2454 status
= read16(state
, SCU_RAM_AGC_CONFIG__A
, &data
);
2457 data
|= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M
;
2458 status
= write16(state
, SCU_RAM_AGC_CONFIG__A
, data
);
2462 } /* switch (agcSettingsIf->ctrlMode) */
2464 /* always set the top to support
2465 configurations without if-loop */
2466 status
= write16(state
, SCU_RAM_AGC_INGAIN_TGT_MIN__A
, pAgcCfg
->top
);
2469 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2473 static int ReadIFAgc(struct drxk_state
*state
, u32
*pValue
)
2481 status
= read16(state
, IQM_AF_AGC_IF__A
, &agcDacLvl
);
2483 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2489 if (agcDacLvl
> DRXK_AGC_DAC_OFFSET
)
2490 Level
= agcDacLvl
- DRXK_AGC_DAC_OFFSET
;
2492 *pValue
= (14000 - Level
) / 4;
2499 static int GetQAMSignalToNoise(struct drxk_state
*state
,
2500 s32
*pSignalToNoise
)
2503 u16 qamSlErrPower
= 0; /* accum. error between
2504 raw and sliced symbols */
2505 u32 qamSlSigPower
= 0; /* used for MER, depends of
2506 QAM constellation */
2507 u32 qamSlMer
= 0; /* QAM MER */
2511 /* MER calculation */
2513 /* get the register value needed for MER */
2514 status
= read16(state
, QAM_SL_ERR_POWER__A
, &qamSlErrPower
);
2516 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2520 switch (state
->param
.u
.qam
.modulation
) {
2522 qamSlSigPower
= DRXK_QAM_SL_SIG_POWER_QAM16
<< 2;
2525 qamSlSigPower
= DRXK_QAM_SL_SIG_POWER_QAM32
<< 2;
2528 qamSlSigPower
= DRXK_QAM_SL_SIG_POWER_QAM64
<< 2;
2531 qamSlSigPower
= DRXK_QAM_SL_SIG_POWER_QAM128
<< 2;
2535 qamSlSigPower
= DRXK_QAM_SL_SIG_POWER_QAM256
<< 2;
2539 if (qamSlErrPower
> 0) {
2540 qamSlMer
= Log10Times100(qamSlSigPower
) -
2541 Log10Times100((u32
) qamSlErrPower
);
2543 *pSignalToNoise
= qamSlMer
;
2548 static int GetDVBTSignalToNoise(struct drxk_state
*state
,
2549 s32
*pSignalToNoise
)
2553 u32 EqRegTdSqrErrI
= 0;
2554 u32 EqRegTdSqrErrQ
= 0;
2555 u16 EqRegTdSqrErrExp
= 0;
2556 u16 EqRegTdTpsPwrOfs
= 0;
2557 u16 EqRegTdReqSmbCnt
= 0;
2564 u16 transmissionParams
= 0;
2568 status
= read16(state
, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A
, &EqRegTdTpsPwrOfs
);
2571 status
= read16(state
, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A
, &EqRegTdReqSmbCnt
);
2574 status
= read16(state
, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A
, &EqRegTdSqrErrExp
);
2577 status
= read16(state
, OFDM_EQ_TOP_TD_SQR_ERR_I__A
, ®Data
);
2580 /* Extend SQR_ERR_I operational range */
2581 EqRegTdSqrErrI
= (u32
) regData
;
2582 if ((EqRegTdSqrErrExp
> 11) &&
2583 (EqRegTdSqrErrI
< 0x00000FFFUL
)) {
2584 EqRegTdSqrErrI
+= 0x00010000UL
;
2586 status
= read16(state
, OFDM_EQ_TOP_TD_SQR_ERR_Q__A
, ®Data
);
2589 /* Extend SQR_ERR_Q operational range */
2590 EqRegTdSqrErrQ
= (u32
) regData
;
2591 if ((EqRegTdSqrErrExp
> 11) &&
2592 (EqRegTdSqrErrQ
< 0x00000FFFUL
))
2593 EqRegTdSqrErrQ
+= 0x00010000UL
;
2595 status
= read16(state
, OFDM_SC_RA_RAM_OP_PARAM__A
, &transmissionParams
);
2599 /* Check input data for MER */
2601 /* MER calculation (in 0.1 dB) without math.h */
2602 if ((EqRegTdTpsPwrOfs
== 0) || (EqRegTdReqSmbCnt
== 0))
2604 else if ((EqRegTdSqrErrI
+ EqRegTdSqrErrQ
) == 0) {
2605 /* No error at all, this must be the HW reset value
2606 * Apparently no first measurement yet
2610 SqrErrIQ
= (EqRegTdSqrErrI
+ EqRegTdSqrErrQ
) <<
2612 if ((transmissionParams
&
2613 OFDM_SC_RA_RAM_OP_PARAM_MODE__M
)
2614 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K
)
2619 /* IMER = 100 * log10 (x)
2620 where x = (EqRegTdTpsPwrOfs^2 *
2621 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2624 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2625 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2626 c = 100 * log10 (SqrErrIQ)
2629 /* log(x) x = 9bits * 9bits->18 bits */
2630 a
= Log10Times100(EqRegTdTpsPwrOfs
*
2632 /* log(x) x = 16bits * 7bits->23 bits */
2633 b
= Log10Times100(EqRegTdReqSmbCnt
* tpsCnt
);
2634 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2635 c
= Log10Times100(SqrErrIQ
);
2638 /* No negative MER, clip to zero */
2644 *pSignalToNoise
= iMER
;
2648 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2652 static int GetSignalToNoise(struct drxk_state
*state
, s32
*pSignalToNoise
)
2656 *pSignalToNoise
= 0;
2657 switch (state
->m_OperationMode
) {
2659 return GetDVBTSignalToNoise(state
, pSignalToNoise
);
2662 return GetQAMSignalToNoise(state
, pSignalToNoise
);
2670 static int GetDVBTQuality(struct drxk_state
*state
, s32
*pQuality
)
2672 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2677 static s32 QE_SN
[] = {
2683 108, /* 16-QAM 1/2 */
2684 131, /* 16-QAM 2/3 */
2685 146, /* 16-QAM 3/4 */
2686 156, /* 16-QAM 5/6 */
2687 160, /* 16-QAM 7/8 */
2688 165, /* 64-QAM 1/2 */
2689 187, /* 64-QAM 2/3 */
2690 202, /* 64-QAM 3/4 */
2691 216, /* 64-QAM 5/6 */
2692 225, /* 64-QAM 7/8 */
2698 s32 SignalToNoise
= 0;
2699 u16 Constellation
= 0;
2701 u32 SignalToNoiseRel
;
2704 status
= GetDVBTSignalToNoise(state
, &SignalToNoise
);
2707 status
= read16(state
, OFDM_EQ_TOP_TD_TPS_CONST__A
, &Constellation
);
2710 Constellation
&= OFDM_EQ_TOP_TD_TPS_CONST__M
;
2712 status
= read16(state
, OFDM_EQ_TOP_TD_TPS_CODE_HP__A
, &CodeRate
);
2715 CodeRate
&= OFDM_EQ_TOP_TD_TPS_CODE_HP__M
;
2717 if (Constellation
> OFDM_EQ_TOP_TD_TPS_CONST_64QAM
||
2718 CodeRate
> OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8
)
2720 SignalToNoiseRel
= SignalToNoise
-
2721 QE_SN
[Constellation
* 5 + CodeRate
];
2724 if (SignalToNoiseRel
< -70)
2726 else if (SignalToNoiseRel
< 30)
2727 *pQuality
= ((SignalToNoiseRel
+ 70) *
2730 *pQuality
= BERQuality
;
2735 static int GetDVBCQuality(struct drxk_state
*state
, s32
*pQuality
)
2743 u32 SignalToNoise
= 0;
2744 u32 BERQuality
= 100;
2745 u32 SignalToNoiseRel
= 0;
2747 status
= GetQAMSignalToNoise(state
, &SignalToNoise
);
2751 switch (state
->param
.u
.qam
.modulation
) {
2753 SignalToNoiseRel
= SignalToNoise
- 200;
2756 SignalToNoiseRel
= SignalToNoise
- 230;
2757 break; /* Not in NorDig */
2759 SignalToNoiseRel
= SignalToNoise
- 260;
2762 SignalToNoiseRel
= SignalToNoise
- 290;
2766 SignalToNoiseRel
= SignalToNoise
- 320;
2770 if (SignalToNoiseRel
< -70)
2772 else if (SignalToNoiseRel
< 30)
2773 *pQuality
= ((SignalToNoiseRel
+ 70) *
2776 *pQuality
= BERQuality
;
2782 static int GetQuality(struct drxk_state
*state
, s32
*pQuality
)
2786 switch (state
->m_OperationMode
) {
2788 return GetDVBTQuality(state
, pQuality
);
2790 return GetDVBCQuality(state
, pQuality
);
2799 /* Free data ram in SIO HI */
2800 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2801 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2803 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2804 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2805 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2806 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2808 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2809 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2810 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2812 static int ConfigureI2CBridge(struct drxk_state
*state
, bool bEnableBridge
)
2814 int status
= -EINVAL
;
2818 if (state
->m_DrxkState
== DRXK_UNINITIALIZED
)
2820 if (state
->m_DrxkState
== DRXK_POWERED_DOWN
)
2823 if (state
->no_i2c_bridge
)
2826 status
= write16(state
, SIO_HI_RA_RAM_PAR_1__A
, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY
);
2829 if (bEnableBridge
) {
2830 status
= write16(state
, SIO_HI_RA_RAM_PAR_2__A
, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED
);
2834 status
= write16(state
, SIO_HI_RA_RAM_PAR_2__A
, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN
);
2839 status
= HI_Command(state
, SIO_HI_RA_RAM_CMD_BRDCTRL
, 0);
2843 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2847 static int SetPreSaw(struct drxk_state
*state
,
2848 struct SCfgPreSaw
*pPreSawCfg
)
2850 int status
= -EINVAL
;
2854 if ((pPreSawCfg
== NULL
)
2855 || (pPreSawCfg
->reference
> IQM_AF_PDREF__M
))
2858 status
= write16(state
, IQM_AF_PDREF__A
, pPreSawCfg
->reference
);
2861 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2865 static int BLDirectCmd(struct drxk_state
*state
, u32 targetAddr
,
2866 u16 romOffset
, u16 nrOfElements
, u32 timeOut
)
2869 u16 offset
= (u16
) ((targetAddr
>> 0) & 0x00FFFF);
2870 u16 blockbank
= (u16
) ((targetAddr
>> 16) & 0x000FFF);
2876 mutex_lock(&state
->mutex
);
2877 status
= write16(state
, SIO_BL_MODE__A
, SIO_BL_MODE_DIRECT
);
2880 status
= write16(state
, SIO_BL_TGT_HDR__A
, blockbank
);
2883 status
= write16(state
, SIO_BL_TGT_ADDR__A
, offset
);
2886 status
= write16(state
, SIO_BL_SRC_ADDR__A
, romOffset
);
2889 status
= write16(state
, SIO_BL_SRC_LEN__A
, nrOfElements
);
2892 status
= write16(state
, SIO_BL_ENABLE__A
, SIO_BL_ENABLE_ON
);
2896 end
= jiffies
+ msecs_to_jiffies(timeOut
);
2898 status
= read16(state
, SIO_BL_STATUS__A
, &blStatus
);
2901 } while ((blStatus
== 0x1) && time_is_after_jiffies(end
));
2902 if (blStatus
== 0x1) {
2903 printk(KERN_ERR
"drxk: SIO not ready\n");
2909 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2911 mutex_unlock(&state
->mutex
);
2916 static int ADCSyncMeasurement(struct drxk_state
*state
, u16
*count
)
2923 /* Start measurement */
2924 status
= write16(state
, IQM_AF_COMM_EXEC__A
, IQM_AF_COMM_EXEC_ACTIVE
);
2927 status
= write16(state
, IQM_AF_START_LOCK__A
, 1);
2932 status
= read16(state
, IQM_AF_PHASE0__A
, &data
);
2936 *count
= *count
+ 1;
2937 status
= read16(state
, IQM_AF_PHASE1__A
, &data
);
2941 *count
= *count
+ 1;
2942 status
= read16(state
, IQM_AF_PHASE2__A
, &data
);
2946 *count
= *count
+ 1;
2950 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2954 static int ADCSynchronization(struct drxk_state
*state
)
2961 status
= ADCSyncMeasurement(state
, &count
);
2966 /* Try sampling on a diffrent edge */
2969 status
= read16(state
, IQM_AF_CLKNEG__A
, &clkNeg
);
2972 if ((clkNeg
| IQM_AF_CLKNEG_CLKNEGDATA__M
) ==
2973 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS
) {
2974 clkNeg
&= (~(IQM_AF_CLKNEG_CLKNEGDATA__M
));
2976 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG
;
2978 clkNeg
&= (~(IQM_AF_CLKNEG_CLKNEGDATA__M
));
2980 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS
;
2982 status
= write16(state
, IQM_AF_CLKNEG__A
, clkNeg
);
2985 status
= ADCSyncMeasurement(state
, &count
);
2994 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
2998 static int SetFrequencyShifter(struct drxk_state
*state
,
2999 u16 intermediateFreqkHz
,
3000 s32 tunerFreqOffset
, bool isDTV
)
3002 bool selectPosImage
= false;
3003 u32 rfFreqResidual
= tunerFreqOffset
;
3004 u32 fmFrequencyShift
= 0;
3005 bool tunerMirror
= !state
->m_bMirrorFreqSpect
;
3010 u32 samplingFrequency
= (u32
) (state
->m_sysClockFreq
/ 3);
3017 Program frequency shifter
3018 No need to account for mirroring on RF
3021 if ((state
->m_OperationMode
== OM_QAM_ITU_A
) ||
3022 (state
->m_OperationMode
== OM_QAM_ITU_C
) ||
3023 (state
->m_OperationMode
== OM_DVBT
))
3024 selectPosImage
= true;
3026 selectPosImage
= false;
3029 /* tuner doesn't mirror */
3030 ifFreqActual
= intermediateFreqkHz
+
3031 rfFreqResidual
+ fmFrequencyShift
;
3034 ifFreqActual
= intermediateFreqkHz
-
3035 rfFreqResidual
- fmFrequencyShift
;
3036 if (ifFreqActual
> samplingFrequency
/ 2) {
3038 adcFreq
= samplingFrequency
- ifFreqActual
;
3041 /* adc doesn't mirror */
3042 adcFreq
= ifFreqActual
;
3046 frequencyShift
= adcFreq
;
3047 imageToSelect
= state
->m_rfmirror
^ tunerMirror
^
3048 adcFlip
^ selectPosImage
;
3049 state
->m_IqmFsRateOfs
=
3050 Frac28a((frequencyShift
), samplingFrequency
);
3053 state
->m_IqmFsRateOfs
= ~state
->m_IqmFsRateOfs
+ 1;
3055 /* Program frequency shifter with tuner offset compensation */
3056 /* frequencyShift += tunerFreqOffset; TODO */
3057 status
= write32(state
, IQM_FS_RATE_OFS_LO__A
,
3058 state
->m_IqmFsRateOfs
);
3060 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3064 static int InitAGC(struct drxk_state
*state
, bool isDTV
)
3067 u16 ingainTgtMin
= 0;
3068 u16 ingainTgtMax
= 0;
3076 u16 kiInnergainMin
= 0;
3077 u16 ifIaccuHiTgt
= 0;
3078 u16 ifIaccuHiTgtMin
= 0;
3079 u16 ifIaccuHiTgtMax
= 0;
3081 u16 fastClpCtrlDelay
= 0;
3082 u16 clpCtrlMode
= 0;
3087 /* Common settings */
3089 ifIaccuHiTgtMin
= 2047;
3093 /* AGCInit() not available for DVBT; init done in microcode */
3094 if (!IsQAM(state
)) {
3095 printk(KERN_ERR
"drxk: %s: mode %d is not DVB-C\n", __func__
, state
->m_OperationMode
);
3099 /* FIXME: Analog TV AGC require different settings */
3101 /* Standard specific settings */
3103 clpDirTo
= (u16
) -9;
3106 snsDirTo
= (u16
) -9;
3107 kiInnergainMin
= (u16
) -1030;
3108 ifIaccuHiTgtMax
= 0x2380;
3109 ifIaccuHiTgt
= 0x2380;
3110 ingainTgtMin
= 0x0511;
3112 ingainTgtMax
= 5119;
3113 fastClpCtrlDelay
= state
->m_qamIfAgcCfg
.FastClipCtrlDelay
;
3115 status
= write16(state
, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A
, fastClpCtrlDelay
);
3119 status
= write16(state
, SCU_RAM_AGC_CLP_CTRL_MODE__A
, clpCtrlMode
);
3122 status
= write16(state
, SCU_RAM_AGC_INGAIN_TGT__A
, ingainTgt
);
3125 status
= write16(state
, SCU_RAM_AGC_INGAIN_TGT_MIN__A
, ingainTgtMin
);
3128 status
= write16(state
, SCU_RAM_AGC_INGAIN_TGT_MAX__A
, ingainTgtMax
);
3131 status
= write16(state
, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A
, ifIaccuHiTgtMin
);
3134 status
= write16(state
, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A
, ifIaccuHiTgtMax
);
3137 status
= write16(state
, SCU_RAM_AGC_IF_IACCU_HI__A
, 0);
3140 status
= write16(state
, SCU_RAM_AGC_IF_IACCU_LO__A
, 0);
3143 status
= write16(state
, SCU_RAM_AGC_RF_IACCU_HI__A
, 0);
3146 status
= write16(state
, SCU_RAM_AGC_RF_IACCU_LO__A
, 0);
3149 status
= write16(state
, SCU_RAM_AGC_CLP_SUM_MAX__A
, clpSumMax
);
3152 status
= write16(state
, SCU_RAM_AGC_SNS_SUM_MAX__A
, snsSumMax
);
3156 status
= write16(state
, SCU_RAM_AGC_KI_INNERGAIN_MIN__A
, kiInnergainMin
);
3159 status
= write16(state
, SCU_RAM_AGC_IF_IACCU_HI_TGT__A
, ifIaccuHiTgt
);
3162 status
= write16(state
, SCU_RAM_AGC_CLP_CYCLEN__A
, clpCyclen
);
3166 status
= write16(state
, SCU_RAM_AGC_RF_SNS_DEV_MAX__A
, 1023);
3169 status
= write16(state
, SCU_RAM_AGC_RF_SNS_DEV_MIN__A
, (u16
) -1023);
3172 status
= write16(state
, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A
, 50);
3176 status
= write16(state
, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A
, 20);
3179 status
= write16(state
, SCU_RAM_AGC_CLP_SUM_MIN__A
, clpSumMin
);
3182 status
= write16(state
, SCU_RAM_AGC_SNS_SUM_MIN__A
, snsSumMin
);
3185 status
= write16(state
, SCU_RAM_AGC_CLP_DIR_TO__A
, clpDirTo
);
3188 status
= write16(state
, SCU_RAM_AGC_SNS_DIR_TO__A
, snsDirTo
);
3191 status
= write16(state
, SCU_RAM_AGC_KI_MINGAIN__A
, 0x7fff);
3194 status
= write16(state
, SCU_RAM_AGC_KI_MAXGAIN__A
, 0x0);
3197 status
= write16(state
, SCU_RAM_AGC_KI_MIN__A
, 0x0117);
3200 status
= write16(state
, SCU_RAM_AGC_KI_MAX__A
, 0x0657);
3203 status
= write16(state
, SCU_RAM_AGC_CLP_SUM__A
, 0);
3206 status
= write16(state
, SCU_RAM_AGC_CLP_CYCCNT__A
, 0);
3209 status
= write16(state
, SCU_RAM_AGC_CLP_DIR_WD__A
, 0);
3212 status
= write16(state
, SCU_RAM_AGC_CLP_DIR_STP__A
, 1);
3215 status
= write16(state
, SCU_RAM_AGC_SNS_SUM__A
, 0);
3218 status
= write16(state
, SCU_RAM_AGC_SNS_CYCCNT__A
, 0);
3221 status
= write16(state
, SCU_RAM_AGC_SNS_DIR_WD__A
, 0);
3224 status
= write16(state
, SCU_RAM_AGC_SNS_DIR_STP__A
, 1);
3227 status
= write16(state
, SCU_RAM_AGC_SNS_CYCLEN__A
, 500);
3230 status
= write16(state
, SCU_RAM_AGC_KI_CYCLEN__A
, 500);
3234 /* Initialize inner-loop KI gain factors */
3235 status
= read16(state
, SCU_RAM_AGC_KI__A
, &data
);
3240 data
&= ~SCU_RAM_AGC_KI_RF__M
;
3241 data
|= (DRXK_KI_RAGC_QAM
<< SCU_RAM_AGC_KI_RF__B
);
3242 data
&= ~SCU_RAM_AGC_KI_IF__M
;
3243 data
|= (DRXK_KI_IAGC_QAM
<< SCU_RAM_AGC_KI_IF__B
);
3245 status
= write16(state
, SCU_RAM_AGC_KI__A
, data
);
3248 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3252 static int DVBTQAMGetAccPktErr(struct drxk_state
*state
, u16
*packetErr
)
3257 if (packetErr
== NULL
)
3258 status
= write16(state
, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A
, 0);
3260 status
= read16(state
, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A
, packetErr
);
3262 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3266 static int DVBTScCommand(struct drxk_state
*state
,
3267 u16 cmd
, u16 subcmd
,
3268 u16 param0
, u16 param1
, u16 param2
,
3269 u16 param3
, u16 param4
)
3278 status
= read16(state
, OFDM_SC_COMM_EXEC__A
, &scExec
);
3280 /* SC is not running */
3286 /* Wait until sc is ready to receive command */
3290 status
= read16(state
, OFDM_SC_RA_RAM_CMD__A
, &curCmd
);
3292 } while ((curCmd
!= 0) && (retryCnt
< DRXK_MAX_RETRIES
));
3293 if (retryCnt
>= DRXK_MAX_RETRIES
&& (status
< 0))
3296 /* Write sub-command */
3298 /* All commands using sub-cmd */
3299 case OFDM_SC_RA_RAM_CMD_PROC_START
:
3300 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM
:
3301 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM
:
3302 status
= write16(state
, OFDM_SC_RA_RAM_CMD_ADDR__A
, subcmd
);
3311 /* Write needed parameters and the command */
3313 /* All commands using 5 parameters */
3314 /* All commands using 4 parameters */
3315 /* All commands using 3 parameters */
3316 /* All commands using 2 parameters */
3317 case OFDM_SC_RA_RAM_CMD_PROC_START
:
3318 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM
:
3319 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM
:
3320 status
= write16(state
, OFDM_SC_RA_RAM_PARAM1__A
, param1
);
3321 /* All commands using 1 parameters */
3322 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING
:
3323 case OFDM_SC_RA_RAM_CMD_USER_IO
:
3324 status
= write16(state
, OFDM_SC_RA_RAM_PARAM0__A
, param0
);
3325 /* All commands using 0 parameters */
3326 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM
:
3327 case OFDM_SC_RA_RAM_CMD_NULL
:
3329 status
= write16(state
, OFDM_SC_RA_RAM_CMD__A
, cmd
);
3332 /* Unknown command */
3338 /* Wait until sc is ready processing command */
3342 status
= read16(state
, OFDM_SC_RA_RAM_CMD__A
, &curCmd
);
3344 } while ((curCmd
!= 0) && (retryCnt
< DRXK_MAX_RETRIES
));
3345 if (retryCnt
>= DRXK_MAX_RETRIES
&& (status
< 0))
3348 /* Check for illegal cmd */
3349 status
= read16(state
, OFDM_SC_RA_RAM_CMD_ADDR__A
, &errCode
);
3350 if (errCode
== 0xFFFF) {
3351 /* illegal command */
3357 /* Retreive results parameters from SC */
3359 /* All commands yielding 5 results */
3360 /* All commands yielding 4 results */
3361 /* All commands yielding 3 results */
3362 /* All commands yielding 2 results */
3363 /* All commands yielding 1 result */
3364 case OFDM_SC_RA_RAM_CMD_USER_IO
:
3365 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM
:
3366 status
= read16(state
, OFDM_SC_RA_RAM_PARAM0__A
, &(param0
));
3367 /* All commands yielding 0 results */
3368 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING
:
3369 case OFDM_SC_RA_RAM_CMD_SET_TIMER
:
3370 case OFDM_SC_RA_RAM_CMD_PROC_START
:
3371 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM
:
3372 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM
:
3373 case OFDM_SC_RA_RAM_CMD_NULL
:
3376 /* Unknown command */
3379 } /* switch (cmd->cmd) */
3382 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3386 static int PowerUpDVBT(struct drxk_state
*state
)
3388 enum DRXPowerMode powerMode
= DRX_POWER_UP
;
3392 status
= CtrlPowerMode(state
, &powerMode
);
3394 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3398 static int DVBTCtrlSetIncEnable(struct drxk_state
*state
, bool *enabled
)
3403 if (*enabled
== true)
3404 status
= write16(state
, IQM_CF_BYPASSDET__A
, 0);
3406 status
= write16(state
, IQM_CF_BYPASSDET__A
, 1);
3408 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3412 #define DEFAULT_FR_THRES_8K 4000
3413 static int DVBTCtrlSetFrEnable(struct drxk_state
*state
, bool *enabled
)
3419 if (*enabled
== true) {
3420 /* write mask to 1 */
3421 status
= write16(state
, OFDM_SC_RA_RAM_FR_THRES_8K__A
,
3422 DEFAULT_FR_THRES_8K
);
3424 /* write mask to 0 */
3425 status
= write16(state
, OFDM_SC_RA_RAM_FR_THRES_8K__A
, 0);
3428 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3433 static int DVBTCtrlSetEchoThreshold(struct drxk_state
*state
,
3434 struct DRXKCfgDvbtEchoThres_t
*echoThres
)
3440 status
= read16(state
, OFDM_SC_RA_RAM_ECHO_THRES__A
, &data
);
3444 switch (echoThres
->fftMode
) {
3445 case DRX_FFTMODE_2K
:
3446 data
&= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M
;
3447 data
|= ((echoThres
->threshold
<<
3448 OFDM_SC_RA_RAM_ECHO_THRES_2K__B
)
3449 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M
));
3451 case DRX_FFTMODE_8K
:
3452 data
&= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M
;
3453 data
|= ((echoThres
->threshold
<<
3454 OFDM_SC_RA_RAM_ECHO_THRES_8K__B
)
3455 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M
));
3461 status
= write16(state
, OFDM_SC_RA_RAM_ECHO_THRES__A
, data
);
3464 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3468 static int DVBTCtrlSetSqiSpeed(struct drxk_state
*state
,
3469 enum DRXKCfgDvbtSqiSpeed
*speed
)
3471 int status
= -EINVAL
;
3476 case DRXK_DVBT_SQI_SPEED_FAST
:
3477 case DRXK_DVBT_SQI_SPEED_MEDIUM
:
3478 case DRXK_DVBT_SQI_SPEED_SLOW
:
3483 status
= write16(state
, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A
,
3487 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3491 /*============================================================================*/
3494 * \brief Activate DVBT specific presets
3495 * \param demod instance of demodulator.
3496 * \return DRXStatus_t.
3498 * Called in DVBTSetStandard
3501 static int DVBTActivatePresets(struct drxk_state
*state
)
3504 bool setincenable
= false;
3505 bool setfrenable
= true;
3507 struct DRXKCfgDvbtEchoThres_t echoThres2k
= { 0, DRX_FFTMODE_2K
};
3508 struct DRXKCfgDvbtEchoThres_t echoThres8k
= { 0, DRX_FFTMODE_8K
};
3511 status
= DVBTCtrlSetIncEnable(state
, &setincenable
);
3514 status
= DVBTCtrlSetFrEnable(state
, &setfrenable
);
3517 status
= DVBTCtrlSetEchoThreshold(state
, &echoThres2k
);
3520 status
= DVBTCtrlSetEchoThreshold(state
, &echoThres8k
);
3523 status
= write16(state
, SCU_RAM_AGC_INGAIN_TGT_MAX__A
, state
->m_dvbtIfAgcCfg
.IngainTgtMax
);
3526 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3530 /*============================================================================*/
3533 * \brief Initialize channelswitch-independent settings for DVBT.
3534 * \param demod instance of demodulator.
3535 * \return DRXStatus_t.
3537 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3538 * the DVB-T taps from the drxk_filters.h are used.
3540 static int SetDVBTStandard(struct drxk_state
*state
,
3541 enum OperationMode oMode
)
3550 /* added antenna switch */
3551 SwitchAntennaToDVBT(state
);
3552 /* send OFDM reset command */
3553 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_RESET
, 0, NULL
, 1, &cmdResult
);
3557 /* send OFDM setenv command */
3558 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV
, 0, NULL
, 1, &cmdResult
);
3562 /* reset datapath for OFDM, processors first */
3563 status
= write16(state
, OFDM_SC_COMM_EXEC__A
, OFDM_SC_COMM_EXEC_STOP
);
3566 status
= write16(state
, OFDM_LC_COMM_EXEC__A
, OFDM_LC_COMM_EXEC_STOP
);
3569 status
= write16(state
, IQM_COMM_EXEC__A
, IQM_COMM_EXEC_B_STOP
);
3574 /* synchronize on ofdstate->m_festart */
3575 status
= write16(state
, IQM_AF_UPD_SEL__A
, 1);
3578 /* window size for clipping ADC detection */
3579 status
= write16(state
, IQM_AF_CLP_LEN__A
, 0);
3582 /* window size for for sense pre-SAW detection */
3583 status
= write16(state
, IQM_AF_SNS_LEN__A
, 0);
3586 /* sense threshold for sense pre-SAW detection */
3587 status
= write16(state
, IQM_AF_AMUX__A
, IQM_AF_AMUX_SIGNAL2ADC
);
3590 status
= SetIqmAf(state
, true);
3594 status
= write16(state
, IQM_AF_AGC_RF__A
, 0);
3598 /* Impulse noise cruncher setup */
3599 status
= write16(state
, IQM_AF_INC_LCT__A
, 0); /* crunch in IQM_CF */
3602 status
= write16(state
, IQM_CF_DET_LCT__A
, 0); /* detect in IQM_CF */
3605 status
= write16(state
, IQM_CF_WND_LEN__A
, 3); /* peak detector window length */
3609 status
= write16(state
, IQM_RC_STRETCH__A
, 16);
3612 status
= write16(state
, IQM_CF_OUT_ENA__A
, 0x4); /* enable output 2 */
3615 status
= write16(state
, IQM_CF_DS_ENA__A
, 0x4); /* decimate output 2 */
3618 status
= write16(state
, IQM_CF_SCALE__A
, 1600);
3621 status
= write16(state
, IQM_CF_SCALE_SH__A
, 0);
3625 /* virtual clipping threshold for clipping ADC detection */
3626 status
= write16(state
, IQM_AF_CLP_TH__A
, 448);
3629 status
= write16(state
, IQM_CF_DATATH__A
, 495); /* crunching threshold */
3633 status
= BLChainCmd(state
, DRXK_BL_ROM_OFFSET_TAPS_DVBT
, DRXK_BLCC_NR_ELEMENTS_TAPS
, DRXK_BLC_TIMEOUT
);
3637 status
= write16(state
, IQM_CF_PKDTH__A
, 2); /* peak detector threshold */
3640 status
= write16(state
, IQM_CF_POW_MEAS_LEN__A
, 2);
3643 /* enable power measurement interrupt */
3644 status
= write16(state
, IQM_CF_COMM_INT_MSK__A
, 1);
3647 status
= write16(state
, IQM_COMM_EXEC__A
, IQM_COMM_EXEC_B_ACTIVE
);
3651 /* IQM will not be reset from here, sync ADC and update/init AGC */
3652 status
= ADCSynchronization(state
);
3655 status
= SetPreSaw(state
, &state
->m_dvbtPreSawCfg
);
3659 /* Halt SCU to enable safe non-atomic accesses */
3660 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_HOLD
);
3664 status
= SetAgcRf(state
, &state
->m_dvbtRfAgcCfg
, true);
3667 status
= SetAgcIf(state
, &state
->m_dvbtIfAgcCfg
, true);
3671 /* Set Noise Estimation notch width and enable DC fix */
3672 status
= read16(state
, OFDM_SC_RA_RAM_CONFIG__A
, &data
);
3675 data
|= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M
;
3676 status
= write16(state
, OFDM_SC_RA_RAM_CONFIG__A
, data
);
3680 /* Activate SCU to enable SCU commands */
3681 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_ACTIVE
);
3685 if (!state
->m_DRXK_A3_ROM_CODE
) {
3686 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3687 status
= write16(state
, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A
, state
->m_dvbtIfAgcCfg
.FastClipCtrlDelay
);
3693 #ifdef COMPILE_FOR_NONRT
3694 status
= write16(state
, OFDM_SC_RA_RAM_BE_OPT_DELAY__A
, 1);
3697 status
= write16(state
, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A
, 2);
3703 status
= write16(state
, FEC_DI_INPUT_CTL__A
, 1); /* OFDM input */
3708 #ifdef COMPILE_FOR_NONRT
3709 status
= write16(state
, FEC_RS_MEASUREMENT_PERIOD__A
, 0x400);
3713 status
= write16(state
, FEC_RS_MEASUREMENT_PERIOD__A
, 0x1000);
3717 status
= write16(state
, FEC_RS_MEASUREMENT_PRESCALE__A
, 0x0001);
3721 /* Setup MPEG bus */
3722 status
= MPEGTSDtoSetup(state
, OM_DVBT
);
3725 /* Set DVBT Presets */
3726 status
= DVBTActivatePresets(state
);
3732 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3736 /*============================================================================*/
3738 * \brief Start dvbt demodulating for channel.
3739 * \param demod instance of demodulator.
3740 * \return DRXStatus_t.
3742 static int DVBTStart(struct drxk_state
*state
)
3746 /* DRXKOfdmScCmd_t scCmd; */
3749 /* Start correct processes to get in lock */
3750 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3751 param1
= OFDM_SC_RA_RAM_LOCKTRACK_MIN
;
3752 status
= DVBTScCommand(state
, OFDM_SC_RA_RAM_CMD_PROC_START
, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M
, param1
, 0, 0, 0);
3756 status
= MPEGTSStart(state
);
3759 status
= write16(state
, FEC_COMM_EXEC__A
, FEC_COMM_EXEC_ACTIVE
);
3764 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
3769 /*============================================================================*/
3772 * \brief Set up dvbt demodulator for channel.
3773 * \param demod instance of demodulator.
3774 * \return DRXStatus_t.
3775 * // original DVBTSetChannel()
3777 static int SetDVBT(struct drxk_state
*state
, u16 IntermediateFreqkHz
,
3778 s32 tunerFreqOffset
)
3781 u16 transmissionParams
= 0;
3782 u16 operationMode
= 0;
3783 u32 iqmRcRateOfs
= 0;
3788 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz
, tunerFreqOffset
);
3790 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_STOP
, 0, NULL
, 1, &cmdResult
);
3794 /* Halt SCU to enable safe non-atomic accesses */
3795 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_HOLD
);
3799 /* Stop processors */
3800 status
= write16(state
, OFDM_SC_COMM_EXEC__A
, OFDM_SC_COMM_EXEC_STOP
);
3803 status
= write16(state
, OFDM_LC_COMM_EXEC__A
, OFDM_LC_COMM_EXEC_STOP
);
3807 /* Mandatory fix, always stop CP, required to set spl offset back to
3808 hardware default (is set to 0 by ucode during pilot detection */
3809 status
= write16(state
, OFDM_CP_COMM_EXEC__A
, OFDM_CP_COMM_EXEC_STOP
);
3813 /*== Write channel settings to device =====================================*/
3816 switch (state
->param
.u
.ofdm
.transmission_mode
) {
3817 case TRANSMISSION_MODE_AUTO
:
3819 operationMode
|= OFDM_SC_RA_RAM_OP_AUTO_MODE__M
;
3820 /* fall through , try first guess DRX_FFTMODE_8K */
3821 case TRANSMISSION_MODE_8K
:
3822 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K
;
3824 case TRANSMISSION_MODE_2K
:
3825 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K
;
3830 switch (state
->param
.u
.ofdm
.guard_interval
) {
3832 case GUARD_INTERVAL_AUTO
:
3833 operationMode
|= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M
;
3834 /* fall through , try first guess DRX_GUARD_1DIV4 */
3835 case GUARD_INTERVAL_1_4
:
3836 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4
;
3838 case GUARD_INTERVAL_1_32
:
3839 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32
;
3841 case GUARD_INTERVAL_1_16
:
3842 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16
;
3844 case GUARD_INTERVAL_1_8
:
3845 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8
;
3850 switch (state
->param
.u
.ofdm
.hierarchy_information
) {
3851 case HIERARCHY_AUTO
:
3852 case HIERARCHY_NONE
:
3854 operationMode
|= OFDM_SC_RA_RAM_OP_AUTO_HIER__M
;
3855 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3856 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3859 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1
;
3862 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2
;
3865 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4
;
3871 switch (state
->param
.u
.ofdm
.constellation
) {
3874 operationMode
|= OFDM_SC_RA_RAM_OP_AUTO_CONST__M
;
3875 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3877 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64
;
3880 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK
;
3883 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16
;
3887 /* No hierachical channels support in BDA */
3888 /* Priority (only for hierarchical channels) */
3889 switch (channel
->priority
) {
3890 case DRX_PRIORITY_LOW
:
3891 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO
;
3892 WR16(devAddr
, OFDM_EC_SB_PRIOR__A
,
3893 OFDM_EC_SB_PRIOR_LO
);
3895 case DRX_PRIORITY_HIGH
:
3896 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI
;
3897 WR16(devAddr
, OFDM_EC_SB_PRIOR__A
,
3898 OFDM_EC_SB_PRIOR_HI
));
3900 case DRX_PRIORITY_UNKNOWN
: /* fall through */
3906 /* Set Priorty high */
3907 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI
;
3908 status
= write16(state
, OFDM_EC_SB_PRIOR__A
, OFDM_EC_SB_PRIOR_HI
);
3914 switch (state
->param
.u
.ofdm
.code_rate_HP
) {
3917 operationMode
|= OFDM_SC_RA_RAM_OP_AUTO_RATE__M
;
3918 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3920 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3
;
3923 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2
;
3926 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4
;
3929 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6
;
3932 transmissionParams
|= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8
;
3936 /* SAW filter selection: normaly not necesarry, but if wanted
3937 the application can select a SAW filter via the driver by using UIOs */
3938 /* First determine real bandwidth (Hz) */
3939 /* Also set delay for impulse noise cruncher */
3940 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3941 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3943 switch (state
->param
.u
.ofdm
.bandwidth
) {
3944 case BANDWIDTH_AUTO
:
3945 case BANDWIDTH_8_MHZ
:
3946 bandwidth
= DRXK_BANDWIDTH_8MHZ_IN_HZ
;
3947 status
= write16(state
, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A
, 3052);
3950 /* cochannel protection for PAL 8 MHz */
3951 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A
, 7);
3954 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A
, 7);
3957 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A
, 7);
3960 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A
, 1);
3964 case BANDWIDTH_7_MHZ
:
3965 bandwidth
= DRXK_BANDWIDTH_7MHZ_IN_HZ
;
3966 status
= write16(state
, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A
, 3491);
3969 /* cochannel protection for PAL 7 MHz */
3970 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A
, 8);
3973 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A
, 8);
3976 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A
, 4);
3979 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A
, 1);
3983 case BANDWIDTH_6_MHZ
:
3984 bandwidth
= DRXK_BANDWIDTH_6MHZ_IN_HZ
;
3985 status
= write16(state
, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A
, 4073);
3988 /* cochannel protection for NTSC 6 MHz */
3989 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A
, 19);
3992 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A
, 19);
3995 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A
, 14);
3998 status
= write16(state
, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A
, 1);
4007 if (iqmRcRateOfs
== 0) {
4008 /* Now compute IQM_RC_RATE_OFS
4009 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4011 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4013 /* (SysFreq / BandWidth) * (2^28) */
4014 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4015 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4016 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4017 iqmRcRateOfs
= Frac28a((u32
)
4018 ((state
->m_sysClockFreq
*
4019 1000) / 3), bandwidth
);
4020 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4021 if ((iqmRcRateOfs
& 0x7fL
) >= 0x40)
4022 iqmRcRateOfs
+= 0x80L
;
4023 iqmRcRateOfs
= iqmRcRateOfs
>> 7;
4024 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4025 iqmRcRateOfs
= iqmRcRateOfs
- (1 << 23);
4029 ((((u32
) IQM_RC_RATE_OFS_HI__M
) <<
4030 IQM_RC_RATE_OFS_LO__W
) | IQM_RC_RATE_OFS_LO__M
);
4031 status
= write32(state
, IQM_RC_RATE_OFS_LO__A
, iqmRcRateOfs
);
4035 /* Bandwidth setting done */
4038 status
= DVBTSetFrequencyShift(demod
, channel
, tunerOffset
);
4042 status
= SetFrequencyShifter(state
, IntermediateFreqkHz
, tunerFreqOffset
, true);
4046 /*== Start SC, write channel settings to SC ===============================*/
4048 /* Activate SCU to enable SCU commands */
4049 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_ACTIVE
);
4053 /* Enable SC after setting all other parameters */
4054 status
= write16(state
, OFDM_SC_COMM_STATE__A
, 0);
4057 status
= write16(state
, OFDM_SC_COMM_EXEC__A
, 1);
4062 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_OFDM
| SCU_RAM_COMMAND_CMD_DEMOD_START
, 0, NULL
, 1, &cmdResult
);
4066 /* Write SC parameter registers, set all AUTO flags in operation mode */
4067 param1
= (OFDM_SC_RA_RAM_OP_AUTO_MODE__M
|
4068 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M
|
4069 OFDM_SC_RA_RAM_OP_AUTO_CONST__M
|
4070 OFDM_SC_RA_RAM_OP_AUTO_HIER__M
|
4071 OFDM_SC_RA_RAM_OP_AUTO_RATE__M
);
4072 status
= DVBTScCommand(state
, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM
,
4073 0, transmissionParams
, param1
, 0, 0, 0);
4077 if (!state
->m_DRXK_A3_ROM_CODE
)
4078 status
= DVBTCtrlSetSqiSpeed(state
, &state
->m_sqiSpeed
);
4081 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
4087 /*============================================================================*/
4090 * \brief Retreive lock status .
4091 * \param demod Pointer to demodulator instance.
4092 * \param lockStat Pointer to lock status structure.
4093 * \return DRXStatus_t.
4096 static int GetDVBTLockStatus(struct drxk_state
*state
, u32
*pLockStatus
)
4099 const u16 mpeg_lock_mask
= (OFDM_SC_RA_RAM_LOCK_MPEG__M
|
4100 OFDM_SC_RA_RAM_LOCK_FEC__M
);
4101 const u16 fec_lock_mask
= (OFDM_SC_RA_RAM_LOCK_FEC__M
);
4102 const u16 demod_lock_mask
= OFDM_SC_RA_RAM_LOCK_DEMOD__M
;
4104 u16 ScRaRamLock
= 0;
4109 *pLockStatus
= NOT_LOCKED
;
4111 /* Check if SC is running */
4112 status
= read16(state
, OFDM_SC_COMM_EXEC__A
, &ScCommExec
);
4115 if (ScCommExec
== OFDM_SC_COMM_EXEC_STOP
)
4118 status
= read16(state
, OFDM_SC_RA_RAM_LOCK__A
, &ScRaRamLock
);
4122 if ((ScRaRamLock
& mpeg_lock_mask
) == mpeg_lock_mask
)
4123 *pLockStatus
= MPEG_LOCK
;
4124 else if ((ScRaRamLock
& fec_lock_mask
) == fec_lock_mask
)
4125 *pLockStatus
= FEC_LOCK
;
4126 else if ((ScRaRamLock
& demod_lock_mask
) == demod_lock_mask
)
4127 *pLockStatus
= DEMOD_LOCK
;
4128 else if (ScRaRamLock
& OFDM_SC_RA_RAM_LOCK_NODVBT__M
)
4129 *pLockStatus
= NEVER_LOCK
;
4132 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
4137 static int PowerUpQAM(struct drxk_state
*state
)
4139 enum DRXPowerMode powerMode
= DRXK_POWER_DOWN_OFDM
;
4143 status
= CtrlPowerMode(state
, &powerMode
);
4145 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
4151 /** Power Down QAM */
4152 static int PowerDownQAM(struct drxk_state
*state
)
4159 status
= read16(state
, SCU_COMM_EXEC__A
, &data
);
4162 if (data
== SCU_COMM_EXEC_ACTIVE
) {
4167 /* stop all comstate->m_exec */
4168 status
= write16(state
, QAM_COMM_EXEC__A
, QAM_COMM_EXEC_STOP
);
4171 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_STOP
, 0, NULL
, 1, &cmdResult
);
4176 status
= SetIqmAf(state
, false);
4180 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
4185 /*============================================================================*/
4188 * \brief Setup of the QAM Measurement intervals for signal quality
4189 * \param demod instance of demod.
4190 * \param constellation current constellation.
4191 * \return DRXStatus_t.
4194 * Take into account that for certain settings the errorcounters can overflow.
4195 * The implementation does not check this.
4198 static int SetQAMMeasurement(struct drxk_state
*state
,
4199 enum EDrxkConstellation constellation
,
4202 u32 fecBitsDesired
= 0; /* BER accounting period */
4203 u32 fecRsPeriodTotal
= 0; /* Total period */
4204 u16 fecRsPrescale
= 0; /* ReedSolomon Measurement Prescale */
4205 u16 fecRsPeriod
= 0; /* Value for corresponding I2C register */
4211 /* fecBitsDesired = symbolRate [kHz] *
4213 (constellation + 1) *
4217 switch (constellation
) {
4218 case DRX_CONSTELLATION_QAM16
:
4219 fecBitsDesired
= 4 * symbolRate
;
4221 case DRX_CONSTELLATION_QAM32
:
4222 fecBitsDesired
= 5 * symbolRate
;
4224 case DRX_CONSTELLATION_QAM64
:
4225 fecBitsDesired
= 6 * symbolRate
;
4227 case DRX_CONSTELLATION_QAM128
:
4228 fecBitsDesired
= 7 * symbolRate
;
4230 case DRX_CONSTELLATION_QAM256
:
4231 fecBitsDesired
= 8 * symbolRate
;
4239 fecBitsDesired
/= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4240 fecBitsDesired
*= 500; /* meas. period [ms] */
4242 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4243 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4244 fecRsPeriodTotal
= (fecBitsDesired
/ 1632UL) + 1; /* roughly ceil */
4246 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4247 fecRsPrescale
= 1 + (u16
) (fecRsPeriodTotal
>> 16);
4248 if (fecRsPrescale
== 0) {
4249 /* Divide by zero (though impossible) */
4255 ((u16
) fecRsPeriodTotal
+
4256 (fecRsPrescale
>> 1)) / fecRsPrescale
;
4258 /* write corresponding registers */
4259 status
= write16(state
, FEC_RS_MEASUREMENT_PERIOD__A
, fecRsPeriod
);
4262 status
= write16(state
, FEC_RS_MEASUREMENT_PRESCALE__A
, fecRsPrescale
);
4265 status
= write16(state
, FEC_OC_SNC_FAIL_PERIOD__A
, fecRsPeriod
);
4268 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
4272 static int SetQAM16(struct drxk_state
*state
)
4277 /* QAM Equalizer Setup */
4279 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD0__A
, 13517);
4282 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD1__A
, 13517);
4285 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD2__A
, 13517);
4288 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD3__A
, 13517);
4291 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD4__A
, 13517);
4294 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD5__A
, 13517);
4297 /* Decision Feedback Equalizer */
4298 status
= write16(state
, QAM_DQ_QUAL_FUN0__A
, 2);
4301 status
= write16(state
, QAM_DQ_QUAL_FUN1__A
, 2);
4304 status
= write16(state
, QAM_DQ_QUAL_FUN2__A
, 2);
4307 status
= write16(state
, QAM_DQ_QUAL_FUN3__A
, 2);
4310 status
= write16(state
, QAM_DQ_QUAL_FUN4__A
, 2);
4313 status
= write16(state
, QAM_DQ_QUAL_FUN5__A
, 0);
4317 status
= write16(state
, QAM_SY_SYNC_HWM__A
, 5);
4320 status
= write16(state
, QAM_SY_SYNC_AWM__A
, 4);
4323 status
= write16(state
, QAM_SY_SYNC_LWM__A
, 3);
4327 /* QAM Slicer Settings */
4328 status
= write16(state
, SCU_RAM_QAM_SL_SIG_POWER__A
, DRXK_QAM_SL_SIG_POWER_QAM16
);
4332 /* QAM Loop Controller Coeficients */
4333 status
= write16(state
, SCU_RAM_QAM_LC_CA_FINE__A
, 15);
4336 status
= write16(state
, SCU_RAM_QAM_LC_CA_COARSE__A
, 40);
4339 status
= write16(state
, SCU_RAM_QAM_LC_EP_FINE__A
, 12);
4342 status
= write16(state
, SCU_RAM_QAM_LC_EP_MEDIUM__A
, 24);
4345 status
= write16(state
, SCU_RAM_QAM_LC_EP_COARSE__A
, 24);
4348 status
= write16(state
, SCU_RAM_QAM_LC_EI_FINE__A
, 12);
4351 status
= write16(state
, SCU_RAM_QAM_LC_EI_MEDIUM__A
, 16);
4354 status
= write16(state
, SCU_RAM_QAM_LC_EI_COARSE__A
, 16);
4358 status
= write16(state
, SCU_RAM_QAM_LC_CP_FINE__A
, 5);
4361 status
= write16(state
, SCU_RAM_QAM_LC_CP_MEDIUM__A
, 20);
4364 status
= write16(state
, SCU_RAM_QAM_LC_CP_COARSE__A
, 80);
4367 status
= write16(state
, SCU_RAM_QAM_LC_CI_FINE__A
, 5);
4370 status
= write16(state
, SCU_RAM_QAM_LC_CI_MEDIUM__A
, 20);
4373 status
= write16(state
, SCU_RAM_QAM_LC_CI_COARSE__A
, 50);
4376 status
= write16(state
, SCU_RAM_QAM_LC_CF_FINE__A
, 16);
4379 status
= write16(state
, SCU_RAM_QAM_LC_CF_MEDIUM__A
, 16);
4382 status
= write16(state
, SCU_RAM_QAM_LC_CF_COARSE__A
, 32);
4385 status
= write16(state
, SCU_RAM_QAM_LC_CF1_FINE__A
, 5);
4388 status
= write16(state
, SCU_RAM_QAM_LC_CF1_MEDIUM__A
, 10);
4391 status
= write16(state
, SCU_RAM_QAM_LC_CF1_COARSE__A
, 10);
4396 /* QAM State Machine (FSM) Thresholds */
4398 status
= write16(state
, SCU_RAM_QAM_FSM_RTH__A
, 140);
4401 status
= write16(state
, SCU_RAM_QAM_FSM_FTH__A
, 50);
4404 status
= write16(state
, SCU_RAM_QAM_FSM_CTH__A
, 95);
4407 status
= write16(state
, SCU_RAM_QAM_FSM_PTH__A
, 120);
4410 status
= write16(state
, SCU_RAM_QAM_FSM_QTH__A
, 230);
4413 status
= write16(state
, SCU_RAM_QAM_FSM_MTH__A
, 105);
4417 status
= write16(state
, SCU_RAM_QAM_FSM_RATE_LIM__A
, 40);
4420 status
= write16(state
, SCU_RAM_QAM_FSM_COUNT_LIM__A
, 4);
4423 status
= write16(state
, SCU_RAM_QAM_FSM_FREQ_LIM__A
, 24);
4428 /* QAM FSM Tracking Parameters */
4430 status
= write16(state
, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A
, (u16
) 16);
4433 status
= write16(state
, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A
, (u16
) 220);
4436 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A
, (u16
) 25);
4439 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A
, (u16
) 6);
4442 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A
, (u16
) -24);
4445 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A
, (u16
) -65);
4448 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A
, (u16
) -127);
4454 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
4458 /*============================================================================*/
4461 * \brief QAM32 specific setup
4462 * \param demod instance of demod.
4463 * \return DRXStatus_t.
4465 static int SetQAM32(struct drxk_state
*state
)
4471 /* QAM Equalizer Setup */
4473 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD0__A
, 6707);
4476 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD1__A
, 6707);
4479 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD2__A
, 6707);
4482 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD3__A
, 6707);
4485 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD4__A
, 6707);
4488 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD5__A
, 6707);
4492 /* Decision Feedback Equalizer */
4493 status
= write16(state
, QAM_DQ_QUAL_FUN0__A
, 3);
4496 status
= write16(state
, QAM_DQ_QUAL_FUN1__A
, 3);
4499 status
= write16(state
, QAM_DQ_QUAL_FUN2__A
, 3);
4502 status
= write16(state
, QAM_DQ_QUAL_FUN3__A
, 3);
4505 status
= write16(state
, QAM_DQ_QUAL_FUN4__A
, 3);
4508 status
= write16(state
, QAM_DQ_QUAL_FUN5__A
, 0);
4512 status
= write16(state
, QAM_SY_SYNC_HWM__A
, 6);
4515 status
= write16(state
, QAM_SY_SYNC_AWM__A
, 5);
4518 status
= write16(state
, QAM_SY_SYNC_LWM__A
, 3);
4522 /* QAM Slicer Settings */
4524 status
= write16(state
, SCU_RAM_QAM_SL_SIG_POWER__A
, DRXK_QAM_SL_SIG_POWER_QAM32
);
4529 /* QAM Loop Controller Coeficients */
4531 status
= write16(state
, SCU_RAM_QAM_LC_CA_FINE__A
, 15);
4534 status
= write16(state
, SCU_RAM_QAM_LC_CA_COARSE__A
, 40);
4537 status
= write16(state
, SCU_RAM_QAM_LC_EP_FINE__A
, 12);
4540 status
= write16(state
, SCU_RAM_QAM_LC_EP_MEDIUM__A
, 24);
4543 status
= write16(state
, SCU_RAM_QAM_LC_EP_COARSE__A
, 24);
4546 status
= write16(state
, SCU_RAM_QAM_LC_EI_FINE__A
, 12);
4549 status
= write16(state
, SCU_RAM_QAM_LC_EI_MEDIUM__A
, 16);
4552 status
= write16(state
, SCU_RAM_QAM_LC_EI_COARSE__A
, 16);
4556 status
= write16(state
, SCU_RAM_QAM_LC_CP_FINE__A
, 5);
4559 status
= write16(state
, SCU_RAM_QAM_LC_CP_MEDIUM__A
, 20);
4562 status
= write16(state
, SCU_RAM_QAM_LC_CP_COARSE__A
, 80);
4565 status
= write16(state
, SCU_RAM_QAM_LC_CI_FINE__A
, 5);
4568 status
= write16(state
, SCU_RAM_QAM_LC_CI_MEDIUM__A
, 20);
4571 status
= write16(state
, SCU_RAM_QAM_LC_CI_COARSE__A
, 50);
4574 status
= write16(state
, SCU_RAM_QAM_LC_CF_FINE__A
, 16);
4577 status
= write16(state
, SCU_RAM_QAM_LC_CF_MEDIUM__A
, 16);
4580 status
= write16(state
, SCU_RAM_QAM_LC_CF_COARSE__A
, 16);
4583 status
= write16(state
, SCU_RAM_QAM_LC_CF1_FINE__A
, 5);
4586 status
= write16(state
, SCU_RAM_QAM_LC_CF1_MEDIUM__A
, 10);
4589 status
= write16(state
, SCU_RAM_QAM_LC_CF1_COARSE__A
, 0);
4594 /* QAM State Machine (FSM) Thresholds */
4596 status
= write16(state
, SCU_RAM_QAM_FSM_RTH__A
, 90);
4599 status
= write16(state
, SCU_RAM_QAM_FSM_FTH__A
, 50);
4602 status
= write16(state
, SCU_RAM_QAM_FSM_CTH__A
, 80);
4605 status
= write16(state
, SCU_RAM_QAM_FSM_PTH__A
, 100);
4608 status
= write16(state
, SCU_RAM_QAM_FSM_QTH__A
, 170);
4611 status
= write16(state
, SCU_RAM_QAM_FSM_MTH__A
, 100);
4615 status
= write16(state
, SCU_RAM_QAM_FSM_RATE_LIM__A
, 40);
4618 status
= write16(state
, SCU_RAM_QAM_FSM_COUNT_LIM__A
, 4);
4621 status
= write16(state
, SCU_RAM_QAM_FSM_FREQ_LIM__A
, 10);
4626 /* QAM FSM Tracking Parameters */
4628 status
= write16(state
, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A
, (u16
) 12);
4631 status
= write16(state
, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A
, (u16
) 140);
4634 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A
, (u16
) -8);
4637 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A
, (u16
) -16);
4640 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A
, (u16
) -26);
4643 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A
, (u16
) -56);
4646 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A
, (u16
) -86);
4649 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
4653 /*============================================================================*/
4656 * \brief QAM64 specific setup
4657 * \param demod instance of demod.
4658 * \return DRXStatus_t.
4660 static int SetQAM64(struct drxk_state
*state
)
4665 /* QAM Equalizer Setup */
4667 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD0__A
, 13336);
4670 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD1__A
, 12618);
4673 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD2__A
, 11988);
4676 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD3__A
, 13809);
4679 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD4__A
, 13809);
4682 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD5__A
, 15609);
4686 /* Decision Feedback Equalizer */
4687 status
= write16(state
, QAM_DQ_QUAL_FUN0__A
, 4);
4690 status
= write16(state
, QAM_DQ_QUAL_FUN1__A
, 4);
4693 status
= write16(state
, QAM_DQ_QUAL_FUN2__A
, 4);
4696 status
= write16(state
, QAM_DQ_QUAL_FUN3__A
, 4);
4699 status
= write16(state
, QAM_DQ_QUAL_FUN4__A
, 3);
4702 status
= write16(state
, QAM_DQ_QUAL_FUN5__A
, 0);
4706 status
= write16(state
, QAM_SY_SYNC_HWM__A
, 5);
4709 status
= write16(state
, QAM_SY_SYNC_AWM__A
, 4);
4712 status
= write16(state
, QAM_SY_SYNC_LWM__A
, 3);
4716 /* QAM Slicer Settings */
4717 status
= write16(state
, SCU_RAM_QAM_SL_SIG_POWER__A
, DRXK_QAM_SL_SIG_POWER_QAM64
);
4722 /* QAM Loop Controller Coeficients */
4724 status
= write16(state
, SCU_RAM_QAM_LC_CA_FINE__A
, 15);
4727 status
= write16(state
, SCU_RAM_QAM_LC_CA_COARSE__A
, 40);
4730 status
= write16(state
, SCU_RAM_QAM_LC_EP_FINE__A
, 12);
4733 status
= write16(state
, SCU_RAM_QAM_LC_EP_MEDIUM__A
, 24);
4736 status
= write16(state
, SCU_RAM_QAM_LC_EP_COARSE__A
, 24);
4739 status
= write16(state
, SCU_RAM_QAM_LC_EI_FINE__A
, 12);
4742 status
= write16(state
, SCU_RAM_QAM_LC_EI_MEDIUM__A
, 16);
4745 status
= write16(state
, SCU_RAM_QAM_LC_EI_COARSE__A
, 16);
4749 status
= write16(state
, SCU_RAM_QAM_LC_CP_FINE__A
, 5);
4752 status
= write16(state
, SCU_RAM_QAM_LC_CP_MEDIUM__A
, 30);
4755 status
= write16(state
, SCU_RAM_QAM_LC_CP_COARSE__A
, 100);
4758 status
= write16(state
, SCU_RAM_QAM_LC_CI_FINE__A
, 5);
4761 status
= write16(state
, SCU_RAM_QAM_LC_CI_MEDIUM__A
, 30);
4764 status
= write16(state
, SCU_RAM_QAM_LC_CI_COARSE__A
, 50);
4767 status
= write16(state
, SCU_RAM_QAM_LC_CF_FINE__A
, 16);
4770 status
= write16(state
, SCU_RAM_QAM_LC_CF_MEDIUM__A
, 25);
4773 status
= write16(state
, SCU_RAM_QAM_LC_CF_COARSE__A
, 48);
4776 status
= write16(state
, SCU_RAM_QAM_LC_CF1_FINE__A
, 5);
4779 status
= write16(state
, SCU_RAM_QAM_LC_CF1_MEDIUM__A
, 10);
4782 status
= write16(state
, SCU_RAM_QAM_LC_CF1_COARSE__A
, 10);
4787 /* QAM State Machine (FSM) Thresholds */
4789 status
= write16(state
, SCU_RAM_QAM_FSM_RTH__A
, 100);
4792 status
= write16(state
, SCU_RAM_QAM_FSM_FTH__A
, 60);
4795 status
= write16(state
, SCU_RAM_QAM_FSM_CTH__A
, 80);
4798 status
= write16(state
, SCU_RAM_QAM_FSM_PTH__A
, 110);
4801 status
= write16(state
, SCU_RAM_QAM_FSM_QTH__A
, 200);
4804 status
= write16(state
, SCU_RAM_QAM_FSM_MTH__A
, 95);
4808 status
= write16(state
, SCU_RAM_QAM_FSM_RATE_LIM__A
, 40);
4811 status
= write16(state
, SCU_RAM_QAM_FSM_COUNT_LIM__A
, 4);
4814 status
= write16(state
, SCU_RAM_QAM_FSM_FREQ_LIM__A
, 15);
4819 /* QAM FSM Tracking Parameters */
4821 status
= write16(state
, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A
, (u16
) 12);
4824 status
= write16(state
, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A
, (u16
) 141);
4827 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A
, (u16
) 7);
4830 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A
, (u16
) 0);
4833 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A
, (u16
) -15);
4836 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A
, (u16
) -45);
4839 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A
, (u16
) -80);
4842 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
4847 /*============================================================================*/
4850 * \brief QAM128 specific setup
4851 * \param demod: instance of demod.
4852 * \return DRXStatus_t.
4854 static int SetQAM128(struct drxk_state
*state
)
4859 /* QAM Equalizer Setup */
4861 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD0__A
, 6564);
4864 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD1__A
, 6598);
4867 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD2__A
, 6394);
4870 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD3__A
, 6409);
4873 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD4__A
, 6656);
4876 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD5__A
, 7238);
4880 /* Decision Feedback Equalizer */
4881 status
= write16(state
, QAM_DQ_QUAL_FUN0__A
, 6);
4884 status
= write16(state
, QAM_DQ_QUAL_FUN1__A
, 6);
4887 status
= write16(state
, QAM_DQ_QUAL_FUN2__A
, 6);
4890 status
= write16(state
, QAM_DQ_QUAL_FUN3__A
, 6);
4893 status
= write16(state
, QAM_DQ_QUAL_FUN4__A
, 5);
4896 status
= write16(state
, QAM_DQ_QUAL_FUN5__A
, 0);
4900 status
= write16(state
, QAM_SY_SYNC_HWM__A
, 6);
4903 status
= write16(state
, QAM_SY_SYNC_AWM__A
, 5);
4906 status
= write16(state
, QAM_SY_SYNC_LWM__A
, 3);
4911 /* QAM Slicer Settings */
4913 status
= write16(state
, SCU_RAM_QAM_SL_SIG_POWER__A
, DRXK_QAM_SL_SIG_POWER_QAM128
);
4918 /* QAM Loop Controller Coeficients */
4920 status
= write16(state
, SCU_RAM_QAM_LC_CA_FINE__A
, 15);
4923 status
= write16(state
, SCU_RAM_QAM_LC_CA_COARSE__A
, 40);
4926 status
= write16(state
, SCU_RAM_QAM_LC_EP_FINE__A
, 12);
4929 status
= write16(state
, SCU_RAM_QAM_LC_EP_MEDIUM__A
, 24);
4932 status
= write16(state
, SCU_RAM_QAM_LC_EP_COARSE__A
, 24);
4935 status
= write16(state
, SCU_RAM_QAM_LC_EI_FINE__A
, 12);
4938 status
= write16(state
, SCU_RAM_QAM_LC_EI_MEDIUM__A
, 16);
4941 status
= write16(state
, SCU_RAM_QAM_LC_EI_COARSE__A
, 16);
4945 status
= write16(state
, SCU_RAM_QAM_LC_CP_FINE__A
, 5);
4948 status
= write16(state
, SCU_RAM_QAM_LC_CP_MEDIUM__A
, 40);
4951 status
= write16(state
, SCU_RAM_QAM_LC_CP_COARSE__A
, 120);
4954 status
= write16(state
, SCU_RAM_QAM_LC_CI_FINE__A
, 5);
4957 status
= write16(state
, SCU_RAM_QAM_LC_CI_MEDIUM__A
, 40);
4960 status
= write16(state
, SCU_RAM_QAM_LC_CI_COARSE__A
, 60);
4963 status
= write16(state
, SCU_RAM_QAM_LC_CF_FINE__A
, 16);
4966 status
= write16(state
, SCU_RAM_QAM_LC_CF_MEDIUM__A
, 25);
4969 status
= write16(state
, SCU_RAM_QAM_LC_CF_COARSE__A
, 64);
4972 status
= write16(state
, SCU_RAM_QAM_LC_CF1_FINE__A
, 5);
4975 status
= write16(state
, SCU_RAM_QAM_LC_CF1_MEDIUM__A
, 10);
4978 status
= write16(state
, SCU_RAM_QAM_LC_CF1_COARSE__A
, 0);
4983 /* QAM State Machine (FSM) Thresholds */
4985 status
= write16(state
, SCU_RAM_QAM_FSM_RTH__A
, 50);
4988 status
= write16(state
, SCU_RAM_QAM_FSM_FTH__A
, 60);
4991 status
= write16(state
, SCU_RAM_QAM_FSM_CTH__A
, 80);
4994 status
= write16(state
, SCU_RAM_QAM_FSM_PTH__A
, 100);
4997 status
= write16(state
, SCU_RAM_QAM_FSM_QTH__A
, 140);
5000 status
= write16(state
, SCU_RAM_QAM_FSM_MTH__A
, 100);
5004 status
= write16(state
, SCU_RAM_QAM_FSM_RATE_LIM__A
, 40);
5007 status
= write16(state
, SCU_RAM_QAM_FSM_COUNT_LIM__A
, 5);
5011 status
= write16(state
, SCU_RAM_QAM_FSM_FREQ_LIM__A
, 12);
5015 /* QAM FSM Tracking Parameters */
5017 status
= write16(state
, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A
, (u16
) 8);
5020 status
= write16(state
, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A
, (u16
) 65);
5023 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A
, (u16
) 5);
5026 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A
, (u16
) 3);
5029 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A
, (u16
) -1);
5032 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A
, (u16
) -12);
5035 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A
, (u16
) -23);
5038 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5043 /*============================================================================*/
5046 * \brief QAM256 specific setup
5047 * \param demod: instance of demod.
5048 * \return DRXStatus_t.
5050 static int SetQAM256(struct drxk_state
*state
)
5055 /* QAM Equalizer Setup */
5057 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD0__A
, 11502);
5060 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD1__A
, 12084);
5063 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD2__A
, 12543);
5066 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD3__A
, 12931);
5069 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD4__A
, 13629);
5072 status
= write16(state
, SCU_RAM_QAM_EQ_CMA_RAD5__A
, 15385);
5076 /* Decision Feedback Equalizer */
5077 status
= write16(state
, QAM_DQ_QUAL_FUN0__A
, 8);
5080 status
= write16(state
, QAM_DQ_QUAL_FUN1__A
, 8);
5083 status
= write16(state
, QAM_DQ_QUAL_FUN2__A
, 8);
5086 status
= write16(state
, QAM_DQ_QUAL_FUN3__A
, 8);
5089 status
= write16(state
, QAM_DQ_QUAL_FUN4__A
, 6);
5092 status
= write16(state
, QAM_DQ_QUAL_FUN5__A
, 0);
5096 status
= write16(state
, QAM_SY_SYNC_HWM__A
, 5);
5099 status
= write16(state
, QAM_SY_SYNC_AWM__A
, 4);
5102 status
= write16(state
, QAM_SY_SYNC_LWM__A
, 3);
5106 /* QAM Slicer Settings */
5108 status
= write16(state
, SCU_RAM_QAM_SL_SIG_POWER__A
, DRXK_QAM_SL_SIG_POWER_QAM256
);
5113 /* QAM Loop Controller Coeficients */
5115 status
= write16(state
, SCU_RAM_QAM_LC_CA_FINE__A
, 15);
5118 status
= write16(state
, SCU_RAM_QAM_LC_CA_COARSE__A
, 40);
5121 status
= write16(state
, SCU_RAM_QAM_LC_EP_FINE__A
, 12);
5124 status
= write16(state
, SCU_RAM_QAM_LC_EP_MEDIUM__A
, 24);
5127 status
= write16(state
, SCU_RAM_QAM_LC_EP_COARSE__A
, 24);
5130 status
= write16(state
, SCU_RAM_QAM_LC_EI_FINE__A
, 12);
5133 status
= write16(state
, SCU_RAM_QAM_LC_EI_MEDIUM__A
, 16);
5136 status
= write16(state
, SCU_RAM_QAM_LC_EI_COARSE__A
, 16);
5140 status
= write16(state
, SCU_RAM_QAM_LC_CP_FINE__A
, 5);
5143 status
= write16(state
, SCU_RAM_QAM_LC_CP_MEDIUM__A
, 50);
5146 status
= write16(state
, SCU_RAM_QAM_LC_CP_COARSE__A
, 250);
5149 status
= write16(state
, SCU_RAM_QAM_LC_CI_FINE__A
, 5);
5152 status
= write16(state
, SCU_RAM_QAM_LC_CI_MEDIUM__A
, 50);
5155 status
= write16(state
, SCU_RAM_QAM_LC_CI_COARSE__A
, 125);
5158 status
= write16(state
, SCU_RAM_QAM_LC_CF_FINE__A
, 16);
5161 status
= write16(state
, SCU_RAM_QAM_LC_CF_MEDIUM__A
, 25);
5164 status
= write16(state
, SCU_RAM_QAM_LC_CF_COARSE__A
, 48);
5167 status
= write16(state
, SCU_RAM_QAM_LC_CF1_FINE__A
, 5);
5170 status
= write16(state
, SCU_RAM_QAM_LC_CF1_MEDIUM__A
, 10);
5173 status
= write16(state
, SCU_RAM_QAM_LC_CF1_COARSE__A
, 10);
5178 /* QAM State Machine (FSM) Thresholds */
5180 status
= write16(state
, SCU_RAM_QAM_FSM_RTH__A
, 50);
5183 status
= write16(state
, SCU_RAM_QAM_FSM_FTH__A
, 60);
5186 status
= write16(state
, SCU_RAM_QAM_FSM_CTH__A
, 80);
5189 status
= write16(state
, SCU_RAM_QAM_FSM_PTH__A
, 100);
5192 status
= write16(state
, SCU_RAM_QAM_FSM_QTH__A
, 150);
5195 status
= write16(state
, SCU_RAM_QAM_FSM_MTH__A
, 110);
5199 status
= write16(state
, SCU_RAM_QAM_FSM_RATE_LIM__A
, 40);
5202 status
= write16(state
, SCU_RAM_QAM_FSM_COUNT_LIM__A
, 4);
5205 status
= write16(state
, SCU_RAM_QAM_FSM_FREQ_LIM__A
, 12);
5210 /* QAM FSM Tracking Parameters */
5212 status
= write16(state
, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A
, (u16
) 8);
5215 status
= write16(state
, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A
, (u16
) 74);
5218 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A
, (u16
) 18);
5221 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A
, (u16
) 13);
5224 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A
, (u16
) 7);
5227 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A
, (u16
) 0);
5230 status
= write16(state
, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A
, (u16
) -8);
5233 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5238 /*============================================================================*/
5240 * \brief Reset QAM block.
5241 * \param demod: instance of demod.
5242 * \param channel: pointer to channel data.
5243 * \return DRXStatus_t.
5245 static int QAMResetQAM(struct drxk_state
*state
)
5251 /* Stop QAM comstate->m_exec */
5252 status
= write16(state
, QAM_COMM_EXEC__A
, QAM_COMM_EXEC_STOP
);
5256 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_RESET
, 0, NULL
, 1, &cmdResult
);
5259 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5263 /*============================================================================*/
5266 * \brief Set QAM symbolrate.
5267 * \param demod: instance of demod.
5268 * \param channel: pointer to channel data.
5269 * \return DRXStatus_t.
5271 static int QAMSetSymbolrate(struct drxk_state
*state
)
5273 u32 adcFrequency
= 0;
5281 /* Select & calculate correct IQM rate */
5282 adcFrequency
= (state
->m_sysClockFreq
* 1000) / 3;
5284 /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */
5285 if (state
->param
.u
.qam
.symbol_rate
<= 1188750)
5287 else if (state
->param
.u
.qam
.symbol_rate
<= 2377500)
5289 else if (state
->param
.u
.qam
.symbol_rate
<= 4755000)
5291 status
= write16(state
, IQM_FD_RATESEL__A
, ratesel
);
5296 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5298 symbFreq
= state
->param
.u
.qam
.symbol_rate
* (1 << ratesel
);
5299 if (symbFreq
== 0) {
5300 /* Divide by zero */
5304 iqmRcRate
= (adcFrequency
/ symbFreq
) * (1 << 21) +
5305 (Frac28a((adcFrequency
% symbFreq
), symbFreq
) >> 7) -
5307 status
= write32(state
, IQM_RC_RATE_OFS_LO__A
, iqmRcRate
);
5310 state
->m_iqmRcRate
= iqmRcRate
;
5312 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5314 symbFreq
= state
->param
.u
.qam
.symbol_rate
;
5315 if (adcFrequency
== 0) {
5316 /* Divide by zero */
5320 lcSymbRate
= (symbFreq
/ adcFrequency
) * (1 << 12) +
5321 (Frac28a((symbFreq
% adcFrequency
), adcFrequency
) >>
5323 if (lcSymbRate
> 511)
5325 status
= write16(state
, QAM_LC_SYMBOL_FREQ__A
, (u16
) lcSymbRate
);
5329 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5333 /*============================================================================*/
5336 * \brief Get QAM lock status.
5337 * \param demod: instance of demod.
5338 * \param channel: pointer to channel data.
5339 * \return DRXStatus_t.
5342 static int GetQAMLockStatus(struct drxk_state
*state
, u32
*pLockStatus
)
5345 u16 Result
[2] = { 0, 0 };
5348 *pLockStatus
= NOT_LOCKED
;
5349 status
= scu_command(state
,
5350 SCU_RAM_COMMAND_STANDARD_QAM
|
5351 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK
, 0, NULL
, 2,
5354 printk(KERN_ERR
"drxk: %s status = %08x\n", __func__
, status
);
5356 if (Result
[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED
) {
5357 /* 0x0000 NOT LOCKED */
5358 } else if (Result
[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED
) {
5359 /* 0x4000 DEMOD LOCKED */
5360 *pLockStatus
= DEMOD_LOCK
;
5361 } else if (Result
[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK
) {
5362 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5363 *pLockStatus
= MPEG_LOCK
;
5365 /* 0xC000 NEVER LOCKED */
5366 /* (system will never be able to lock to the signal) */
5367 /* TODO: check this, intermediate & standard specific lock states are not
5368 taken into account here */
5369 *pLockStatus
= NEVER_LOCK
;
5374 #define QAM_MIRROR__M 0x03
5375 #define QAM_MIRROR_NORMAL 0x00
5376 #define QAM_MIRRORED 0x01
5377 #define QAM_MIRROR_AUTO_ON 0x02
5378 #define QAM_LOCKRANGE__M 0x10
5379 #define QAM_LOCKRANGE_NORMAL 0x10
5381 static int SetQAM(struct drxk_state
*state
, u16 IntermediateFreqkHz
,
5382 s32 tunerFreqOffset
)
5385 u16 setParamParameters
[4] = { 0, 0, 0, 0 };
5390 * STEP 1: reset demodulator
5391 * resets FEC DI and FEC RS
5393 * resets SCU variables
5395 status
= write16(state
, FEC_DI_COMM_EXEC__A
, FEC_DI_COMM_EXEC_STOP
);
5398 status
= write16(state
, FEC_RS_COMM_EXEC__A
, FEC_RS_COMM_EXEC_STOP
);
5401 status
= QAMResetQAM(state
);
5406 * STEP 2: configure demodulator
5407 * -set params; resets IQM,QAM,FEC HW; initializes some
5410 status
= QAMSetSymbolrate(state
);
5415 switch (state
->param
.u
.qam
.modulation
) {
5417 state
->m_Constellation
= DRX_CONSTELLATION_QAM256
;
5421 state
->m_Constellation
= DRX_CONSTELLATION_QAM64
;
5424 state
->m_Constellation
= DRX_CONSTELLATION_QAM16
;
5427 state
->m_Constellation
= DRX_CONSTELLATION_QAM32
;
5430 state
->m_Constellation
= DRX_CONSTELLATION_QAM128
;
5438 setParamParameters
[0] = state
->m_Constellation
; /* constellation */
5439 setParamParameters
[1] = DRXK_QAM_I12_J17
; /* interleave mode */
5440 if (state
->m_OperationMode
== OM_QAM_ITU_C
)
5441 setParamParameters
[2] = QAM_TOP_ANNEX_C
;
5443 setParamParameters
[2] = QAM_TOP_ANNEX_A
;
5444 setParamParameters
[3] |= (QAM_MIRROR_AUTO_ON
);
5445 /* Env parameters */
5446 /* check for LOCKRANGE Extented */
5447 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5449 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM
, 4, setParamParameters
, 1, &cmdResult
);
5451 /* Fall-back to the simpler call */
5452 if (state
->m_OperationMode
== OM_QAM_ITU_C
)
5453 setParamParameters
[0] = QAM_TOP_ANNEX_C
;
5455 setParamParameters
[0] = QAM_TOP_ANNEX_A
;
5456 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV
, 1, setParamParameters
, 1, &cmdResult
);
5460 setParamParameters
[0] = state
->m_Constellation
; /* constellation */
5461 setParamParameters
[1] = DRXK_QAM_I12_J17
; /* interleave mode */
5462 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM
, 2, setParamParameters
, 1, &cmdResult
);
5468 * STEP 3: enable the system in a mode where the ADC provides valid
5469 * signal setup constellation independent registers
5472 status
= SetFrequency(channel
, tunerFreqOffset
));
5476 status
= SetFrequencyShifter(state
, IntermediateFreqkHz
, tunerFreqOffset
, true);
5480 /* Setup BER measurement */
5481 status
= SetQAMMeasurement(state
, state
->m_Constellation
, state
->param
.u
. qam
.symbol_rate
);
5485 /* Reset default values */
5486 status
= write16(state
, IQM_CF_SCALE_SH__A
, IQM_CF_SCALE_SH__PRE
);
5489 status
= write16(state
, QAM_SY_TIMEOUT__A
, QAM_SY_TIMEOUT__PRE
);
5493 /* Reset default LC values */
5494 status
= write16(state
, QAM_LC_RATE_LIMIT__A
, 3);
5497 status
= write16(state
, QAM_LC_LPF_FACTORP__A
, 4);
5500 status
= write16(state
, QAM_LC_LPF_FACTORI__A
, 4);
5503 status
= write16(state
, QAM_LC_MODE__A
, 7);
5507 status
= write16(state
, QAM_LC_QUAL_TAB0__A
, 1);
5510 status
= write16(state
, QAM_LC_QUAL_TAB1__A
, 1);
5513 status
= write16(state
, QAM_LC_QUAL_TAB2__A
, 1);
5516 status
= write16(state
, QAM_LC_QUAL_TAB3__A
, 1);
5519 status
= write16(state
, QAM_LC_QUAL_TAB4__A
, 2);
5522 status
= write16(state
, QAM_LC_QUAL_TAB5__A
, 2);
5525 status
= write16(state
, QAM_LC_QUAL_TAB6__A
, 2);
5528 status
= write16(state
, QAM_LC_QUAL_TAB8__A
, 2);
5531 status
= write16(state
, QAM_LC_QUAL_TAB9__A
, 2);
5534 status
= write16(state
, QAM_LC_QUAL_TAB10__A
, 2);
5537 status
= write16(state
, QAM_LC_QUAL_TAB12__A
, 2);
5540 status
= write16(state
, QAM_LC_QUAL_TAB15__A
, 3);
5543 status
= write16(state
, QAM_LC_QUAL_TAB16__A
, 3);
5546 status
= write16(state
, QAM_LC_QUAL_TAB20__A
, 4);
5549 status
= write16(state
, QAM_LC_QUAL_TAB25__A
, 4);
5553 /* Mirroring, QAM-block starting point not inverted */
5554 status
= write16(state
, QAM_SY_SP_INV__A
, QAM_SY_SP_INV_SPECTRUM_INV_DIS
);
5558 /* Halt SCU to enable safe non-atomic accesses */
5559 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_HOLD
);
5563 /* STEP 4: constellation specific setup */
5564 switch (state
->param
.u
.qam
.modulation
) {
5566 status
= SetQAM16(state
);
5569 status
= SetQAM32(state
);
5573 status
= SetQAM64(state
);
5576 status
= SetQAM128(state
);
5579 status
= SetQAM256(state
);
5588 /* Activate SCU to enable SCU commands */
5589 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_ACTIVE
);
5593 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5594 /* extAttr->currentChannel.constellation = channel->constellation; */
5595 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5596 status
= MPEGTSDtoSetup(state
, state
->m_OperationMode
);
5600 /* Start processes */
5601 status
= MPEGTSStart(state
);
5604 status
= write16(state
, FEC_COMM_EXEC__A
, FEC_COMM_EXEC_ACTIVE
);
5607 status
= write16(state
, QAM_COMM_EXEC__A
, QAM_COMM_EXEC_ACTIVE
);
5610 status
= write16(state
, IQM_COMM_EXEC__A
, IQM_COMM_EXEC_B_ACTIVE
);
5614 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5615 status
= scu_command(state
, SCU_RAM_COMMAND_STANDARD_QAM
| SCU_RAM_COMMAND_CMD_DEMOD_START
, 0, NULL
, 1, &cmdResult
);
5619 /* update global DRXK data container */
5620 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5624 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5628 static int SetQAMStandard(struct drxk_state
*state
,
5629 enum OperationMode oMode
)
5632 #ifdef DRXK_QAM_TAPS
5633 #define DRXK_QAMA_TAPS_SELECT
5634 #include "drxk_filters.h"
5635 #undef DRXK_QAMA_TAPS_SELECT
5640 /* added antenna switch */
5641 SwitchAntennaToQAM(state
);
5643 /* Ensure correct power-up mode */
5644 status
= PowerUpQAM(state
);
5647 /* Reset QAM block */
5648 status
= QAMResetQAM(state
);
5654 status
= write16(state
, IQM_COMM_EXEC__A
, IQM_COMM_EXEC_B_STOP
);
5657 status
= write16(state
, IQM_AF_AMUX__A
, IQM_AF_AMUX_SIGNAL2ADC
);
5661 /* Upload IQM Channel Filter settings by
5662 boot loader from ROM table */
5665 status
= BLChainCmd(state
, DRXK_BL_ROM_OFFSET_TAPS_ITU_A
, DRXK_BLCC_NR_ELEMENTS_TAPS
, DRXK_BLC_TIMEOUT
);
5668 status
= BLDirectCmd(state
, IQM_CF_TAP_RE0__A
, DRXK_BL_ROM_OFFSET_TAPS_ITU_C
, DRXK_BLDC_NR_ELEMENTS_TAPS
, DRXK_BLC_TIMEOUT
);
5671 status
= BLDirectCmd(state
, IQM_CF_TAP_IM0__A
, DRXK_BL_ROM_OFFSET_TAPS_ITU_C
, DRXK_BLDC_NR_ELEMENTS_TAPS
, DRXK_BLC_TIMEOUT
);
5679 status
= write16(state
, IQM_CF_OUT_ENA__A
, (1 << IQM_CF_OUT_ENA_QAM__B
));
5682 status
= write16(state
, IQM_CF_SYMMETRIC__A
, 0);
5685 status
= write16(state
, IQM_CF_MIDTAP__A
, ((1 << IQM_CF_MIDTAP_RE__B
) | (1 << IQM_CF_MIDTAP_IM__B
)));
5689 status
= write16(state
, IQM_RC_STRETCH__A
, 21);
5692 status
= write16(state
, IQM_AF_CLP_LEN__A
, 0);
5695 status
= write16(state
, IQM_AF_CLP_TH__A
, 448);
5698 status
= write16(state
, IQM_AF_SNS_LEN__A
, 0);
5701 status
= write16(state
, IQM_CF_POW_MEAS_LEN__A
, 0);
5705 status
= write16(state
, IQM_FS_ADJ_SEL__A
, 1);
5708 status
= write16(state
, IQM_RC_ADJ_SEL__A
, 1);
5711 status
= write16(state
, IQM_CF_ADJ_SEL__A
, 1);
5714 status
= write16(state
, IQM_AF_UPD_SEL__A
, 0);
5718 /* IQM Impulse Noise Processing Unit */
5719 status
= write16(state
, IQM_CF_CLP_VAL__A
, 500);
5722 status
= write16(state
, IQM_CF_DATATH__A
, 1000);
5725 status
= write16(state
, IQM_CF_BYPASSDET__A
, 1);
5728 status
= write16(state
, IQM_CF_DET_LCT__A
, 0);
5731 status
= write16(state
, IQM_CF_WND_LEN__A
, 1);
5734 status
= write16(state
, IQM_CF_PKDTH__A
, 1);
5737 status
= write16(state
, IQM_AF_INC_BYPASS__A
, 1);
5741 /* turn on IQMAF. Must be done before setAgc**() */
5742 status
= SetIqmAf(state
, true);
5745 status
= write16(state
, IQM_AF_START_LOCK__A
, 0x01);
5749 /* IQM will not be reset from here, sync ADC and update/init AGC */
5750 status
= ADCSynchronization(state
);
5754 /* Set the FSM step period */
5755 status
= write16(state
, SCU_RAM_QAM_FSM_STEP_PERIOD__A
, 2000);
5759 /* Halt SCU to enable safe non-atomic accesses */
5760 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_HOLD
);
5764 /* No more resets of the IQM, current standard correctly set =>
5765 now AGCs can be configured. */
5767 status
= InitAGC(state
, true);
5770 status
= SetPreSaw(state
, &(state
->m_qamPreSawCfg
));
5774 /* Configure AGC's */
5775 status
= SetAgcRf(state
, &(state
->m_qamRfAgcCfg
), true);
5778 status
= SetAgcIf(state
, &(state
->m_qamIfAgcCfg
), true);
5782 /* Activate SCU to enable SCU commands */
5783 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_ACTIVE
);
5786 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5790 static int WriteGPIO(struct drxk_state
*state
)
5796 /* stop lock indicator process */
5797 status
= write16(state
, SCU_RAM_GPIO__A
, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE
);
5801 /* Write magic word to enable pdr reg write */
5802 status
= write16(state
, SIO_TOP_COMM_KEY__A
, SIO_TOP_COMM_KEY_KEY
);
5806 if (state
->m_hasSAWSW
) {
5807 if (state
->UIO_mask
& 0x0001) { /* UIO-1 */
5808 /* write to io pad configuration register - output mode */
5809 status
= write16(state
, SIO_PDR_SMA_TX_CFG__A
, state
->m_GPIOCfg
);
5813 /* use corresponding bit in io data output registar */
5814 status
= read16(state
, SIO_PDR_UIO_OUT_LO__A
, &value
);
5817 if ((state
->m_GPIO
& 0x0001) == 0)
5818 value
&= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5820 value
|= 0x8000; /* write one to 15th bit - 1st UIO */
5821 /* write back to io data output register */
5822 status
= write16(state
, SIO_PDR_UIO_OUT_LO__A
, value
);
5826 if (state
->UIO_mask
& 0x0002) { /* UIO-2 */
5827 /* write to io pad configuration register - output mode */
5828 status
= write16(state
, SIO_PDR_SMA_TX_CFG__A
, state
->m_GPIOCfg
);
5832 /* use corresponding bit in io data output registar */
5833 status
= read16(state
, SIO_PDR_UIO_OUT_LO__A
, &value
);
5836 if ((state
->m_GPIO
& 0x0002) == 0)
5837 value
&= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5839 value
|= 0x4000; /* write one to 14th bit - 2st UIO */
5840 /* write back to io data output register */
5841 status
= write16(state
, SIO_PDR_UIO_OUT_LO__A
, value
);
5845 if (state
->UIO_mask
& 0x0004) { /* UIO-3 */
5846 /* write to io pad configuration register - output mode */
5847 status
= write16(state
, SIO_PDR_SMA_TX_CFG__A
, state
->m_GPIOCfg
);
5851 /* use corresponding bit in io data output registar */
5852 status
= read16(state
, SIO_PDR_UIO_OUT_LO__A
, &value
);
5855 if ((state
->m_GPIO
& 0x0004) == 0)
5856 value
&= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5858 value
|= 0x0004; /* write one to 2nd bit - 3rd UIO */
5859 /* write back to io data output register */
5860 status
= write16(state
, SIO_PDR_UIO_OUT_LO__A
, value
);
5865 /* Write magic word to disable pdr reg write */
5866 status
= write16(state
, SIO_TOP_COMM_KEY__A
, 0x0000);
5869 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5873 static int SwitchAntennaToQAM(struct drxk_state
*state
)
5880 if (!state
->antenna_gpio
)
5883 gpio_state
= state
->m_GPIO
& state
->antenna_gpio
;
5885 if (state
->antenna_dvbt
^ gpio_state
) {
5886 /* Antenna is on DVB-T mode. Switch */
5887 if (state
->antenna_dvbt
)
5888 state
->m_GPIO
&= ~state
->antenna_gpio
;
5890 state
->m_GPIO
|= state
->antenna_gpio
;
5891 status
= WriteGPIO(state
);
5894 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5898 static int SwitchAntennaToDVBT(struct drxk_state
*state
)
5905 if (!state
->antenna_gpio
)
5908 gpio_state
= state
->m_GPIO
& state
->antenna_gpio
;
5910 if (!(state
->antenna_dvbt
^ gpio_state
)) {
5911 /* Antenna is on DVB-C mode. Switch */
5912 if (state
->antenna_dvbt
)
5913 state
->m_GPIO
|= state
->antenna_gpio
;
5915 state
->m_GPIO
&= ~state
->antenna_gpio
;
5916 status
= WriteGPIO(state
);
5919 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5924 static int PowerDownDevice(struct drxk_state
*state
)
5926 /* Power down to requested mode */
5927 /* Backup some register settings */
5928 /* Set pins with possible pull-ups connected to them in input mode */
5929 /* Analog power down */
5930 /* ADC power down */
5931 /* Power down device */
5935 if (state
->m_bPDownOpenBridge
) {
5936 /* Open I2C bridge before power down of DRXK */
5937 status
= ConfigureI2CBridge(state
, true);
5942 status
= DVBTEnableOFDMTokenRing(state
, false);
5946 status
= write16(state
, SIO_CC_PWD_MODE__A
, SIO_CC_PWD_MODE_LEVEL_CLOCK
);
5949 status
= write16(state
, SIO_CC_UPDATE__A
, SIO_CC_UPDATE_KEY
);
5952 state
->m_HICfgCtrl
|= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ
;
5953 status
= HI_CfgCommand(state
);
5956 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
5961 static int load_microcode(struct drxk_state
*state
, const char *mc_name
)
5963 const struct firmware
*fw
= NULL
;
5968 err
= request_firmware(&fw
, mc_name
, state
->i2c
->dev
.parent
);
5971 "drxk: Could not load firmware file %s.\n", mc_name
);
5973 "drxk: Copy %s to your hotplug directory!\n", mc_name
);
5976 err
= DownloadMicrocode(state
, fw
->data
, fw
->size
);
5977 release_firmware(fw
);
5981 static int init_drxk(struct drxk_state
*state
)
5984 enum DRXPowerMode powerMode
= DRXK_POWER_DOWN_OFDM
;
5988 if ((state
->m_DrxkState
== DRXK_UNINITIALIZED
)) {
5989 status
= PowerUpDevice(state
);
5992 status
= DRXX_Open(state
);
5995 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5996 status
= write16(state
, SIO_CC_SOFT_RST__A
, SIO_CC_SOFT_RST_OFDM__M
| SIO_CC_SOFT_RST_SYS__M
| SIO_CC_SOFT_RST_OSC__M
);
5999 status
= write16(state
, SIO_CC_UPDATE__A
, SIO_CC_UPDATE_KEY
);
6002 /* TODO is this needed, if yes how much delay in worst case scenario */
6004 state
->m_DRXK_A3_PATCH_CODE
= true;
6005 status
= GetDeviceCapabilities(state
);
6009 /* Bridge delay, uses oscilator clock */
6010 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6011 /* SDA brdige delay */
6012 state
->m_HICfgBridgeDelay
=
6013 (u16
) ((state
->m_oscClockFreq
/ 1000) *
6014 HI_I2C_BRIDGE_DELAY
) / 1000;
6016 if (state
->m_HICfgBridgeDelay
>
6017 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M
) {
6018 state
->m_HICfgBridgeDelay
=
6019 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M
;
6021 /* SCL bridge delay, same as SDA for now */
6022 state
->m_HICfgBridgeDelay
+=
6023 state
->m_HICfgBridgeDelay
<<
6024 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B
;
6026 status
= InitHI(state
);
6029 /* disable various processes */
6031 if (!(state
->m_DRXK_A1_ROM_CODE
)
6032 && !(state
->m_DRXK_A2_ROM_CODE
))
6035 status
= write16(state
, SCU_RAM_GPIO__A
, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE
);
6040 /* disable MPEG port */
6041 status
= MPEGTSDisable(state
);
6045 /* Stop AUD and SCU */
6046 status
= write16(state
, AUD_COMM_EXEC__A
, AUD_COMM_EXEC_STOP
);
6049 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_STOP
);
6053 /* enable token-ring bus through OFDM block for possible ucode upload */
6054 status
= write16(state
, SIO_OFDM_SH_OFDM_RING_ENABLE__A
, SIO_OFDM_SH_OFDM_RING_ENABLE_ON
);
6058 /* include boot loader section */
6059 status
= write16(state
, SIO_BL_COMM_EXEC__A
, SIO_BL_COMM_EXEC_ACTIVE
);
6062 status
= BLChainCmd(state
, 0, 6, 100);
6066 if (!state
->microcode_name
)
6067 load_microcode(state
, "drxk_a3.mc");
6069 load_microcode(state
, state
->microcode_name
);
6071 /* disable token-ring bus through OFDM block for possible ucode upload */
6072 status
= write16(state
, SIO_OFDM_SH_OFDM_RING_ENABLE__A
, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF
);
6076 /* Run SCU for a little while to initialize microcode version numbers */
6077 status
= write16(state
, SCU_COMM_EXEC__A
, SCU_COMM_EXEC_ACTIVE
);
6080 status
= DRXX_Open(state
);
6083 /* added for test */
6086 powerMode
= DRXK_POWER_DOWN_OFDM
;
6087 status
= CtrlPowerMode(state
, &powerMode
);
6091 /* Stamp driver version number in SCU data RAM in BCD code
6092 Done to enable field application engineers to retreive drxdriver version
6093 via I2C from SCU RAM.
6094 Not using SCU command interface for SCU register access since no
6095 microcode may be present.
6098 (((DRXK_VERSION_MAJOR
/ 100) % 10) << 12) +
6099 (((DRXK_VERSION_MAJOR
/ 10) % 10) << 8) +
6100 ((DRXK_VERSION_MAJOR
% 10) << 4) +
6101 (DRXK_VERSION_MINOR
% 10);
6102 status
= write16(state
, SCU_RAM_DRIVER_VER_HI__A
, driverVersion
);
6106 (((DRXK_VERSION_PATCH
/ 1000) % 10) << 12) +
6107 (((DRXK_VERSION_PATCH
/ 100) % 10) << 8) +
6108 (((DRXK_VERSION_PATCH
/ 10) % 10) << 4) +
6109 (DRXK_VERSION_PATCH
% 10);
6110 status
= write16(state
, SCU_RAM_DRIVER_VER_LO__A
, driverVersion
);
6114 printk(KERN_INFO
"DRXK driver version %d.%d.%d\n",
6115 DRXK_VERSION_MAJOR
, DRXK_VERSION_MINOR
,
6116 DRXK_VERSION_PATCH
);
6118 /* Dirty fix of default values for ROM/PATCH microcode
6119 Dirty because this fix makes it impossible to setup suitable values
6120 before calling DRX_Open. This solution requires changes to RF AGC speed
6121 to be done via the CTRL function after calling DRX_Open */
6123 /* m_dvbtRfAgcCfg.speed = 3; */
6125 /* Reset driver debug flags to 0 */
6126 status
= write16(state
, SCU_RAM_DRIVER_DEBUG__A
, 0);
6131 NOTE: No more full FEC resets allowed afterwards!! */
6132 status
= write16(state
, FEC_COMM_EXEC__A
, FEC_COMM_EXEC_STOP
);
6135 /* MPEGTS functions are still the same */
6136 status
= MPEGTSDtoInit(state
);
6139 status
= MPEGTSStop(state
);
6142 status
= MPEGTSConfigurePolarity(state
);
6145 status
= MPEGTSConfigurePins(state
, state
->m_enableMPEGOutput
);
6148 /* added: configure GPIO */
6149 status
= WriteGPIO(state
);
6153 state
->m_DrxkState
= DRXK_STOPPED
;
6155 if (state
->m_bPowerDown
) {
6156 status
= PowerDownDevice(state
);
6159 state
->m_DrxkState
= DRXK_POWERED_DOWN
;
6161 state
->m_DrxkState
= DRXK_STOPPED
;
6165 printk(KERN_ERR
"drxk: Error %d on %s\n", status
, __func__
);
6170 static void drxk_c_release(struct dvb_frontend
*fe
)
6172 struct drxk_state
*state
= fe
->demodulator_priv
;
6178 static int drxk_c_init(struct dvb_frontend
*fe
)
6180 struct drxk_state
*state
= fe
->demodulator_priv
;
6183 if (mutex_trylock(&state
->ctlock
) == 0)
6185 SetOperationMode(state
, OM_QAM_ITU_A
);
6189 static int drxk_c_sleep(struct dvb_frontend
*fe
)
6191 struct drxk_state
*state
= fe
->demodulator_priv
;
6195 mutex_unlock(&state
->ctlock
);
6199 static int drxk_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
6201 struct drxk_state
*state
= fe
->demodulator_priv
;
6203 dprintk(1, "%s\n", enable
? "enable" : "disable");
6204 return ConfigureI2CBridge(state
, enable
? true : false);
6207 static int drxk_set_parameters(struct dvb_frontend
*fe
,
6208 struct dvb_frontend_parameters
*p
)
6210 struct drxk_state
*state
= fe
->demodulator_priv
;
6214 if (fe
->ops
.i2c_gate_ctrl
)
6215 fe
->ops
.i2c_gate_ctrl(fe
, 1);
6216 if (fe
->ops
.tuner_ops
.set_params
)
6217 fe
->ops
.tuner_ops
.set_params(fe
, p
);
6218 if (fe
->ops
.i2c_gate_ctrl
)
6219 fe
->ops
.i2c_gate_ctrl(fe
, 0);
6221 fe
->ops
.tuner_ops
.get_frequency(fe
, &IF
);
6222 Start(state
, 0, IF
);
6224 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6229 static int drxk_c_get_frontend(struct dvb_frontend
*fe
,
6230 struct dvb_frontend_parameters
*p
)
6236 static int drxk_read_status(struct dvb_frontend
*fe
, fe_status_t
*status
)
6238 struct drxk_state
*state
= fe
->demodulator_priv
;
6243 GetLockStatus(state
, &stat
, 0);
6244 if (stat
== MPEG_LOCK
)
6246 if (stat
== FEC_LOCK
)
6248 if (stat
== DEMOD_LOCK
)
6253 static int drxk_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
6261 static int drxk_read_signal_strength(struct dvb_frontend
*fe
,
6264 struct drxk_state
*state
= fe
->demodulator_priv
;
6268 ReadIFAgc(state
, &val
);
6269 *strength
= val
& 0xffff;
6273 static int drxk_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
6275 struct drxk_state
*state
= fe
->demodulator_priv
;
6279 GetSignalToNoise(state
, &snr2
);
6280 *snr
= snr2
& 0xffff;
6284 static int drxk_read_ucblocks(struct dvb_frontend
*fe
, u32
*ucblocks
)
6286 struct drxk_state
*state
= fe
->demodulator_priv
;
6290 DVBTQAMGetAccPktErr(state
, &err
);
6291 *ucblocks
= (u32
) err
;
6295 static int drxk_c_get_tune_settings(struct dvb_frontend
*fe
, struct dvb_frontend_tune_settings
6299 sets
->min_delay_ms
= 3000;
6300 sets
->max_drift
= 0;
6301 sets
->step_size
= 0;
6305 static void drxk_t_release(struct dvb_frontend
*fe
)
6308 * There's nothing to release here, as the state struct
6309 * is already freed by drxk_c_release.
6313 static int drxk_t_init(struct dvb_frontend
*fe
)
6315 struct drxk_state
*state
= fe
->demodulator_priv
;
6318 if (mutex_trylock(&state
->ctlock
) == 0)
6320 SetOperationMode(state
, OM_DVBT
);
6324 static int drxk_t_sleep(struct dvb_frontend
*fe
)
6326 struct drxk_state
*state
= fe
->demodulator_priv
;
6329 mutex_unlock(&state
->ctlock
);
6333 static int drxk_t_get_frontend(struct dvb_frontend
*fe
,
6334 struct dvb_frontend_parameters
*p
)
6341 static struct dvb_frontend_ops drxk_c_ops
= {
6343 .name
= "DRXK DVB-C",
6345 .frequency_stepsize
= 62500,
6346 .frequency_min
= 47000000,
6347 .frequency_max
= 862000000,
6348 .symbol_rate_min
= 870000,
6349 .symbol_rate_max
= 11700000,
6350 .caps
= FE_CAN_QAM_16
| FE_CAN_QAM_32
| FE_CAN_QAM_64
|
6351 FE_CAN_QAM_128
| FE_CAN_QAM_256
| FE_CAN_FEC_AUTO
},
6352 .release
= drxk_c_release
,
6353 .init
= drxk_c_init
,
6354 .sleep
= drxk_c_sleep
,
6355 .i2c_gate_ctrl
= drxk_gate_ctrl
,
6357 .set_frontend
= drxk_set_parameters
,
6358 .get_frontend
= drxk_c_get_frontend
,
6359 .get_tune_settings
= drxk_c_get_tune_settings
,
6361 .read_status
= drxk_read_status
,
6362 .read_ber
= drxk_read_ber
,
6363 .read_signal_strength
= drxk_read_signal_strength
,
6364 .read_snr
= drxk_read_snr
,
6365 .read_ucblocks
= drxk_read_ucblocks
,
6368 static struct dvb_frontend_ops drxk_t_ops
= {
6370 .name
= "DRXK DVB-T",
6372 .frequency_min
= 47125000,
6373 .frequency_max
= 865000000,
6374 .frequency_stepsize
= 166667,
6375 .frequency_tolerance
= 0,
6376 .caps
= FE_CAN_FEC_1_2
| FE_CAN_FEC_2_3
|
6377 FE_CAN_FEC_3_4
| FE_CAN_FEC_5_6
| FE_CAN_FEC_7_8
|
6379 FE_CAN_QAM_16
| FE_CAN_QAM_64
|
6381 FE_CAN_TRANSMISSION_MODE_AUTO
|
6382 FE_CAN_GUARD_INTERVAL_AUTO
|
6383 FE_CAN_HIERARCHY_AUTO
| FE_CAN_RECOVER
| FE_CAN_MUTE_TS
},
6384 .release
= drxk_t_release
,
6385 .init
= drxk_t_init
,
6386 .sleep
= drxk_t_sleep
,
6387 .i2c_gate_ctrl
= drxk_gate_ctrl
,
6389 .set_frontend
= drxk_set_parameters
,
6390 .get_frontend
= drxk_t_get_frontend
,
6392 .read_status
= drxk_read_status
,
6393 .read_ber
= drxk_read_ber
,
6394 .read_signal_strength
= drxk_read_signal_strength
,
6395 .read_snr
= drxk_read_snr
,
6396 .read_ucblocks
= drxk_read_ucblocks
,
6399 struct dvb_frontend
*drxk_attach(const struct drxk_config
*config
,
6400 struct i2c_adapter
*i2c
,
6401 struct dvb_frontend
**fe_t
)
6403 struct drxk_state
*state
= NULL
;
6404 u8 adr
= config
->adr
;
6407 state
= kzalloc(sizeof(struct drxk_state
), GFP_KERNEL
);
6412 state
->demod_address
= adr
;
6413 state
->single_master
= config
->single_master
;
6414 state
->microcode_name
= config
->microcode_name
;
6415 state
->no_i2c_bridge
= config
->no_i2c_bridge
;
6416 state
->antenna_gpio
= config
->antenna_gpio
;
6417 state
->antenna_dvbt
= config
->antenna_dvbt
;
6419 /* NOTE: as more UIO bits will be used, add them to the mask */
6420 state
->UIO_mask
= config
->antenna_gpio
;
6422 /* Default gpio to DVB-C */
6423 if (!state
->antenna_dvbt
&& state
->antenna_gpio
)
6424 state
->m_GPIO
|= state
->antenna_gpio
;
6426 state
->m_GPIO
&= ~state
->antenna_gpio
;
6428 mutex_init(&state
->mutex
);
6429 mutex_init(&state
->ctlock
);
6431 memcpy(&state
->c_frontend
.ops
, &drxk_c_ops
,
6432 sizeof(struct dvb_frontend_ops
));
6433 memcpy(&state
->t_frontend
.ops
, &drxk_t_ops
,
6434 sizeof(struct dvb_frontend_ops
));
6435 state
->c_frontend
.demodulator_priv
= state
;
6436 state
->t_frontend
.demodulator_priv
= state
;
6439 if (init_drxk(state
) < 0)
6441 *fe_t
= &state
->t_frontend
;
6443 return &state
->c_frontend
;
6446 printk(KERN_ERR
"drxk: not found\n");
6450 EXPORT_SYMBOL(drxk_attach
);
6452 MODULE_DESCRIPTION("DRX-K driver");
6453 MODULE_AUTHOR("Ralph Metzler");
6454 MODULE_LICENSE("GPL");