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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_link.c
blob818723c9e6783aa97b6e2340cd84c7ab44578cfa
1 /* Copyright 2008-2011 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
26
27 #include "bnx2x.h"
28 #include "bnx2x_cmn.h"
29
30
31 /********************************************************/
32 #define ETH_HLEN 14
33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
34 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
35 #define ETH_MIN_PACKET_SIZE 60
36 #define ETH_MAX_PACKET_SIZE 1500
37 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
38 #define MDIO_ACCESS_TIMEOUT 1000
39 #define BMAC_CONTROL_RX_ENABLE 2
40 #define WC_LANE_MAX 4
41 #define I2C_SWITCH_WIDTH 2
42 #define I2C_BSC0 0
43 #define I2C_BSC1 1
44 #define I2C_WA_RETRY_CNT 3
45 #define MCPR_IMC_COMMAND_READ_OP 1
46 #define MCPR_IMC_COMMAND_WRITE_OP 2
47
48 /***********************************************************/
49 /* Shortcut definitions */
50 /***********************************************************/
51
52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
53
54 #define NIG_STATUS_EMAC0_MI_INT \
55 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
56 #define NIG_STATUS_XGXS0_LINK10G \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
58 #define NIG_STATUS_XGXS0_LINK_STATUS \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
62 #define NIG_STATUS_SERDES0_LINK_STATUS \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
64 #define NIG_MASK_MI_INT \
65 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
66 #define NIG_MASK_XGXS0_LINK10G \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
68 #define NIG_MASK_XGXS0_LINK_STATUS \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
70 #define NIG_MASK_SERDES0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
72
73 #define MDIO_AN_CL73_OR_37_COMPLETE \
74 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
75 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
76
77 #define XGXS_RESET_BITS \
78 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
80 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
83
84 #define SERDES_RESET_BITS \
85 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
86 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
89
90 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
91 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
92 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
93 #define AUTONEG_PARALLEL \
94 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
95 #define AUTONEG_SGMII_FIBER_AUTODET \
96 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
97 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
98
99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
103 #define GP_STATUS_SPEED_MASK \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
105 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
106 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
107 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
108 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
109 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
110 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
111 #define GP_STATUS_10G_HIG \
112 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
113 #define GP_STATUS_10G_CX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
116 #define GP_STATUS_10G_KX4 \
117 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
119 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
121 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
122 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
123 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
124 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
125 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
126 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
127 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
128 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
129 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
130 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
131 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
132 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
133 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
134 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
135 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
136 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
137
138
139
140 /* */
141 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
142 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
143 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
144
145
146 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
147 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
148 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
149 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
150
151 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
152 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
154
155 #define SFP_EEPROM_OPTIONS_ADDR 0x40
156 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
157 #define SFP_EEPROM_OPTIONS_SIZE 2
158
159 #define EDC_MODE_LINEAR 0x0022
160 #define EDC_MODE_LIMITING 0x0044
161 #define EDC_MODE_PASSIVE_DAC 0x0055
162
163
164 /* BRB thresholds for E2*/
165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
167
168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
170
171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
173
174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
176
177 /* BRB thresholds for E3A0 */
178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
180
181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
183
184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
186
187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
189
190
191 /* BRB thresholds for E3B0 2 port mode*/
192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
194
195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
197
198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
200
201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
203
204 /* only for E3B0*/
205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
207
208 /* Lossy +Lossless GUARANTIED == GUART */
209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
210 /* Lossless +Lossless*/
211 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
212 /* Lossy +Lossy*/
213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
214
215 /* Lossy +Lossless*/
216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
217 /* Lossless +Lossless*/
218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
219 /* Lossy +Lossy*/
220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
222
223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
225
226 /* BRB thresholds for E3B0 4 port mode */
227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
229
230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
232
233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
235
236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
238
239
240 /* only for E3B0*/
241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
243 #define PFC_E3B0_4P_LB_GUART 120
244
245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
247
248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
250
251 #define DCBX_INVALID_COS (0xFF)
252
253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
254 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
257 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
258
259 #define MAX_PACKET_SIZE (9700)
260 #define WC_UC_TIMEOUT 100
261
262 /**********************************************************/
263 /* INTERFACE */
264 /**********************************************************/
265
266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
267 bnx2x_cl45_write(_bp, _phy, \
268 (_phy)->def_md_devad, \
269 (_bank + (_addr & 0xf)), \
270 _val)
271
272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
273 bnx2x_cl45_read(_bp, _phy, \
274 (_phy)->def_md_devad, \
275 (_bank + (_addr & 0xf)), \
276 _val)
277
278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
279 {
280 u32 val = REG_RD(bp, reg);
281
282 val |= bits;
283 REG_WR(bp, reg, val);
284 return val;
285 }
286
287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
288 {
289 u32 val = REG_RD(bp, reg);
290
291 val &= ~bits;
292 REG_WR(bp, reg, val);
293 return val;
294 }
295
296 /******************************************************************/
297 /* EPIO/GPIO section */
298 /******************************************************************/
299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
300 {
301 u32 epio_mask, gp_oenable;
302 *en = 0;
303 /* Sanity check */
304 if (epio_pin > 31) {
305 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
306 return;
307 }
308
309 epio_mask = 1 << epio_pin;
310 /* Set this EPIO to output */
311 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
312 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
313
314 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
315 }
316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
317 {
318 u32 epio_mask, gp_output, gp_oenable;
319
320 /* Sanity check */
321 if (epio_pin > 31) {
322 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
323 return;
324 }
325 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
326 epio_mask = 1 << epio_pin;
327 /* Set this EPIO to output */
328 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
329 if (en)
330 gp_output |= epio_mask;
331 else
332 gp_output &= ~epio_mask;
333
334 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
335
336 /* Set the value for this EPIO */
337 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
338 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
339 }
340
341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
342 {
343 if (pin_cfg == PIN_CFG_NA)
344 return;
345 if (pin_cfg >= PIN_CFG_EPIO0) {
346 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
347 } else {
348 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
349 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
350 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
351 }
352 }
353
354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
355 {
356 if (pin_cfg == PIN_CFG_NA)
357 return -EINVAL;
358 if (pin_cfg >= PIN_CFG_EPIO0) {
359 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
360 } else {
361 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
362 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
363 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
364 }
365 return 0;
366
367 }
368 /******************************************************************/
369 /* ETS section */
370 /******************************************************************/
371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
372 {
373 /* ETS disabled configuration*/
374 struct bnx2x *bp = params->bp;
375
376 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
377
378 /*
379 * mapping between entry priority to client number (0,1,2 -debug and
380 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
381 * 3bits client num.
382 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
383 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
384 */
385
386 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
387 /*
388 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
389 * as strict. Bits 0,1,2 - debug and management entries, 3 -
390 * COS0 entry, 4 - COS1 entry.
391 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
392 * bit4 bit3 bit2 bit1 bit0
393 * MCP and debug are strict
394 */
395
396 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
397 /* defines which entries (clients) are subjected to WFQ arbitration */
398 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
399 /*
400 * For strict priority entries defines the number of consecutive
401 * slots for the highest priority.
402 */
403 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
404 /*
405 * mapping between the CREDIT_WEIGHT registers and actual client
406 * numbers
407 */
408 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
409 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
410 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
411
412 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
413 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
414 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
415 /* ETS mode disable */
416 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
417 /*
418 * If ETS mode is enabled (there is no strict priority) defines a WFQ
419 * weight for COS0/COS1.
420 */
421 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
422 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
423 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
424 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
425 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
426 /* Defines the number of consecutive slots for the strict priority */
427 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
428 }
429 /******************************************************************************
430 * Description:
431 * Getting min_w_val will be set according to line speed .
432 *.
433 ******************************************************************************/
434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
435 {
436 u32 min_w_val = 0;
437 /* Calculate min_w_val.*/
438 if (vars->link_up) {
439 if (SPEED_20000 == vars->line_speed)
440 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
441 else
442 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
443 } else
444 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
445 /**
446 * If the link isn't up (static configuration for example ) The
447 * link will be according to 20GBPS.
448 */
449 return min_w_val;
450 }
451 /******************************************************************************
452 * Description:
453 * Getting credit upper bound form min_w_val.
454 *.
455 ******************************************************************************/
456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
457 {
458 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
459 MAX_PACKET_SIZE);
460 return credit_upper_bound;
461 }
462 /******************************************************************************
463 * Description:
464 * Set credit upper bound for NIG.
465 *.
466 ******************************************************************************/
467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
468 const struct link_params *params,
469 const u32 min_w_val)
470 {
471 struct bnx2x *bp = params->bp;
472 const u8 port = params->port;
473 const u32 credit_upper_bound =
474 bnx2x_ets_get_credit_upper_bound(min_w_val);
475
476 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
477 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
478 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
479 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
480 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
481 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
482 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
483 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
484 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
485 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
486 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
487 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
488
489 if (0 == port) {
490 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
491 credit_upper_bound);
492 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
493 credit_upper_bound);
494 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
495 credit_upper_bound);
496 }
497 }
498 /******************************************************************************
499 * Description:
500 * Will return the NIG ETS registers to init values.Except
501 * credit_upper_bound.
502 * That isn't used in this configuration (No WFQ is enabled) and will be
503 * configured acording to spec
504 *.
505 ******************************************************************************/
506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
507 const struct link_vars *vars)
508 {
509 struct bnx2x *bp = params->bp;
510 const u8 port = params->port;
511 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
512 /**
513 * mapping between entry priority to client number (0,1,2 -debug and
514 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
515 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
516 * reset value or init tool
517 */
518 if (port) {
519 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
520 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
521 } else {
522 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
523 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
524 }
525 /**
526 * For strict priority entries defines the number of consecutive
527 * slots for the highest priority.
528 */
529 /* TODO_ETS - Should be done by reset value or init tool */
530 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
531 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
532 /**
533 * mapping between the CREDIT_WEIGHT registers and actual client
534 * numbers
535 */
536 /* TODO_ETS - Should be done by reset value or init tool */
537 if (port) {
538 /*Port 1 has 6 COS*/
539 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
540 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
541 } else {
542 /*Port 0 has 9 COS*/
543 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
544 0x43210876);
545 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
546 }
547
548 /**
549 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
550 * as strict. Bits 0,1,2 - debug and management entries, 3 -
551 * COS0 entry, 4 - COS1 entry.
552 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
553 * bit4 bit3 bit2 bit1 bit0
554 * MCP and debug are strict
555 */
556 if (port)
557 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
558 else
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
560 /* defines which entries (clients) are subjected to WFQ arbitration */
561 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
562 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
563
564 /**
565 * Please notice the register address are note continuous and a
566 * for here is note appropriate.In 2 port mode port0 only COS0-5
567 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
568 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
569 * are never used for WFQ
570 */
571 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
572 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
573 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
574 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
575 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
576 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
578 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
579 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
580 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
581 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
582 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
583 if (0 == port) {
584 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
585 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
586 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
587 }
588
589 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
590 }
591 /******************************************************************************
592 * Description:
593 * Set credit upper bound for PBF.
594 *.
595 ******************************************************************************/
596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
597 const struct link_params *params,
598 const u32 min_w_val)
599 {
600 struct bnx2x *bp = params->bp;
601 const u32 credit_upper_bound =
602 bnx2x_ets_get_credit_upper_bound(min_w_val);
603 const u8 port = params->port;
604 u32 base_upper_bound = 0;
605 u8 max_cos = 0;
606 u8 i = 0;
607 /**
608 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
609 * port mode port1 has COS0-2 that can be used for WFQ.
610 */
611 if (0 == port) {
612 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
613 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
614 } else {
615 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
616 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
617 }
618
619 for (i = 0; i < max_cos; i++)
620 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
621 }
622
623 /******************************************************************************
624 * Description:
625 * Will return the PBF ETS registers to init values.Except
626 * credit_upper_bound.
627 * That isn't used in this configuration (No WFQ is enabled) and will be
628 * configured acording to spec
629 *.
630 ******************************************************************************/
631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
632 {
633 struct bnx2x *bp = params->bp;
634 const u8 port = params->port;
635 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
636 u8 i = 0;
637 u32 base_weight = 0;
638 u8 max_cos = 0;
639
640 /**
641 * mapping between entry priority to client number 0 - COS0
642 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
643 * TODO_ETS - Should be done by reset value or init tool
644 */
645 if (port)
646 /* 0x688 (|011|0 10|00 1|000) */
647 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
648 else
649 /* (10 1|100 |011|0 10|00 1|000) */
650 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
651
652 /* TODO_ETS - Should be done by reset value or init tool */
653 if (port)
654 /* 0x688 (|011|0 10|00 1|000)*/
655 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
656 else
657 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
658 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
659
660 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
661 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
662
663
664 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
665 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
666
667 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
668 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
669 /**
670 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
671 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
672 */
673 if (0 == port) {
674 base_weight = PBF_REG_COS0_WEIGHT_P0;
675 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
676 } else {
677 base_weight = PBF_REG_COS0_WEIGHT_P1;
678 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
679 }
680
681 for (i = 0; i < max_cos; i++)
682 REG_WR(bp, base_weight + (0x4 * i), 0);
683
684 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
685 }
686 /******************************************************************************
687 * Description:
688 * E3B0 disable will return basicly the values to init values.
689 *.
690 ******************************************************************************/
691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
692 const struct link_vars *vars)
693 {
694 struct bnx2x *bp = params->bp;
695
696 if (!CHIP_IS_E3B0(bp)) {
697 DP(NETIF_MSG_LINK,
698 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
699 return -EINVAL;
700 }
701
702 bnx2x_ets_e3b0_nig_disabled(params, vars);
703
704 bnx2x_ets_e3b0_pbf_disabled(params);
705
706 return 0;
707 }
708
709 /******************************************************************************
710 * Description:
711 * Disable will return basicly the values to init values.
712 *.
713 ******************************************************************************/
714 int bnx2x_ets_disabled(struct link_params *params,
715 struct link_vars *vars)
716 {
717 struct bnx2x *bp = params->bp;
718 int bnx2x_status = 0;
719
720 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
721 bnx2x_ets_e2e3a0_disabled(params);
722 else if (CHIP_IS_E3B0(bp))
723 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
724 else {
725 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
726 return -EINVAL;
727 }
728
729 return bnx2x_status;
730 }
731
732 /******************************************************************************
733 * Description
734 * Set the COS mappimg to SP and BW until this point all the COS are not
735 * set as SP or BW.
736 ******************************************************************************/
737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
738 const struct bnx2x_ets_params *ets_params,
739 const u8 cos_sp_bitmap,
740 const u8 cos_bw_bitmap)
741 {
742 struct bnx2x *bp = params->bp;
743 const u8 port = params->port;
744 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
745 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
746 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
747 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
748
749 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
750 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
751
752 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
753 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
754
755 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
756 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
757 nig_cli_subject2wfq_bitmap);
758
759 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
760 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
761 pbf_cli_subject2wfq_bitmap);
762
763 return 0;
764 }
765
766 /******************************************************************************
767 * Description:
768 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
769 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
770 ******************************************************************************/
771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
772 const u8 cos_entry,
773 const u32 min_w_val_nig,
774 const u32 min_w_val_pbf,
775 const u16 total_bw,
776 const u8 bw,
777 const u8 port)
778 {
779 u32 nig_reg_adress_crd_weight = 0;
780 u32 pbf_reg_adress_crd_weight = 0;
781 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
782 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
783 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
784
785 switch (cos_entry) {
786 case 0:
787 nig_reg_adress_crd_weight =
788 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
789 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
790 pbf_reg_adress_crd_weight = (port) ?
791 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
792 break;
793 case 1:
794 nig_reg_adress_crd_weight = (port) ?
795 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
796 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
797 pbf_reg_adress_crd_weight = (port) ?
798 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
799 break;
800 case 2:
801 nig_reg_adress_crd_weight = (port) ?
802 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
803 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
804
805 pbf_reg_adress_crd_weight = (port) ?
806 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
807 break;
808 case 3:
809 if (port)
810 return -EINVAL;
811 nig_reg_adress_crd_weight =
812 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
813 pbf_reg_adress_crd_weight =
814 PBF_REG_COS3_WEIGHT_P0;
815 break;
816 case 4:
817 if (port)
818 return -EINVAL;
819 nig_reg_adress_crd_weight =
820 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
821 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
822 break;
823 case 5:
824 if (port)
825 return -EINVAL;
826 nig_reg_adress_crd_weight =
827 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
828 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
829 break;
830 }
831
832 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
833
834 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
835
836 return 0;
837 }
838 /******************************************************************************
839 * Description:
840 * Calculate the total BW.A value of 0 isn't legal.
841 *.
842 ******************************************************************************/
843 static int bnx2x_ets_e3b0_get_total_bw(
844 const struct link_params *params,
845 const struct bnx2x_ets_params *ets_params,
846 u16 *total_bw)
847 {
848 struct bnx2x *bp = params->bp;
849 u8 cos_idx = 0;
850
851 *total_bw = 0 ;
852 /* Calculate total BW requested */
853 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
854 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
855 *total_bw +=
856 ets_params->cos[cos_idx].params.bw_params.bw;
857 }
858 }
859
860 /* Check total BW is valid */
861 if ((100 != *total_bw) || (0 == *total_bw)) {
862 if (0 == *total_bw) {
863 DP(NETIF_MSG_LINK,
864 "bnx2x_ets_E3B0_config toatl BW shouldn't be 0\n");
865 return -EINVAL;
866 }
867 DP(NETIF_MSG_LINK,
868 "bnx2x_ets_E3B0_config toatl BW should be 100\n");
869 /**
870 * We can handle a case whre the BW isn't 100 this can happen
871 * if the TC are joined.
872 */
873 }
874 return 0;
875 }
876
877 /******************************************************************************
878 * Description:
879 * Invalidate all the sp_pri_to_cos.
880 *.
881 ******************************************************************************/
882 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
883 {
884 u8 pri = 0;
885 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
886 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
887 }
888 /******************************************************************************
889 * Description:
890 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
891 * according to sp_pri_to_cos.
892 *.
893 ******************************************************************************/
894 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
895 u8 *sp_pri_to_cos, const u8 pri,
896 const u8 cos_entry)
897 {
898 struct bnx2x *bp = params->bp;
899 const u8 port = params->port;
900 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
901 DCBX_E3B0_MAX_NUM_COS_PORT0;
902
903 if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
904 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
905 "parameter There can't be two COS's with "
906 "the same strict pri\n");
907 return -EINVAL;
908 }
909
910 if (pri > max_num_of_cos) {
911 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
912 "parameter Illegal strict priority\n");
913 return -EINVAL;
914 }
915
916 sp_pri_to_cos[pri] = cos_entry;
917 return 0;
918
919 }
920
921 /******************************************************************************
922 * Description:
923 * Returns the correct value according to COS and priority in
924 * the sp_pri_cli register.
925 *.
926 ******************************************************************************/
927 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
928 const u8 pri_set,
929 const u8 pri_offset,
930 const u8 entry_size)
931 {
932 u64 pri_cli_nig = 0;
933 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
934 (pri_set + pri_offset));
935
936 return pri_cli_nig;
937 }
938 /******************************************************************************
939 * Description:
940 * Returns the correct value according to COS and priority in the
941 * sp_pri_cli register for NIG.
942 *.
943 ******************************************************************************/
944 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
945 {
946 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
947 const u8 nig_cos_offset = 3;
948 const u8 nig_pri_offset = 3;
949
950 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
951 nig_pri_offset, 4);
952
953 }
954 /******************************************************************************
955 * Description:
956 * Returns the correct value according to COS and priority in the
957 * sp_pri_cli register for PBF.
958 *.
959 ******************************************************************************/
960 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
961 {
962 const u8 pbf_cos_offset = 0;
963 const u8 pbf_pri_offset = 0;
964
965 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
966 pbf_pri_offset, 3);
967
968 }
969
970 /******************************************************************************
971 * Description:
972 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
973 * according to sp_pri_to_cos.(which COS has higher priority)
974 *.
975 ******************************************************************************/
976 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
977 u8 *sp_pri_to_cos)
978 {
979 struct bnx2x *bp = params->bp;
980 u8 i = 0;
981 const u8 port = params->port;
982 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
983 u64 pri_cli_nig = 0x210;
984 u32 pri_cli_pbf = 0x0;
985 u8 pri_set = 0;
986 u8 pri_bitmask = 0;
987 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
988 DCBX_E3B0_MAX_NUM_COS_PORT0;
989
990 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
991
992 /* Set all the strict priority first */
993 for (i = 0; i < max_num_of_cos; i++) {
994 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
995 if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
996 DP(NETIF_MSG_LINK,
997 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
998 "invalid cos entry\n");
999 return -EINVAL;
1000 }
1001
1002 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1003 sp_pri_to_cos[i], pri_set);
1004
1005 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1006 sp_pri_to_cos[i], pri_set);
1007 pri_bitmask = 1 << sp_pri_to_cos[i];
1008 /* COS is used remove it from bitmap.*/
1009 if (0 == (pri_bitmask & cos_bit_to_set)) {
1010 DP(NETIF_MSG_LINK,
1011 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1012 "invalid There can't be two COS's with"
1013 " the same strict pri\n");
1014 return -EINVAL;
1015 }
1016 cos_bit_to_set &= ~pri_bitmask;
1017 pri_set++;
1018 }
1019 }
1020
1021 /* Set all the Non strict priority i= COS*/
1022 for (i = 0; i < max_num_of_cos; i++) {
1023 pri_bitmask = 1 << i;
1024 /* Check if COS was already used for SP */
1025 if (pri_bitmask & cos_bit_to_set) {
1026 /* COS wasn't used for SP */
1027 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1028 i, pri_set);
1029
1030 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1031 i, pri_set);
1032 /* COS is used remove it from bitmap.*/
1033 cos_bit_to_set &= ~pri_bitmask;
1034 pri_set++;
1035 }
1036 }
1037
1038 if (pri_set != max_num_of_cos) {
1039 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1040 "entries were set\n");
1041 return -EINVAL;
1042 }
1043
1044 if (port) {
1045 /* Only 6 usable clients*/
1046 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1047 (u32)pri_cli_nig);
1048
1049 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1050 } else {
1051 /* Only 9 usable clients*/
1052 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1053 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1054
1055 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1056 pri_cli_nig_lsb);
1057 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1058 pri_cli_nig_msb);
1059
1060 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1061 }
1062 return 0;
1063 }
1064
1065 /******************************************************************************
1066 * Description:
1067 * Configure the COS to ETS according to BW and SP settings.
1068 ******************************************************************************/
1069 int bnx2x_ets_e3b0_config(const struct link_params *params,
1070 const struct link_vars *vars,
1071 const struct bnx2x_ets_params *ets_params)
1072 {
1073 struct bnx2x *bp = params->bp;
1074 int bnx2x_status = 0;
1075 const u8 port = params->port;
1076 u16 total_bw = 0;
1077 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1078 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1079 u8 cos_bw_bitmap = 0;
1080 u8 cos_sp_bitmap = 0;
1081 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1082 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1083 DCBX_E3B0_MAX_NUM_COS_PORT0;
1084 u8 cos_entry = 0;
1085
1086 if (!CHIP_IS_E3B0(bp)) {
1087 DP(NETIF_MSG_LINK,
1088 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1089 return -EINVAL;
1090 }
1091
1092 if ((ets_params->num_of_cos > max_num_of_cos)) {
1093 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1094 "isn't supported\n");
1095 return -EINVAL;
1096 }
1097
1098 /* Prepare sp strict priority parameters*/
1099 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1100
1101 /* Prepare BW parameters*/
1102 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1103 &total_bw);
1104 if (0 != bnx2x_status) {
1105 DP(NETIF_MSG_LINK,
1106 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1107 return -EINVAL;
1108 }
1109
1110 /**
1111 * Upper bound is set according to current link speed (min_w_val
1112 * should be the same for upper bound and COS credit val).
1113 */
1114 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1115 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1116
1117
1118 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1119 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1120 cos_bw_bitmap |= (1 << cos_entry);
1121 /**
1122 * The function also sets the BW in HW(not the mappin
1123 * yet)
1124 */
1125 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1126 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1127 total_bw,
1128 ets_params->cos[cos_entry].params.bw_params.bw,
1129 port);
1130 } else if (bnx2x_cos_state_strict ==
1131 ets_params->cos[cos_entry].state){
1132 cos_sp_bitmap |= (1 << cos_entry);
1133
1134 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1135 params,
1136 sp_pri_to_cos,
1137 ets_params->cos[cos_entry].params.sp_params.pri,
1138 cos_entry);
1139
1140 } else {
1141 DP(NETIF_MSG_LINK,
1142 "bnx2x_ets_e3b0_config cos state not valid\n");
1143 return -EINVAL;
1144 }
1145 if (0 != bnx2x_status) {
1146 DP(NETIF_MSG_LINK,
1147 "bnx2x_ets_e3b0_config set cos bw failed\n");
1148 return bnx2x_status;
1149 }
1150 }
1151
1152 /* Set SP register (which COS has higher priority) */
1153 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1154 sp_pri_to_cos);
1155
1156 if (0 != bnx2x_status) {
1157 DP(NETIF_MSG_LINK,
1158 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1159 return bnx2x_status;
1160 }
1161
1162 /* Set client mapping of BW and strict */
1163 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1164 cos_sp_bitmap,
1165 cos_bw_bitmap);
1166
1167 if (0 != bnx2x_status) {
1168 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1169 return bnx2x_status;
1170 }
1171 return 0;
1172 }
1173 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1174 {
1175 /* ETS disabled configuration */
1176 struct bnx2x *bp = params->bp;
1177 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1178 /*
1179 * defines which entries (clients) are subjected to WFQ arbitration
1180 * COS0 0x8
1181 * COS1 0x10
1182 */
1183 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1184 /*
1185 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1186 * client numbers (WEIGHT_0 does not actually have to represent
1187 * client 0)
1188 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1189 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1190 */
1191 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1192
1193 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1194 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1195 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1196 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1197
1198 /* ETS mode enabled*/
1199 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1200
1201 /* Defines the number of consecutive slots for the strict priority */
1202 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1203 /*
1204 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1205 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1206 * entry, 4 - COS1 entry.
1207 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1208 * bit4 bit3 bit2 bit1 bit0
1209 * MCP and debug are strict
1210 */
1211 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1212
1213 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1214 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1215 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1216 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1217 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1218 }
1219
1220 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1221 const u32 cos1_bw)
1222 {
1223 /* ETS disabled configuration*/
1224 struct bnx2x *bp = params->bp;
1225 const u32 total_bw = cos0_bw + cos1_bw;
1226 u32 cos0_credit_weight = 0;
1227 u32 cos1_credit_weight = 0;
1228
1229 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1230
1231 if ((0 == total_bw) ||
1232 (0 == cos0_bw) ||
1233 (0 == cos1_bw)) {
1234 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1235 return;
1236 }
1237
1238 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1239 total_bw;
1240 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1241 total_bw;
1242
1243 bnx2x_ets_bw_limit_common(params);
1244
1245 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1246 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1247
1248 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1249 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1250 }
1251
1252 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1253 {
1254 /* ETS disabled configuration*/
1255 struct bnx2x *bp = params->bp;
1256 u32 val = 0;
1257
1258 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1259 /*
1260 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1261 * as strict. Bits 0,1,2 - debug and management entries,
1262 * 3 - COS0 entry, 4 - COS1 entry.
1263 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1264 * bit4 bit3 bit2 bit1 bit0
1265 * MCP and debug are strict
1266 */
1267 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1268 /*
1269 * For strict priority entries defines the number of consecutive slots
1270 * for the highest priority.
1271 */
1272 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1273 /* ETS mode disable */
1274 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1275 /* Defines the number of consecutive slots for the strict priority */
1276 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1277
1278 /* Defines the number of consecutive slots for the strict priority */
1279 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1280
1281 /*
1282 * mapping between entry priority to client number (0,1,2 -debug and
1283 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1284 * 3bits client num.
1285 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1286 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1287 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1288 */
1289 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1290 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1291
1292 return 0;
1293 }
1294 /******************************************************************/
1295 /* PFC section */
1296 /******************************************************************/
1297
1298 static void bnx2x_update_pfc_xmac(struct link_params *params,
1299 struct link_vars *vars,
1300 u8 is_lb)
1301 {
1302 struct bnx2x *bp = params->bp;
1303 u32 xmac_base;
1304 u32 pause_val, pfc0_val, pfc1_val;
1305
1306 /* XMAC base adrr */
1307 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1308
1309 /* Initialize pause and pfc registers */
1310 pause_val = 0x18000;
1311 pfc0_val = 0xFFFF8000;
1312 pfc1_val = 0x2;
1313
1314 /* No PFC support */
1315 if (!(params->feature_config_flags &
1316 FEATURE_CONFIG_PFC_ENABLED)) {
1317
1318 /*
1319 * RX flow control - Process pause frame in receive direction
1320 */
1321 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1322 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1323
1324 /*
1325 * TX flow control - Send pause packet when buffer is full
1326 */
1327 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1328 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1329 } else {/* PFC support */
1330 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1331 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1332 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1333 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1334 }
1335
1336 /* Write pause and PFC registers */
1337 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1338 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1339 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1340
1341
1342 /* Set MAC address for source TX Pause/PFC frames */
1343 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1344 ((params->mac_addr[2] << 24) |
1345 (params->mac_addr[3] << 16) |
1346 (params->mac_addr[4] << 8) |
1347 (params->mac_addr[5])));
1348 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1349 ((params->mac_addr[0] << 8) |
1350 (params->mac_addr[1])));
1351
1352 udelay(30);
1353 }
1354
1355
1356 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1357 u32 pfc_frames_sent[2],
1358 u32 pfc_frames_received[2])
1359 {
1360 /* Read pfc statistic */
1361 struct bnx2x *bp = params->bp;
1362 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1363 u32 val_xon = 0;
1364 u32 val_xoff = 0;
1365
1366 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1367
1368 /* PFC received frames */
1369 val_xoff = REG_RD(bp, emac_base +
1370 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1371 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1372 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1373 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1374
1375 pfc_frames_received[0] = val_xon + val_xoff;
1376
1377 /* PFC received sent */
1378 val_xoff = REG_RD(bp, emac_base +
1379 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1380 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1381 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1382 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1383
1384 pfc_frames_sent[0] = val_xon + val_xoff;
1385 }
1386
1387 /* Read pfc statistic*/
1388 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1389 u32 pfc_frames_sent[2],
1390 u32 pfc_frames_received[2])
1391 {
1392 /* Read pfc statistic */
1393 struct bnx2x *bp = params->bp;
1394
1395 DP(NETIF_MSG_LINK, "pfc statistic\n");
1396
1397 if (!vars->link_up)
1398 return;
1399
1400 if (MAC_TYPE_EMAC == vars->mac_type) {
1401 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1402 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1403 pfc_frames_received);
1404 }
1405 }
1406 /******************************************************************/
1407 /* MAC/PBF section */
1408 /******************************************************************/
1409 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1410 {
1411 u32 mode, emac_base;
1412 /**
1413 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1414 * (a value of 49==0x31) and make sure that the AUTO poll is off
1415 */
1416
1417 if (CHIP_IS_E2(bp))
1418 emac_base = GRCBASE_EMAC0;
1419 else
1420 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1421 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1422 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1423 EMAC_MDIO_MODE_CLOCK_CNT);
1424 if (USES_WARPCORE(bp))
1425 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1426 else
1427 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1428
1429 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1430 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1431
1432 udelay(40);
1433 }
1434
1435 static void bnx2x_emac_init(struct link_params *params,
1436 struct link_vars *vars)
1437 {
1438 /* reset and unreset the emac core */
1439 struct bnx2x *bp = params->bp;
1440 u8 port = params->port;
1441 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1442 u32 val;
1443 u16 timeout;
1444
1445 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1446 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1447 udelay(5);
1448 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1449 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1450
1451 /* init emac - use read-modify-write */
1452 /* self clear reset */
1453 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1454 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1455
1456 timeout = 200;
1457 do {
1458 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1459 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1460 if (!timeout) {
1461 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1462 return;
1463 }
1464 timeout--;
1465 } while (val & EMAC_MODE_RESET);
1466 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1467 /* Set mac address */
1468 val = ((params->mac_addr[0] << 8) |
1469 params->mac_addr[1]);
1470 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1471
1472 val = ((params->mac_addr[2] << 24) |
1473 (params->mac_addr[3] << 16) |
1474 (params->mac_addr[4] << 8) |
1475 params->mac_addr[5]);
1476 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1477 }
1478
1479 static void bnx2x_set_xumac_nig(struct link_params *params,
1480 u16 tx_pause_en,
1481 u8 enable)
1482 {
1483 struct bnx2x *bp = params->bp;
1484
1485 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1486 enable);
1487 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1488 enable);
1489 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1490 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1491 }
1492
1493 static void bnx2x_umac_enable(struct link_params *params,
1494 struct link_vars *vars, u8 lb)
1495 {
1496 u32 val;
1497 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1498 struct bnx2x *bp = params->bp;
1499 /* Reset UMAC */
1500 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1501 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1502 usleep_range(1000, 1000);
1503
1504 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1505 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1506
1507 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1508
1509 /**
1510 * This register determines on which events the MAC will assert
1511 * error on the i/f to the NIG along w/ EOP.
1512 */
1513
1514 /**
1515 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1516 * params->port*0x14, 0xfffff.
1517 */
1518 /* This register opens the gate for the UMAC despite its name */
1519 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1520
1521 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1522 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1523 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1524 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1525 switch (vars->line_speed) {
1526 case SPEED_10:
1527 val |= (0<<2);
1528 break;
1529 case SPEED_100:
1530 val |= (1<<2);
1531 break;
1532 case SPEED_1000:
1533 val |= (2<<2);
1534 break;
1535 case SPEED_2500:
1536 val |= (3<<2);
1537 break;
1538 default:
1539 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1540 vars->line_speed);
1541 break;
1542 }
1543 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1544 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1545
1546 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1547 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1548
1549 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1550 udelay(50);
1551
1552 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1553 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1554 ((params->mac_addr[2] << 24) |
1555 (params->mac_addr[3] << 16) |
1556 (params->mac_addr[4] << 8) |
1557 (params->mac_addr[5])));
1558 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1559 ((params->mac_addr[0] << 8) |
1560 (params->mac_addr[1])));
1561
1562 /* Enable RX and TX */
1563 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1564 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1565 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1566 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1567 udelay(50);
1568
1569 /* Remove SW Reset */
1570 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1571
1572 /* Check loopback mode */
1573 if (lb)
1574 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1575 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1576
1577 /*
1578 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1579 * length used by the MAC receive logic to check frames.
1580 */
1581 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1582 bnx2x_set_xumac_nig(params,
1583 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1584 vars->mac_type = MAC_TYPE_UMAC;
1585
1586 }
1587
1588 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1589 {
1590 u32 port4mode_ovwr_val;
1591 /* Check 4-port override enabled */
1592 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1593 if (port4mode_ovwr_val & (1<<0)) {
1594 /* Return 4-port mode override value */
1595 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1596 }
1597 /* Return 4-port mode from input pin */
1598 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1599 }
1600
1601 /* Define the XMAC mode */
1602 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1603 {
1604 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1605
1606 /**
1607 * In 4-port mode, need to set the mode only once, so if XMAC is
1608 * already out of reset, it means the mode has already been set,
1609 * and it must not* reset the XMAC again, since it controls both
1610 * ports of the path
1611 **/
1612
1613 if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1614 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1615 DP(NETIF_MSG_LINK,
1616 "XMAC already out of reset in 4-port mode\n");
1617 return;
1618 }
1619
1620 /* Hard reset */
1621 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1622 MISC_REGISTERS_RESET_REG_2_XMAC);
1623 usleep_range(1000, 1000);
1624
1625 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1626 MISC_REGISTERS_RESET_REG_2_XMAC);
1627 if (is_port4mode) {
1628 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1629
1630 /* Set the number of ports on the system side to up to 2 */
1631 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1632
1633 /* Set the number of ports on the Warp Core to 10G */
1634 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1635 } else {
1636 /* Set the number of ports on the system side to 1 */
1637 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1638 if (max_speed == SPEED_10000) {
1639 DP(NETIF_MSG_LINK,
1640 "Init XMAC to 10G x 1 port per path\n");
1641 /* Set the number of ports on the Warp Core to 10G */
1642 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1643 } else {
1644 DP(NETIF_MSG_LINK,
1645 "Init XMAC to 20G x 2 ports per path\n");
1646 /* Set the number of ports on the Warp Core to 20G */
1647 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1648 }
1649 }
1650 /* Soft reset */
1651 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1652 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1653 usleep_range(1000, 1000);
1654
1655 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1656 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1657
1658 }
1659
1660 static void bnx2x_xmac_disable(struct link_params *params)
1661 {
1662 u8 port = params->port;
1663 struct bnx2x *bp = params->bp;
1664 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1665
1666 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1667 MISC_REGISTERS_RESET_REG_2_XMAC) {
1668 /*
1669 * Send an indication to change the state in the NIG back to XON
1670 * Clearing this bit enables the next set of this bit to get
1671 * rising edge
1672 */
1673 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1674 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1675 (pfc_ctrl & ~(1<<1)));
1676 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1677 (pfc_ctrl | (1<<1)));
1678 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1679 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1680 usleep_range(1000, 1000);
1681 bnx2x_set_xumac_nig(params, 0, 0);
1682 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1683 XMAC_CTRL_REG_SOFT_RESET);
1684 }
1685 }
1686
1687 static int bnx2x_xmac_enable(struct link_params *params,
1688 struct link_vars *vars, u8 lb)
1689 {
1690 u32 val, xmac_base;
1691 struct bnx2x *bp = params->bp;
1692 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1693
1694 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1695
1696 bnx2x_xmac_init(bp, vars->line_speed);
1697
1698 /*
1699 * This register determines on which events the MAC will assert
1700 * error on the i/f to the NIG along w/ EOP.
1701 */
1702
1703 /*
1704 * This register tells the NIG whether to send traffic to UMAC
1705 * or XMAC
1706 */
1707 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1708
1709 /* Set Max packet size */
1710 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1711
1712 /* CRC append for Tx packets */
1713 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1714
1715 /* update PFC */
1716 bnx2x_update_pfc_xmac(params, vars, 0);
1717
1718 /* Enable TX and RX */
1719 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1720
1721 /* Check loopback mode */
1722 if (lb)
1723 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1724 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1725 bnx2x_set_xumac_nig(params,
1726 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1727
1728 vars->mac_type = MAC_TYPE_XMAC;
1729
1730 return 0;
1731 }
1732 static int bnx2x_emac_enable(struct link_params *params,
1733 struct link_vars *vars, u8 lb)
1734 {
1735 struct bnx2x *bp = params->bp;
1736 u8 port = params->port;
1737 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1738 u32 val;
1739
1740 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1741
1742 /* Disable BMAC */
1743 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1744 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1745
1746 /* enable emac and not bmac */
1747 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1748
1749 /* ASIC */
1750 if (vars->phy_flags & PHY_XGXS_FLAG) {
1751 u32 ser_lane = ((params->lane_config &
1752 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1753 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1754
1755 DP(NETIF_MSG_LINK, "XGXS\n");
1756 /* select the master lanes (out of 0-3) */
1757 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1758 /* select XGXS */
1759 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1760
1761 } else { /* SerDes */
1762 DP(NETIF_MSG_LINK, "SerDes\n");
1763 /* select SerDes */
1764 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1765 }
1766
1767 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1768 EMAC_RX_MODE_RESET);
1769 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1770 EMAC_TX_MODE_RESET);
1771
1772 if (CHIP_REV_IS_SLOW(bp)) {
1773 /* config GMII mode */
1774 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1775 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1776 } else { /* ASIC */
1777 /* pause enable/disable */
1778 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1779 EMAC_RX_MODE_FLOW_EN);
1780
1781 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1782 (EMAC_TX_MODE_EXT_PAUSE_EN |
1783 EMAC_TX_MODE_FLOW_EN));
1784 if (!(params->feature_config_flags &
1785 FEATURE_CONFIG_PFC_ENABLED)) {
1786 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1787 bnx2x_bits_en(bp, emac_base +
1788 EMAC_REG_EMAC_RX_MODE,
1789 EMAC_RX_MODE_FLOW_EN);
1790
1791 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1792 bnx2x_bits_en(bp, emac_base +
1793 EMAC_REG_EMAC_TX_MODE,
1794 (EMAC_TX_MODE_EXT_PAUSE_EN |
1795 EMAC_TX_MODE_FLOW_EN));
1796 } else
1797 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1798 EMAC_TX_MODE_FLOW_EN);
1799 }
1800
1801 /* KEEP_VLAN_TAG, promiscuous */
1802 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1803 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1804
1805 /*
1806 * Setting this bit causes MAC control frames (except for pause
1807 * frames) to be passed on for processing. This setting has no
1808 * affect on the operation of the pause frames. This bit effects
1809 * all packets regardless of RX Parser packet sorting logic.
1810 * Turn the PFC off to make sure we are in Xon state before
1811 * enabling it.
1812 */
1813 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1814 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1815 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1816 /* Enable PFC again */
1817 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1818 EMAC_REG_RX_PFC_MODE_RX_EN |
1819 EMAC_REG_RX_PFC_MODE_TX_EN |
1820 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1821
1822 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1823 ((0x0101 <<
1824 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1825 (0x00ff <<
1826 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1827 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1828 }
1829 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1830
1831 /* Set Loopback */
1832 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1833 if (lb)
1834 val |= 0x810;
1835 else
1836 val &= ~0x810;
1837 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1838
1839 /* enable emac */
1840 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1841
1842 /* enable emac for jumbo packets */
1843 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1844 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1845 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1846
1847 /* strip CRC */
1848 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1849
1850 /* disable the NIG in/out to the bmac */
1851 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1852 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1853 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1854
1855 /* enable the NIG in/out to the emac */
1856 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1857 val = 0;
1858 if ((params->feature_config_flags &
1859 FEATURE_CONFIG_PFC_ENABLED) ||
1860 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1861 val = 1;
1862
1863 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1864 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1865
1866 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1867
1868 vars->mac_type = MAC_TYPE_EMAC;
1869 return 0;
1870 }
1871
1872 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1873 struct link_vars *vars)
1874 {
1875 u32 wb_data[2];
1876 struct bnx2x *bp = params->bp;
1877 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1878 NIG_REG_INGRESS_BMAC0_MEM;
1879
1880 u32 val = 0x14;
1881 if ((!(params->feature_config_flags &
1882 FEATURE_CONFIG_PFC_ENABLED)) &&
1883 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1884 /* Enable BigMAC to react on received Pause packets */
1885 val |= (1<<5);
1886 wb_data[0] = val;
1887 wb_data[1] = 0;
1888 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1889
1890 /* tx control */
1891 val = 0xc0;
1892 if (!(params->feature_config_flags &
1893 FEATURE_CONFIG_PFC_ENABLED) &&
1894 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1895 val |= 0x800000;
1896 wb_data[0] = val;
1897 wb_data[1] = 0;
1898 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1899 }
1900
1901 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1902 struct link_vars *vars,
1903 u8 is_lb)
1904 {
1905 /*
1906 * Set rx control: Strip CRC and enable BigMAC to relay
1907 * control packets to the system as well
1908 */
1909 u32 wb_data[2];
1910 struct bnx2x *bp = params->bp;
1911 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1912 NIG_REG_INGRESS_BMAC0_MEM;
1913 u32 val = 0x14;
1914
1915 if ((!(params->feature_config_flags &
1916 FEATURE_CONFIG_PFC_ENABLED)) &&
1917 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1918 /* Enable BigMAC to react on received Pause packets */
1919 val |= (1<<5);
1920 wb_data[0] = val;
1921 wb_data[1] = 0;
1922 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1923 udelay(30);
1924
1925 /* Tx control */
1926 val = 0xc0;
1927 if (!(params->feature_config_flags &
1928 FEATURE_CONFIG_PFC_ENABLED) &&
1929 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1930 val |= 0x800000;
1931 wb_data[0] = val;
1932 wb_data[1] = 0;
1933 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1934
1935 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1936 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1937 /* Enable PFC RX & TX & STATS and set 8 COS */
1938 wb_data[0] = 0x0;
1939 wb_data[0] |= (1<<0); /* RX */
1940 wb_data[0] |= (1<<1); /* TX */
1941 wb_data[0] |= (1<<2); /* Force initial Xon */
1942 wb_data[0] |= (1<<3); /* 8 cos */
1943 wb_data[0] |= (1<<5); /* STATS */
1944 wb_data[1] = 0;
1945 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1946 wb_data, 2);
1947 /* Clear the force Xon */
1948 wb_data[0] &= ~(1<<2);
1949 } else {
1950 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1951 /* disable PFC RX & TX & STATS and set 8 COS */
1952 wb_data[0] = 0x8;
1953 wb_data[1] = 0;
1954 }
1955
1956 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1957
1958 /*
1959 * Set Time (based unit is 512 bit time) between automatic
1960 * re-sending of PP packets amd enable automatic re-send of
1961 * Per-Priroity Packet as long as pp_gen is asserted and
1962 * pp_disable is low.
1963 */
1964 val = 0x8000;
1965 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1966 val |= (1<<16); /* enable automatic re-send */
1967
1968 wb_data[0] = val;
1969 wb_data[1] = 0;
1970 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1971 wb_data, 2);
1972
1973 /* mac control */
1974 val = 0x3; /* Enable RX and TX */
1975 if (is_lb) {
1976 val |= 0x4; /* Local loopback */
1977 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1978 }
1979 /* When PFC enabled, Pass pause frames towards the NIG. */
1980 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1981 val |= ((1<<6)|(1<<5));
1982
1983 wb_data[0] = val;
1984 wb_data[1] = 0;
1985 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1986 }
1987
1988
1989 /* PFC BRB internal port configuration params */
1990 struct bnx2x_pfc_brb_threshold_val {
1991 u32 pause_xoff;
1992 u32 pause_xon;
1993 u32 full_xoff;
1994 u32 full_xon;
1995 };
1996
1997 struct bnx2x_pfc_brb_e3b0_val {
1998 u32 full_lb_xoff_th;
1999 u32 full_lb_xon_threshold;
2000 u32 lb_guarantied;
2001 u32 mac_0_class_t_guarantied;
2002 u32 mac_0_class_t_guarantied_hyst;
2003 u32 mac_1_class_t_guarantied;
2004 u32 mac_1_class_t_guarantied_hyst;
2005 };
2006
2007 struct bnx2x_pfc_brb_th_val {
2008 struct bnx2x_pfc_brb_threshold_val pauseable_th;
2009 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2010 };
2011 static int bnx2x_pfc_brb_get_config_params(
2012 struct link_params *params,
2013 struct bnx2x_pfc_brb_th_val *config_val)
2014 {
2015 struct bnx2x *bp = params->bp;
2016 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2017 if (CHIP_IS_E2(bp)) {
2018 config_val->pauseable_th.pause_xoff =
2019 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2020 config_val->pauseable_th.pause_xon =
2021 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2022 config_val->pauseable_th.full_xoff =
2023 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2024 config_val->pauseable_th.full_xon =
2025 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2026 /* non pause able*/
2027 config_val->non_pauseable_th.pause_xoff =
2028 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2029 config_val->non_pauseable_th.pause_xon =
2030 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2031 config_val->non_pauseable_th.full_xoff =
2032 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2033 config_val->non_pauseable_th.full_xon =
2034 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2035 } else if (CHIP_IS_E3A0(bp)) {
2036 config_val->pauseable_th.pause_xoff =
2037 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2038 config_val->pauseable_th.pause_xon =
2039 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2040 config_val->pauseable_th.full_xoff =
2041 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2042 config_val->pauseable_th.full_xon =
2043 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2044 /* non pause able*/
2045 config_val->non_pauseable_th.pause_xoff =
2046 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2047 config_val->non_pauseable_th.pause_xon =
2048 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2049 config_val->non_pauseable_th.full_xoff =
2050 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2051 config_val->non_pauseable_th.full_xon =
2052 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2053 } else if (CHIP_IS_E3B0(bp)) {
2054 if (params->phy[INT_PHY].flags &
2055 FLAGS_4_PORT_MODE) {
2056 config_val->pauseable_th.pause_xoff =
2057 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2058 config_val->pauseable_th.pause_xon =
2059 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2060 config_val->pauseable_th.full_xoff =
2061 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2062 config_val->pauseable_th.full_xon =
2063 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2064 /* non pause able*/
2065 config_val->non_pauseable_th.pause_xoff =
2066 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2067 config_val->non_pauseable_th.pause_xon =
2068 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2069 config_val->non_pauseable_th.full_xoff =
2070 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2071 config_val->non_pauseable_th.full_xon =
2072 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2073 } else {
2074 config_val->pauseable_th.pause_xoff =
2075 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2076 config_val->pauseable_th.pause_xon =
2077 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2078 config_val->pauseable_th.full_xoff =
2079 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2080 config_val->pauseable_th.full_xon =
2081 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2082 /* non pause able*/
2083 config_val->non_pauseable_th.pause_xoff =
2084 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2085 config_val->non_pauseable_th.pause_xon =
2086 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2087 config_val->non_pauseable_th.full_xoff =
2088 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2089 config_val->non_pauseable_th.full_xon =
2090 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2091 }
2092 } else
2093 return -EINVAL;
2094
2095 return 0;
2096 }
2097
2098
2099 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2100 struct bnx2x_pfc_brb_e3b0_val
2101 *e3b0_val,
2102 u32 cos0_pauseable,
2103 u32 cos1_pauseable)
2104 {
2105 if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2106 e3b0_val->full_lb_xoff_th =
2107 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2108 e3b0_val->full_lb_xon_threshold =
2109 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2110 e3b0_val->lb_guarantied =
2111 PFC_E3B0_4P_LB_GUART;
2112 e3b0_val->mac_0_class_t_guarantied =
2113 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2114 e3b0_val->mac_0_class_t_guarantied_hyst =
2115 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2116 e3b0_val->mac_1_class_t_guarantied =
2117 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2118 e3b0_val->mac_1_class_t_guarantied_hyst =
2119 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2120 } else {
2121 e3b0_val->full_lb_xoff_th =
2122 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2123 e3b0_val->full_lb_xon_threshold =
2124 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2125 e3b0_val->mac_0_class_t_guarantied_hyst =
2126 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2127 e3b0_val->mac_1_class_t_guarantied =
2128 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2129 e3b0_val->mac_1_class_t_guarantied_hyst =
2130 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2131
2132 if (cos0_pauseable != cos1_pauseable) {
2133 /* nonpauseable= Lossy + pauseable = Lossless*/
2134 e3b0_val->lb_guarantied =
2135 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2136 e3b0_val->mac_0_class_t_guarantied =
2137 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2138 } else if (cos0_pauseable) {
2139 /* Lossless +Lossless*/
2140 e3b0_val->lb_guarantied =
2141 PFC_E3B0_2P_PAUSE_LB_GUART;
2142 e3b0_val->mac_0_class_t_guarantied =
2143 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2144 } else {
2145 /* Lossy +Lossy*/
2146 e3b0_val->lb_guarantied =
2147 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2148 e3b0_val->mac_0_class_t_guarantied =
2149 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2150 }
2151 }
2152 }
2153 static int bnx2x_update_pfc_brb(struct link_params *params,
2154 struct link_vars *vars,
2155 struct bnx2x_nig_brb_pfc_port_params
2156 *pfc_params)
2157 {
2158 struct bnx2x *bp = params->bp;
2159 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2160 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2161 &config_val.pauseable_th;
2162 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2163 int set_pfc = params->feature_config_flags &
2164 FEATURE_CONFIG_PFC_ENABLED;
2165 int bnx2x_status = 0;
2166 u8 port = params->port;
2167
2168 /* default - pause configuration */
2169 reg_th_config = &config_val.pauseable_th;
2170 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2171 if (0 != bnx2x_status)
2172 return bnx2x_status;
2173
2174 if (set_pfc && pfc_params)
2175 /* First COS */
2176 if (!pfc_params->cos0_pauseable)
2177 reg_th_config = &config_val.non_pauseable_th;
2178 /*
2179 * The number of free blocks below which the pause signal to class 0
2180 * of MAC #n is asserted. n=0,1
2181 */
2182 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2183 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2184 reg_th_config->pause_xoff);
2185 /*
2186 * The number of free blocks above which the pause signal to class 0
2187 * of MAC #n is de-asserted. n=0,1
2188 */
2189 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2190 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2191 /*
2192 * The number of free blocks below which the full signal to class 0
2193 * of MAC #n is asserted. n=0,1
2194 */
2195 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2196 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2197 /*
2198 * The number of free blocks above which the full signal to class 0
2199 * of MAC #n is de-asserted. n=0,1
2200 */
2201 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2202 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2203
2204 if (set_pfc && pfc_params) {
2205 /* Second COS */
2206 if (pfc_params->cos1_pauseable)
2207 reg_th_config = &config_val.pauseable_th;
2208 else
2209 reg_th_config = &config_val.non_pauseable_th;
2210 /*
2211 * The number of free blocks below which the pause signal to
2212 * class 1 of MAC #n is asserted. n=0,1
2213 **/
2214 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2215 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2216 reg_th_config->pause_xoff);
2217 /*
2218 * The number of free blocks above which the pause signal to
2219 * class 1 of MAC #n is de-asserted. n=0,1
2220 */
2221 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2222 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2223 reg_th_config->pause_xon);
2224 /*
2225 * The number of free blocks below which the full signal to
2226 * class 1 of MAC #n is asserted. n=0,1
2227 */
2228 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2229 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2230 reg_th_config->full_xoff);
2231 /*
2232 * The number of free blocks above which the full signal to
2233 * class 1 of MAC #n is de-asserted. n=0,1
2234 */
2235 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2236 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2237 reg_th_config->full_xon);
2238
2239
2240 if (CHIP_IS_E3B0(bp)) {
2241 /*Should be done by init tool */
2242 /*
2243 * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2244 * reset value
2245 * 944
2246 */
2247
2248 /**
2249 * The hysteresis on the guarantied buffer space for the Lb port
2250 * before signaling XON.
2251 **/
2252 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2253
2254 bnx2x_pfc_brb_get_e3b0_config_params(
2255 params,
2256 &e3b0_val,
2257 pfc_params->cos0_pauseable,
2258 pfc_params->cos1_pauseable);
2259 /**
2260 * The number of free blocks below which the full signal to the
2261 * LB port is asserted.
2262 */
2263 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2264 e3b0_val.full_lb_xoff_th);
2265 /**
2266 * The number of free blocks above which the full signal to the
2267 * LB port is de-asserted.
2268 */
2269 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2270 e3b0_val.full_lb_xon_threshold);
2271 /**
2272 * The number of blocks guarantied for the MAC #n port. n=0,1
2273 */
2274
2275 /*The number of blocks guarantied for the LB port.*/
2276 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2277 e3b0_val.lb_guarantied);
2278
2279 /**
2280 * The number of blocks guarantied for the MAC #n port.
2281 */
2282 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2283 2 * e3b0_val.mac_0_class_t_guarantied);
2284 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2285 2 * e3b0_val.mac_1_class_t_guarantied);
2286 /**
2287 * The number of blocks guarantied for class #t in MAC0. t=0,1
2288 */
2289 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2290 e3b0_val.mac_0_class_t_guarantied);
2291 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2292 e3b0_val.mac_0_class_t_guarantied);
2293 /**
2294 * The hysteresis on the guarantied buffer space for class in
2295 * MAC0. t=0,1
2296 */
2297 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2298 e3b0_val.mac_0_class_t_guarantied_hyst);
2299 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2300 e3b0_val.mac_0_class_t_guarantied_hyst);
2301
2302 /**
2303 * The number of blocks guarantied for class #t in MAC1.t=0,1
2304 */
2305 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2306 e3b0_val.mac_1_class_t_guarantied);
2307 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2308 e3b0_val.mac_1_class_t_guarantied);
2309 /**
2310 * The hysteresis on the guarantied buffer space for class #t
2311 * in MAC1. t=0,1
2312 */
2313 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2314 e3b0_val.mac_1_class_t_guarantied_hyst);
2315 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2316 e3b0_val.mac_1_class_t_guarantied_hyst);
2317
2318 }
2319
2320 }
2321
2322 return bnx2x_status;
2323 }
2324
2325 /******************************************************************************
2326 * Description:
2327 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2328 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2329 ******************************************************************************/
2330 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2331 u8 cos_entry,
2332 u32 priority_mask, u8 port)
2333 {
2334 u32 nig_reg_rx_priority_mask_add = 0;
2335
2336 switch (cos_entry) {
2337 case 0:
2338 nig_reg_rx_priority_mask_add = (port) ?
2339 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2340 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2341 break;
2342 case 1:
2343 nig_reg_rx_priority_mask_add = (port) ?
2344 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2345 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2346 break;
2347 case 2:
2348 nig_reg_rx_priority_mask_add = (port) ?
2349 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2350 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2351 break;
2352 case 3:
2353 if (port)
2354 return -EINVAL;
2355 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2356 break;
2357 case 4:
2358 if (port)
2359 return -EINVAL;
2360 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2361 break;
2362 case 5:
2363 if (port)
2364 return -EINVAL;
2365 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2366 break;
2367 }
2368
2369 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2370
2371 return 0;
2372 }
2373 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2374 {
2375 struct bnx2x *bp = params->bp;
2376
2377 REG_WR(bp, params->shmem_base +
2378 offsetof(struct shmem_region,
2379 port_mb[params->port].link_status), link_status);
2380 }
2381
2382 static void bnx2x_update_pfc_nig(struct link_params *params,
2383 struct link_vars *vars,
2384 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2385 {
2386 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2387 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2388 u32 pkt_priority_to_cos = 0;
2389 struct bnx2x *bp = params->bp;
2390 u8 port = params->port;
2391
2392 int set_pfc = params->feature_config_flags &
2393 FEATURE_CONFIG_PFC_ENABLED;
2394 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2395
2396 /*
2397 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2398 * MAC control frames (that are not pause packets)
2399 * will be forwarded to the XCM.
2400 */
2401 xcm_mask = REG_RD(bp,
2402 port ? NIG_REG_LLH1_XCM_MASK :
2403 NIG_REG_LLH0_XCM_MASK);
2404 /*
2405 * nig params will override non PFC params, since it's possible to
2406 * do transition from PFC to SAFC
2407 */
2408 if (set_pfc) {
2409 pause_enable = 0;
2410 llfc_out_en = 0;
2411 llfc_enable = 0;
2412 if (CHIP_IS_E3(bp))
2413 ppp_enable = 0;
2414 else
2415 ppp_enable = 1;
2416 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2417 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2418 xcm0_out_en = 0;
2419 p0_hwpfc_enable = 1;
2420 } else {
2421 if (nig_params) {
2422 llfc_out_en = nig_params->llfc_out_en;
2423 llfc_enable = nig_params->llfc_enable;
2424 pause_enable = nig_params->pause_enable;
2425 } else /*defaul non PFC mode - PAUSE */
2426 pause_enable = 1;
2427
2428 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2429 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2430 xcm0_out_en = 1;
2431 }
2432
2433 if (CHIP_IS_E3(bp))
2434 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2435 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2436 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2437 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2438 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2439 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2440 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2441 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2442
2443 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2444 NIG_REG_PPP_ENABLE_0, ppp_enable);
2445
2446 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2447 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2448
2449 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2450
2451 /* output enable for RX_XCM # IF */
2452 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2453
2454 /* HW PFC TX enable */
2455 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2456
2457 if (nig_params) {
2458 u8 i = 0;
2459 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2460
2461 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2462 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2463 nig_params->rx_cos_priority_mask[i], port);
2464
2465 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2466 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2467 nig_params->llfc_high_priority_classes);
2468
2469 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2470 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2471 nig_params->llfc_low_priority_classes);
2472 }
2473 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2474 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2475 pkt_priority_to_cos);
2476 }
2477
2478 int bnx2x_update_pfc(struct link_params *params,
2479 struct link_vars *vars,
2480 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2481 {
2482 /*
2483 * The PFC and pause are orthogonal to one another, meaning when
2484 * PFC is enabled, the pause are disabled, and when PFC is
2485 * disabled, pause are set according to the pause result.
2486 */
2487 u32 val;
2488 struct bnx2x *bp = params->bp;
2489 int bnx2x_status = 0;
2490 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2491
2492 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2493 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2494 else
2495 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2496
2497 bnx2x_update_mng(params, vars->link_status);
2498
2499 /* update NIG params */
2500 bnx2x_update_pfc_nig(params, vars, pfc_params);
2501
2502 /* update BRB params */
2503 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2504 if (0 != bnx2x_status)
2505 return bnx2x_status;
2506
2507 if (!vars->link_up)
2508 return bnx2x_status;
2509
2510 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2511 if (CHIP_IS_E3(bp))
2512 bnx2x_update_pfc_xmac(params, vars, 0);
2513 else {
2514 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2515 if ((val &
2516 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2517 == 0) {
2518 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2519 bnx2x_emac_enable(params, vars, 0);
2520 return bnx2x_status;
2521 }
2522
2523 if (CHIP_IS_E2(bp))
2524 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2525 else
2526 bnx2x_update_pfc_bmac1(params, vars);
2527
2528 val = 0;
2529 if ((params->feature_config_flags &
2530 FEATURE_CONFIG_PFC_ENABLED) ||
2531 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2532 val = 1;
2533 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2534 }
2535 return bnx2x_status;
2536 }
2537
2538
2539 static int bnx2x_bmac1_enable(struct link_params *params,
2540 struct link_vars *vars,
2541 u8 is_lb)
2542 {
2543 struct bnx2x *bp = params->bp;
2544 u8 port = params->port;
2545 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2546 NIG_REG_INGRESS_BMAC0_MEM;
2547 u32 wb_data[2];
2548 u32 val;
2549
2550 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2551
2552 /* XGXS control */
2553 wb_data[0] = 0x3c;
2554 wb_data[1] = 0;
2555 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2556 wb_data, 2);
2557
2558 /* tx MAC SA */
2559 wb_data[0] = ((params->mac_addr[2] << 24) |
2560 (params->mac_addr[3] << 16) |
2561 (params->mac_addr[4] << 8) |
2562 params->mac_addr[5]);
2563 wb_data[1] = ((params->mac_addr[0] << 8) |
2564 params->mac_addr[1]);
2565 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2566
2567 /* mac control */
2568 val = 0x3;
2569 if (is_lb) {
2570 val |= 0x4;
2571 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2572 }
2573 wb_data[0] = val;
2574 wb_data[1] = 0;
2575 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2576
2577 /* set rx mtu */
2578 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2579 wb_data[1] = 0;
2580 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2581
2582 bnx2x_update_pfc_bmac1(params, vars);
2583
2584 /* set tx mtu */
2585 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2586 wb_data[1] = 0;
2587 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2588
2589 /* set cnt max size */
2590 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2591 wb_data[1] = 0;
2592 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2593
2594 /* configure safc */
2595 wb_data[0] = 0x1000200;
2596 wb_data[1] = 0;
2597 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2598 wb_data, 2);
2599
2600 return 0;
2601 }
2602
2603 static int bnx2x_bmac2_enable(struct link_params *params,
2604 struct link_vars *vars,
2605 u8 is_lb)
2606 {
2607 struct bnx2x *bp = params->bp;
2608 u8 port = params->port;
2609 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2610 NIG_REG_INGRESS_BMAC0_MEM;
2611 u32 wb_data[2];
2612
2613 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2614
2615 wb_data[0] = 0;
2616 wb_data[1] = 0;
2617 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2618 udelay(30);
2619
2620 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2621 wb_data[0] = 0x3c;
2622 wb_data[1] = 0;
2623 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2624 wb_data, 2);
2625
2626 udelay(30);
2627
2628 /* tx MAC SA */
2629 wb_data[0] = ((params->mac_addr[2] << 24) |
2630 (params->mac_addr[3] << 16) |
2631 (params->mac_addr[4] << 8) |
2632 params->mac_addr[5]);
2633 wb_data[1] = ((params->mac_addr[0] << 8) |
2634 params->mac_addr[1]);
2635 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2636 wb_data, 2);
2637
2638 udelay(30);
2639
2640 /* Configure SAFC */
2641 wb_data[0] = 0x1000200;
2642 wb_data[1] = 0;
2643 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2644 wb_data, 2);
2645 udelay(30);
2646
2647 /* set rx mtu */
2648 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2649 wb_data[1] = 0;
2650 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2651 udelay(30);
2652
2653 /* set tx mtu */
2654 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2655 wb_data[1] = 0;
2656 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2657 udelay(30);
2658 /* set cnt max size */
2659 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2660 wb_data[1] = 0;
2661 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2662 udelay(30);
2663 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2664
2665 return 0;
2666 }
2667
2668 static int bnx2x_bmac_enable(struct link_params *params,
2669 struct link_vars *vars,
2670 u8 is_lb)
2671 {
2672 int rc = 0;
2673 u8 port = params->port;
2674 struct bnx2x *bp = params->bp;
2675 u32 val;
2676 /* reset and unreset the BigMac */
2677 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2678 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2679 msleep(1);
2680
2681 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2682 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2683
2684 /* enable access for bmac registers */
2685 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2686
2687 /* Enable BMAC according to BMAC type*/
2688 if (CHIP_IS_E2(bp))
2689 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2690 else
2691 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2692 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2693 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2694 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2695 val = 0;
2696 if ((params->feature_config_flags &
2697 FEATURE_CONFIG_PFC_ENABLED) ||
2698 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2699 val = 1;
2700 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2701 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2702 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2703 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2704 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2705 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2706
2707 vars->mac_type = MAC_TYPE_BMAC;
2708 return rc;
2709 }
2710
2711 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2712 {
2713 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2714 NIG_REG_INGRESS_BMAC0_MEM;
2715 u32 wb_data[2];
2716 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2717
2718 /* Only if the bmac is out of reset */
2719 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2720 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2721 nig_bmac_enable) {
2722
2723 if (CHIP_IS_E2(bp)) {
2724 /* Clear Rx Enable bit in BMAC_CONTROL register */
2725 REG_RD_DMAE(bp, bmac_addr +
2726 BIGMAC2_REGISTER_BMAC_CONTROL,
2727 wb_data, 2);
2728 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2729 REG_WR_DMAE(bp, bmac_addr +
2730 BIGMAC2_REGISTER_BMAC_CONTROL,
2731 wb_data, 2);
2732 } else {
2733 /* Clear Rx Enable bit in BMAC_CONTROL register */
2734 REG_RD_DMAE(bp, bmac_addr +
2735 BIGMAC_REGISTER_BMAC_CONTROL,
2736 wb_data, 2);
2737 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2738 REG_WR_DMAE(bp, bmac_addr +
2739 BIGMAC_REGISTER_BMAC_CONTROL,
2740 wb_data, 2);
2741 }
2742 msleep(1);
2743 }
2744 }
2745
2746 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2747 u32 line_speed)
2748 {
2749 struct bnx2x *bp = params->bp;
2750 u8 port = params->port;
2751 u32 init_crd, crd;
2752 u32 count = 1000;
2753
2754 /* disable port */
2755 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2756
2757 /* wait for init credit */
2758 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2759 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2760 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2761
2762 while ((init_crd != crd) && count) {
2763 msleep(5);
2764
2765 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2766 count--;
2767 }
2768 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2769 if (init_crd != crd) {
2770 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2771 init_crd, crd);
2772 return -EINVAL;
2773 }
2774
2775 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2776 line_speed == SPEED_10 ||
2777 line_speed == SPEED_100 ||
2778 line_speed == SPEED_1000 ||
2779 line_speed == SPEED_2500) {
2780 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2781 /* update threshold */
2782 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2783 /* update init credit */
2784 init_crd = 778; /* (800-18-4) */
2785
2786 } else {
2787 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2788 ETH_OVREHEAD)/16;
2789 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2790 /* update threshold */
2791 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2792 /* update init credit */
2793 switch (line_speed) {
2794 case SPEED_10000:
2795 init_crd = thresh + 553 - 22;
2796 break;
2797 default:
2798 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2799 line_speed);
2800 return -EINVAL;
2801 }
2802 }
2803 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2804 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2805 line_speed, init_crd);
2806
2807 /* probe the credit changes */
2808 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2809 msleep(5);
2810 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2811
2812 /* enable port */
2813 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2814 return 0;
2815 }
2816
2817 /**
2818 * bnx2x_get_emac_base - retrive emac base address
2819 *
2820 * @bp: driver handle
2821 * @mdc_mdio_access: access type
2822 * @port: port id
2823 *
2824 * This function selects the MDC/MDIO access (through emac0 or
2825 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2826 * phy has a default access mode, which could also be overridden
2827 * by nvram configuration. This parameter, whether this is the
2828 * default phy configuration, or the nvram overrun
2829 * configuration, is passed here as mdc_mdio_access and selects
2830 * the emac_base for the CL45 read/writes operations
2831 */
2832 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2833 u32 mdc_mdio_access, u8 port)
2834 {
2835 u32 emac_base = 0;
2836 switch (mdc_mdio_access) {
2837 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2838 break;
2839 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2840 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2841 emac_base = GRCBASE_EMAC1;
2842 else
2843 emac_base = GRCBASE_EMAC0;
2844 break;
2845 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2846 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2847 emac_base = GRCBASE_EMAC0;
2848 else
2849 emac_base = GRCBASE_EMAC1;
2850 break;
2851 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2852 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2853 break;
2854 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2855 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2856 break;
2857 default:
2858 break;
2859 }
2860 return emac_base;
2861
2862 }
2863
2864 /******************************************************************/
2865 /* CL22 access functions */
2866 /******************************************************************/
2867 static int bnx2x_cl22_write(struct bnx2x *bp,
2868 struct bnx2x_phy *phy,
2869 u16 reg, u16 val)
2870 {
2871 u32 tmp, mode;
2872 u8 i;
2873 int rc = 0;
2874 /* Switch to CL22 */
2875 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2876 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2877 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2878
2879 /* address */
2880 tmp = ((phy->addr << 21) | (reg << 16) | val |
2881 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2882 EMAC_MDIO_COMM_START_BUSY);
2883 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2884
2885 for (i = 0; i < 50; i++) {
2886 udelay(10);
2887
2888 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2889 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2890 udelay(5);
2891 break;
2892 }
2893 }
2894 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2895 DP(NETIF_MSG_LINK, "write phy register failed\n");
2896 rc = -EFAULT;
2897 }
2898 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2899 return rc;
2900 }
2901
2902 static int bnx2x_cl22_read(struct bnx2x *bp,
2903 struct bnx2x_phy *phy,
2904 u16 reg, u16 *ret_val)
2905 {
2906 u32 val, mode;
2907 u16 i;
2908 int rc = 0;
2909
2910 /* Switch to CL22 */
2911 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2912 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2913 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2914
2915 /* address */
2916 val = ((phy->addr << 21) | (reg << 16) |
2917 EMAC_MDIO_COMM_COMMAND_READ_22 |
2918 EMAC_MDIO_COMM_START_BUSY);
2919 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2920
2921 for (i = 0; i < 50; i++) {
2922 udelay(10);
2923
2924 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2925 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2926 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2927 udelay(5);
2928 break;
2929 }
2930 }
2931 if (val & EMAC_MDIO_COMM_START_BUSY) {
2932 DP(NETIF_MSG_LINK, "read phy register failed\n");
2933
2934 *ret_val = 0;
2935 rc = -EFAULT;
2936 }
2937 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2938 return rc;
2939 }
2940
2941 /******************************************************************/
2942 /* CL45 access functions */
2943 /******************************************************************/
2944 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2945 u8 devad, u16 reg, u16 *ret_val)
2946 {
2947 u32 val;
2948 u16 i;
2949 int rc = 0;
2950 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2951 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2952 EMAC_MDIO_STATUS_10MB);
2953 /* address */
2954 val = ((phy->addr << 21) | (devad << 16) | reg |
2955 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2956 EMAC_MDIO_COMM_START_BUSY);
2957 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2958
2959 for (i = 0; i < 50; i++) {
2960 udelay(10);
2961
2962 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2963 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2964 udelay(5);
2965 break;
2966 }
2967 }
2968 if (val & EMAC_MDIO_COMM_START_BUSY) {
2969 DP(NETIF_MSG_LINK, "read phy register failed\n");
2970 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2971 *ret_val = 0;
2972 rc = -EFAULT;
2973 } else {
2974 /* data */
2975 val = ((phy->addr << 21) | (devad << 16) |
2976 EMAC_MDIO_COMM_COMMAND_READ_45 |
2977 EMAC_MDIO_COMM_START_BUSY);
2978 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2979
2980 for (i = 0; i < 50; i++) {
2981 udelay(10);
2982
2983 val = REG_RD(bp, phy->mdio_ctrl +
2984 EMAC_REG_EMAC_MDIO_COMM);
2985 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2986 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2987 break;
2988 }
2989 }
2990 if (val & EMAC_MDIO_COMM_START_BUSY) {
2991 DP(NETIF_MSG_LINK, "read phy register failed\n");
2992 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2993 *ret_val = 0;
2994 rc = -EFAULT;
2995 }
2996 }
2997 /* Work around for E3 A0 */
2998 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2999 phy->flags ^= FLAGS_DUMMY_READ;
3000 if (phy->flags & FLAGS_DUMMY_READ) {
3001 u16 temp_val;
3002 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3003 }
3004 }
3005
3006 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3007 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3008 EMAC_MDIO_STATUS_10MB);
3009 return rc;
3010 }
3011
3012 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3013 u8 devad, u16 reg, u16 val)
3014 {
3015 u32 tmp;
3016 u8 i;
3017 int rc = 0;
3018 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3019 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3020 EMAC_MDIO_STATUS_10MB);
3021
3022 /* address */
3023
3024 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3025 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3026 EMAC_MDIO_COMM_START_BUSY);
3027 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3028
3029 for (i = 0; i < 50; i++) {
3030 udelay(10);
3031
3032 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3033 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3034 udelay(5);
3035 break;
3036 }
3037 }
3038 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3039 DP(NETIF_MSG_LINK, "write phy register failed\n");
3040 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3041 rc = -EFAULT;
3042
3043 } else {
3044 /* data */
3045 tmp = ((phy->addr << 21) | (devad << 16) | val |
3046 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3047 EMAC_MDIO_COMM_START_BUSY);
3048 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3049
3050 for (i = 0; i < 50; i++) {
3051 udelay(10);
3052
3053 tmp = REG_RD(bp, phy->mdio_ctrl +
3054 EMAC_REG_EMAC_MDIO_COMM);
3055 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3056 udelay(5);
3057 break;
3058 }
3059 }
3060 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3061 DP(NETIF_MSG_LINK, "write phy register failed\n");
3062 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3063 rc = -EFAULT;
3064 }
3065 }
3066 /* Work around for E3 A0 */
3067 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3068 phy->flags ^= FLAGS_DUMMY_READ;
3069 if (phy->flags & FLAGS_DUMMY_READ) {
3070 u16 temp_val;
3071 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3072 }
3073 }
3074 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3075 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3076 EMAC_MDIO_STATUS_10MB);
3077 return rc;
3078 }
3079
3080
3081 /******************************************************************/
3082 /* BSC access functions from E3 */
3083 /******************************************************************/
3084 static void bnx2x_bsc_module_sel(struct link_params *params)
3085 {
3086 int idx;
3087 u32 board_cfg, sfp_ctrl;
3088 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3089 struct bnx2x *bp = params->bp;
3090 u8 port = params->port;
3091 /* Read I2C output PINs */
3092 board_cfg = REG_RD(bp, params->shmem_base +
3093 offsetof(struct shmem_region,
3094 dev_info.shared_hw_config.board));
3095 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3096 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3097 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3098
3099 /* Read I2C output value */
3100 sfp_ctrl = REG_RD(bp, params->shmem_base +
3101 offsetof(struct shmem_region,
3102 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3103 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3104 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3105 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3106 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3107 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3108 }
3109
3110 static int bnx2x_bsc_read(struct link_params *params,
3111 struct bnx2x_phy *phy,
3112 u8 sl_devid,
3113 u16 sl_addr,
3114 u8 lc_addr,
3115 u8 xfer_cnt,
3116 u32 *data_array)
3117 {
3118 u32 val, i;
3119 int rc = 0;
3120 struct bnx2x *bp = params->bp;
3121
3122 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3123 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3124 return -EINVAL;
3125 }
3126
3127 if (xfer_cnt > 16) {
3128 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3129 xfer_cnt);
3130 return -EINVAL;
3131 }
3132 bnx2x_bsc_module_sel(params);
3133
3134 xfer_cnt = 16 - lc_addr;
3135
3136 /* enable the engine */
3137 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3138 val |= MCPR_IMC_COMMAND_ENABLE;
3139 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3140
3141 /* program slave device ID */
3142 val = (sl_devid << 16) | sl_addr;
3143 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3144
3145 /* start xfer with 0 byte to update the address pointer ???*/
3146 val = (MCPR_IMC_COMMAND_ENABLE) |
3147 (MCPR_IMC_COMMAND_WRITE_OP <<
3148 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3149 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3150 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3151
3152 /* poll for completion */
3153 i = 0;
3154 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3155 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3156 udelay(10);
3157 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3158 if (i++ > 1000) {
3159 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3160 i);
3161 rc = -EFAULT;
3162 break;
3163 }
3164 }
3165 if (rc == -EFAULT)
3166 return rc;
3167
3168 /* start xfer with read op */
3169 val = (MCPR_IMC_COMMAND_ENABLE) |
3170 (MCPR_IMC_COMMAND_READ_OP <<
3171 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3172 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3173 (xfer_cnt);
3174 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3175
3176 /* poll for completion */
3177 i = 0;
3178 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3179 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3180 udelay(10);
3181 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3182 if (i++ > 1000) {
3183 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3184 rc = -EFAULT;
3185 break;
3186 }
3187 }
3188 if (rc == -EFAULT)
3189 return rc;
3190
3191 for (i = (lc_addr >> 2); i < 4; i++) {
3192 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3193 #ifdef __BIG_ENDIAN
3194 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3195 ((data_array[i] & 0x0000ff00) << 8) |
3196 ((data_array[i] & 0x00ff0000) >> 8) |
3197 ((data_array[i] & 0xff000000) >> 24);
3198 #endif
3199 }
3200 return rc;
3201 }
3202
3203 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3204 u8 devad, u16 reg, u16 or_val)
3205 {
3206 u16 val;
3207 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3208 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3209 }
3210
3211 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3212 u8 devad, u16 reg, u16 *ret_val)
3213 {
3214 u8 phy_index;
3215 /*
3216 * Probe for the phy according to the given phy_addr, and execute
3217 * the read request on it
3218 */
3219 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3220 if (params->phy[phy_index].addr == phy_addr) {
3221 return bnx2x_cl45_read(params->bp,
3222 &params->phy[phy_index], devad,
3223 reg, ret_val);
3224 }
3225 }
3226 return -EINVAL;
3227 }
3228
3229 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3230 u8 devad, u16 reg, u16 val)
3231 {
3232 u8 phy_index;
3233 /*
3234 * Probe for the phy according to the given phy_addr, and execute
3235 * the write request on it
3236 */
3237 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3238 if (params->phy[phy_index].addr == phy_addr) {
3239 return bnx2x_cl45_write(params->bp,
3240 &params->phy[phy_index], devad,
3241 reg, val);
3242 }
3243 }
3244 return -EINVAL;
3245 }
3246 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3247 struct link_params *params)
3248 {
3249 u8 lane = 0;
3250 struct bnx2x *bp = params->bp;
3251 u32 path_swap, path_swap_ovr;
3252 u8 path, port;
3253
3254 path = BP_PATH(bp);
3255 port = params->port;
3256
3257 if (bnx2x_is_4_port_mode(bp)) {
3258 u32 port_swap, port_swap_ovr;
3259
3260 /*figure out path swap value */
3261 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3262 if (path_swap_ovr & 0x1)
3263 path_swap = (path_swap_ovr & 0x2);
3264 else
3265 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3266
3267 if (path_swap)
3268 path = path ^ 1;
3269
3270 /*figure out port swap value */
3271 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3272 if (port_swap_ovr & 0x1)
3273 port_swap = (port_swap_ovr & 0x2);
3274 else
3275 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3276
3277 if (port_swap)
3278 port = port ^ 1;
3279
3280 lane = (port<<1) + path;
3281 } else { /* two port mode - no port swap */
3282
3283 /*figure out path swap value */
3284 path_swap_ovr =
3285 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3286 if (path_swap_ovr & 0x1) {
3287 path_swap = (path_swap_ovr & 0x2);
3288 } else {
3289 path_swap =
3290 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3291 }
3292 if (path_swap)
3293 path = path ^ 1;
3294
3295 lane = path << 1 ;
3296 }
3297 return lane;
3298 }
3299
3300 static void bnx2x_set_aer_mmd(struct link_params *params,
3301 struct bnx2x_phy *phy)
3302 {
3303 u32 ser_lane;
3304 u16 offset, aer_val;
3305 struct bnx2x *bp = params->bp;
3306 ser_lane = ((params->lane_config &
3307 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3308 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3309
3310 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3311 (phy->addr + ser_lane) : 0;
3312
3313 if (USES_WARPCORE(bp)) {
3314 aer_val = bnx2x_get_warpcore_lane(phy, params);
3315 /*
3316 * In Dual-lane mode, two lanes are joined together,
3317 * so in order to configure them, the AER broadcast method is
3318 * used here.
3319 * 0x200 is the broadcast address for lanes 0,1
3320 * 0x201 is the broadcast address for lanes 2,3
3321 */
3322 if (phy->flags & FLAGS_WC_DUAL_MODE)
3323 aer_val = (aer_val >> 1) | 0x200;
3324 } else if (CHIP_IS_E2(bp))
3325 aer_val = 0x3800 + offset - 1;
3326 else
3327 aer_val = 0x3800 + offset;
3328 DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3329 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3330 MDIO_AER_BLOCK_AER_REG, aer_val);
3331
3332 }
3333
3334 /******************************************************************/
3335 /* Internal phy section */
3336 /******************************************************************/
3337
3338 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3339 {
3340 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3341
3342 /* Set Clause 22 */
3343 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3344 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3345 udelay(500);
3346 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3347 udelay(500);
3348 /* Set Clause 45 */
3349 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3350 }
3351
3352 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3353 {
3354 u32 val;
3355
3356 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3357
3358 val = SERDES_RESET_BITS << (port*16);
3359
3360 /* reset and unreset the SerDes/XGXS */
3361 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3362 udelay(500);
3363 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3364
3365 bnx2x_set_serdes_access(bp, port);
3366
3367 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3368 DEFAULT_PHY_DEV_ADDR);
3369 }
3370
3371 static void bnx2x_xgxs_deassert(struct link_params *params)
3372 {
3373 struct bnx2x *bp = params->bp;
3374 u8 port;
3375 u32 val;
3376 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3377 port = params->port;
3378
3379 val = XGXS_RESET_BITS << (port*16);
3380
3381 /* reset and unreset the SerDes/XGXS */
3382 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3383 udelay(500);
3384 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3385
3386 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3387 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3388 params->phy[INT_PHY].def_md_devad);
3389 }
3390
3391 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3392 struct link_params *params, u16 *ieee_fc)
3393 {
3394 struct bnx2x *bp = params->bp;
3395 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3396 /**
3397 * resolve pause mode and advertisement Please refer to Table
3398 * 28B-3 of the 802.3ab-1999 spec
3399 */
3400
3401 switch (phy->req_flow_ctrl) {
3402 case BNX2X_FLOW_CTRL_AUTO:
3403 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3404 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3405 else
3406 *ieee_fc |=
3407 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3408 break;
3409
3410 case BNX2X_FLOW_CTRL_TX:
3411 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3412 break;
3413
3414 case BNX2X_FLOW_CTRL_RX:
3415 case BNX2X_FLOW_CTRL_BOTH:
3416 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3417 break;
3418
3419 case BNX2X_FLOW_CTRL_NONE:
3420 default:
3421 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3422 break;
3423 }
3424 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3425 }
3426
3427 static void set_phy_vars(struct link_params *params,
3428 struct link_vars *vars)
3429 {
3430 struct bnx2x *bp = params->bp;
3431 u8 actual_phy_idx, phy_index, link_cfg_idx;
3432 u8 phy_config_swapped = params->multi_phy_config &
3433 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3434 for (phy_index = INT_PHY; phy_index < params->num_phys;
3435 phy_index++) {
3436 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3437 actual_phy_idx = phy_index;
3438 if (phy_config_swapped) {
3439 if (phy_index == EXT_PHY1)
3440 actual_phy_idx = EXT_PHY2;
3441 else if (phy_index == EXT_PHY2)
3442 actual_phy_idx = EXT_PHY1;
3443 }
3444 params->phy[actual_phy_idx].req_flow_ctrl =
3445 params->req_flow_ctrl[link_cfg_idx];
3446
3447 params->phy[actual_phy_idx].req_line_speed =
3448 params->req_line_speed[link_cfg_idx];
3449
3450 params->phy[actual_phy_idx].speed_cap_mask =
3451 params->speed_cap_mask[link_cfg_idx];
3452
3453 params->phy[actual_phy_idx].req_duplex =
3454 params->req_duplex[link_cfg_idx];
3455
3456 if (params->req_line_speed[link_cfg_idx] ==
3457 SPEED_AUTO_NEG)
3458 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3459
3460 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3461 " speed_cap_mask %x\n",
3462 params->phy[actual_phy_idx].req_flow_ctrl,
3463 params->phy[actual_phy_idx].req_line_speed,
3464 params->phy[actual_phy_idx].speed_cap_mask);
3465 }
3466 }
3467
3468 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3469 struct bnx2x_phy *phy,
3470 struct link_vars *vars)
3471 {
3472 u16 val;
3473 struct bnx2x *bp = params->bp;
3474 /* read modify write pause advertizing */
3475 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3476
3477 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3478
3479 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3480 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3481 if ((vars->ieee_fc &
3482 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3483 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3484 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3485 }
3486 if ((vars->ieee_fc &
3487 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3488 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3489 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3490 }
3491 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3492 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3493 }
3494
3495 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3496 { /* LD LP */
3497 switch (pause_result) { /* ASYM P ASYM P */
3498 case 0xb: /* 1 0 1 1 */
3499 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3500 break;
3501
3502 case 0xe: /* 1 1 1 0 */
3503 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3504 break;
3505
3506 case 0x5: /* 0 1 0 1 */
3507 case 0x7: /* 0 1 1 1 */
3508 case 0xd: /* 1 1 0 1 */
3509 case 0xf: /* 1 1 1 1 */
3510 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3511 break;
3512
3513 default:
3514 break;
3515 }
3516 if (pause_result & (1<<0))
3517 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3518 if (pause_result & (1<<1))
3519 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3520 }
3521
3522 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3523 struct link_params *params,
3524 struct link_vars *vars)
3525 {
3526 struct bnx2x *bp = params->bp;
3527 u16 ld_pause; /* local */
3528 u16 lp_pause; /* link partner */
3529 u16 pause_result;
3530 u8 ret = 0;
3531 /* read twice */
3532
3533 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3534
3535 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3536 vars->flow_ctrl = phy->req_flow_ctrl;
3537 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3538 vars->flow_ctrl = params->req_fc_auto_adv;
3539 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3540 ret = 1;
3541 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3542 bnx2x_cl22_read(bp, phy,
3543 0x4, &ld_pause);
3544 bnx2x_cl22_read(bp, phy,
3545 0x5, &lp_pause);
3546 } else {
3547 bnx2x_cl45_read(bp, phy,
3548 MDIO_AN_DEVAD,
3549 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3550 bnx2x_cl45_read(bp, phy,
3551 MDIO_AN_DEVAD,
3552 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3553 }
3554 pause_result = (ld_pause &
3555 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3556 pause_result |= (lp_pause &
3557 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3558 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3559 pause_result);
3560 bnx2x_pause_resolve(vars, pause_result);
3561 }
3562 return ret;
3563 }
3564 /******************************************************************/
3565 /* Warpcore section */
3566 /******************************************************************/
3567 /* The init_internal_warpcore should mirror the xgxs,
3568 * i.e. reset the lane (if needed), set aer for the
3569 * init configuration, and set/clear SGMII flag. Internal
3570 * phy init is done purely in phy_init stage.
3571 */
3572 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3573 struct link_params *params,
3574 struct link_vars *vars) {
3575 u16 val16 = 0, lane, bam37 = 0;
3576 struct bnx2x *bp = params->bp;
3577 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3578 /* Check adding advertisement for 1G KX */
3579 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3580 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3581 (vars->line_speed == SPEED_1000)) {
3582 u16 sd_digital;
3583 val16 |= (1<<5);
3584
3585 /* Enable CL37 1G Parallel Detect */
3586 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3587 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3588 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3589 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3590 (sd_digital | 0x1));
3591
3592 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3593 }
3594 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3595 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3596 (vars->line_speed == SPEED_10000)) {
3597 /* Check adding advertisement for 10G KR */
3598 val16 |= (1<<7);
3599 /* Enable 10G Parallel Detect */
3600 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3601 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3602
3603 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3604 }
3605
3606 /* Set Transmit PMD settings */
3607 lane = bnx2x_get_warpcore_lane(phy, params);
3608 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3609 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3610 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3611 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3612 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3613 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3614 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3615 0x03f0);
3616 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3617 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3618 0x03f0);
3619 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3620 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3621 0x383f);
3622
3623 /* Advertised speeds */
3624 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3625 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3626
3627 /* Advertised and set FEC (Forward Error Correction) */
3628 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3629 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3630 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3631 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3632
3633 /* Enable CL37 BAM */
3634 if (REG_RD(bp, params->shmem_base +
3635 offsetof(struct shmem_region, dev_info.
3636 port_hw_config[params->port].default_cfg)) &
3637 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3638 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3639 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3640 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3641 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3642 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3643 }
3644
3645 /* Advertise pause */
3646 bnx2x_ext_phy_set_pause(params, phy, vars);
3647
3648 /* Enable Autoneg */
3649 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3650 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3651
3652 /* Over 1G - AN local device user page 1 */
3653 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3654 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3655
3656 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3657 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3658
3659 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3660 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3661 }
3662
3663 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3664 struct link_params *params,
3665 struct link_vars *vars)
3666 {
3667 struct bnx2x *bp = params->bp;
3668 u16 val;
3669
3670 /* Disable Autoneg */
3671 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3672 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3673
3674 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3675 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3676
3677 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3678 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3679
3680 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3681 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3682
3683 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3684 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3685
3686 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3687 MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3688
3689 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3690 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3691
3692 /* Disable CL36 PCS Tx */
3693 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3694 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3695
3696 /* Double Wide Single Data Rate @ pll rate */
3697 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3698 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3699
3700 /* Leave cl72 training enable, needed for KR */
3701 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3702 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3703 0x2);
3704
3705 /* Leave CL72 enabled */
3706 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3707 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3708 &val);
3709 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3710 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3711 val | 0x3800);
3712
3713 /* Set speed via PMA/PMD register */
3714 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3715 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3716
3717 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3718 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3719
3720 /*Enable encoded forced speed */
3721 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3722 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3723
3724 /* Turn TX scramble payload only the 64/66 scrambler */
3725 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3726 MDIO_WC_REG_TX66_CONTROL, 0x9);
3727
3728 /* Turn RX scramble payload only the 64/66 scrambler */
3729 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3730 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3731
3732 /* set and clear loopback to cause a reset to 64/66 decoder */
3733 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3734 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3735 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3736 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3737
3738 }
3739
3740 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3741 struct link_params *params,
3742 u8 is_xfi)
3743 {
3744 struct bnx2x *bp = params->bp;
3745 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3746 /* Hold rxSeqStart */
3747 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3748 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3749 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3750 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3751
3752 /* Hold tx_fifo_reset */
3753 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3754 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3755 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3756 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3757
3758 /* Disable CL73 AN */
3759 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3760
3761 /* Disable 100FX Enable and Auto-Detect */
3762 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3763 MDIO_WC_REG_FX100_CTRL1, &val);
3764 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3765 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3766
3767 /* Disable 100FX Idle detect */
3768 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3769 MDIO_WC_REG_FX100_CTRL3, &val);
3770 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3772
3773 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3774 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3775 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3776 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3777 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3778
3779 /* Turn off auto-detect & fiber mode */
3780 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3781 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3782 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3783 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3784 (val & 0xFFEE));
3785
3786 /* Set filter_force_link, disable_false_link and parallel_detect */
3787 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3788 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3789 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3790 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3791 ((val | 0x0006) & 0xFFFE));
3792
3793 /* Set XFI / SFI */
3794 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3795 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3796
3797 misc1_val &= ~(0x1f);
3798
3799 if (is_xfi) {
3800 misc1_val |= 0x5;
3801 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3802 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3803 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3804 tx_driver_val =
3805 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3806 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3807 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3808
3809 } else {
3810 misc1_val |= 0x9;
3811 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3812 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3813 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3814 tx_driver_val =
3815 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3816 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3817 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3818 }
3819 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3821
3822 /* Set Transmit PMD settings */
3823 lane = bnx2x_get_warpcore_lane(phy, params);
3824 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3825 MDIO_WC_REG_TX_FIR_TAP,
3826 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3827 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3829 tx_driver_val);
3830
3831 /* Enable fiber mode, enable and invert sig_det */
3832 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3833 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3834 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3835 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3836
3837 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3838 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3839 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3840 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3841 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3842
3843 /* 10G XFI Full Duplex */
3844 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3845 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3846
3847 /* Release tx_fifo_reset */
3848 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3849 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3850 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3852
3853 /* Release rxSeqStart */
3854 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3855 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3856 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3857 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3858 }
3859
3860 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3861 struct bnx2x_phy *phy)
3862 {
3863 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3864 }
3865
3866 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3867 struct bnx2x_phy *phy,
3868 u16 lane)
3869 {
3870 /* Rx0 anaRxControl1G */
3871 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3872 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3873
3874 /* Rx2 anaRxControl1G */
3875 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3877
3878 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879 MDIO_WC_REG_RX66_SCW0, 0xE070);
3880
3881 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3882 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3883
3884 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3885 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3886
3887 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888 MDIO_WC_REG_RX66_SCW3, 0x8090);
3889
3890 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3891 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3892
3893 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3895
3896 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3897 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3898
3899 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3901
3902 /* Serdes Digital Misc1 */
3903 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3905
3906 /* Serdes Digital4 Misc3 */
3907 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3908 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3909
3910 /* Set Transmit PMD settings */
3911 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3912 MDIO_WC_REG_TX_FIR_TAP,
3913 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3914 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3915 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3916 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3917 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3918 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3919 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3920 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3921 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3922 }
3923
3924 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3925 struct link_params *params,
3926 u8 fiber_mode)
3927 {
3928 struct bnx2x *bp = params->bp;
3929 u16 val16, digctrl_kx1, digctrl_kx2;
3930 u8 lane;
3931
3932 lane = bnx2x_get_warpcore_lane(phy, params);
3933
3934 /* Clear XFI clock comp in non-10G single lane mode. */
3935 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3936 MDIO_WC_REG_RX66_CONTROL, &val16);
3937 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3939
3940 if (phy->req_line_speed == SPEED_AUTO_NEG) {
3941 /* SGMII Autoneg */
3942 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3943 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3944 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3945 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3946 val16 | 0x1000);
3947 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3948 } else {
3949 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3950 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3951 val16 &= 0xcfbf;
3952 switch (phy->req_line_speed) {
3953 case SPEED_10:
3954 break;
3955 case SPEED_100:
3956 val16 |= 0x2000;
3957 break;
3958 case SPEED_1000:
3959 val16 |= 0x0040;
3960 break;
3961 default:
3962 DP(NETIF_MSG_LINK,
3963 "Speed not supported: 0x%x\n", phy->req_line_speed);
3964 return;
3965 }
3966
3967 if (phy->req_duplex == DUPLEX_FULL)
3968 val16 |= 0x0100;
3969
3970 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3971 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3972
3973 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3974 phy->req_line_speed);
3975 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3976 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3977 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
3978 }
3979
3980 /* SGMII Slave mode and disable signal detect */
3981 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3982 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3983 if (fiber_mode)
3984 digctrl_kx1 = 1;
3985 else
3986 digctrl_kx1 &= 0xff4a;
3987
3988 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3990 digctrl_kx1);
3991
3992 /* Turn off parallel detect */
3993 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3995 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3996 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3997 (digctrl_kx2 & ~(1<<2)));
3998
3999 /* Re-enable parallel detect */
4000 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4001 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4002 (digctrl_kx2 | (1<<2)));
4003
4004 /* Enable autodet */
4005 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4006 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4007 (digctrl_kx1 | 0x10));
4008 }
4009
4010 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4011 struct bnx2x_phy *phy,
4012 u8 reset)
4013 {
4014 u16 val;
4015 /* Take lane out of reset after configuration is finished */
4016 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4017 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4018 if (reset)
4019 val |= 0xC000;
4020 else
4021 val &= 0x3FFF;
4022 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023 MDIO_WC_REG_DIGITAL5_MISC6, val);
4024 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4025 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4026 }
4027
4028
4029 /* Clear SFI/XFI link settings registers */
4030 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4031 struct link_params *params,
4032 u16 lane)
4033 {
4034 struct bnx2x *bp = params->bp;
4035 u16 val16;
4036
4037 /* Set XFI clock comp as default. */
4038 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4039 MDIO_WC_REG_RX66_CONTROL, &val16);
4040 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4042
4043 bnx2x_warpcore_reset_lane(bp, phy, 1);
4044 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4045 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046 MDIO_WC_REG_FX100_CTRL1, 0x014a);
4047 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048 MDIO_WC_REG_FX100_CTRL3, 0x0800);
4049 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4050 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4051 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4052 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4053 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4054 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4055 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4056 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4057 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4058 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4059 lane = bnx2x_get_warpcore_lane(phy, params);
4060 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4061 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4062 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4063 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4064 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4066 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4067 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4068 bnx2x_warpcore_reset_lane(bp, phy, 0);
4069 }
4070
4071 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4072 u32 chip_id,
4073 u32 shmem_base, u8 port,
4074 u8 *gpio_num, u8 *gpio_port)
4075 {
4076 u32 cfg_pin;
4077 *gpio_num = 0;
4078 *gpio_port = 0;
4079 if (CHIP_IS_E3(bp)) {
4080 cfg_pin = (REG_RD(bp, shmem_base +
4081 offsetof(struct shmem_region,
4082 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4083 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4084 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4085
4086 /*
4087 * Should not happen. This function called upon interrupt
4088 * triggered by GPIO ( since EPIO can only generate interrupts
4089 * to MCP).
4090 * So if this function was called and none of the GPIOs was set,
4091 * it means the shit hit the fan.
4092 */
4093 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4094 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4095 DP(NETIF_MSG_LINK,
4096 "ERROR: Invalid cfg pin %x for module detect indication\n",
4097 cfg_pin);
4098 return -EINVAL;
4099 }
4100
4101 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4102 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4103 } else {
4104 *gpio_num = MISC_REGISTERS_GPIO_3;
4105 *gpio_port = port;
4106 }
4107 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4108 return 0;
4109 }
4110
4111 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4112 struct link_params *params)
4113 {
4114 struct bnx2x *bp = params->bp;
4115 u8 gpio_num, gpio_port;
4116 u32 gpio_val;
4117 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4118 params->shmem_base, params->port,
4119 &gpio_num, &gpio_port) != 0)
4120 return 0;
4121 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4122
4123 /* Call the handling function in case module is detected */
4124 if (gpio_val == 0)
4125 return 1;
4126 else
4127 return 0;
4128 }
4129
4130 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4131 struct link_params *params,
4132 struct link_vars *vars)
4133 {
4134 struct bnx2x *bp = params->bp;
4135 u32 serdes_net_if;
4136 u8 fiber_mode;
4137 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4138 serdes_net_if = (REG_RD(bp, params->shmem_base +
4139 offsetof(struct shmem_region, dev_info.
4140 port_hw_config[params->port].default_cfg)) &
4141 PORT_HW_CFG_NET_SERDES_IF_MASK);
4142 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4143 "serdes_net_if = 0x%x\n",
4144 vars->line_speed, serdes_net_if);
4145 bnx2x_set_aer_mmd(params, phy);
4146
4147 vars->phy_flags |= PHY_XGXS_FLAG;
4148 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4149 (phy->req_line_speed &&
4150 ((phy->req_line_speed == SPEED_100) ||
4151 (phy->req_line_speed == SPEED_10)))) {
4152 vars->phy_flags |= PHY_SGMII_FLAG;
4153 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4154 bnx2x_warpcore_clear_regs(phy, params, lane);
4155 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4156 } else {
4157 switch (serdes_net_if) {
4158 case PORT_HW_CFG_NET_SERDES_IF_KR:
4159 /* Enable KR Auto Neg */
4160 if (params->loopback_mode == LOOPBACK_NONE)
4161 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4162 else {
4163 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4164 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4165 }
4166 break;
4167
4168 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4169 bnx2x_warpcore_clear_regs(phy, params, lane);
4170 if (vars->line_speed == SPEED_10000) {
4171 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4172 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4173 } else {
4174 if (SINGLE_MEDIA_DIRECT(params)) {
4175 DP(NETIF_MSG_LINK, "1G Fiber\n");
4176 fiber_mode = 1;
4177 } else {
4178 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4179 fiber_mode = 0;
4180 }
4181 bnx2x_warpcore_set_sgmii_speed(phy,
4182 params,
4183 fiber_mode);
4184 }
4185
4186 break;
4187
4188 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4189
4190 bnx2x_warpcore_clear_regs(phy, params, lane);
4191 if (vars->line_speed == SPEED_10000) {
4192 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4193 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4194 } else if (vars->line_speed == SPEED_1000) {
4195 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4196 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4197 }
4198 /* Issue Module detection */
4199 if (bnx2x_is_sfp_module_plugged(phy, params))
4200 bnx2x_sfp_module_detection(phy, params);
4201 break;
4202
4203 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4204 if (vars->line_speed != SPEED_20000) {
4205 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4206 return;
4207 }
4208 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4209 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4210 /* Issue Module detection */
4211
4212 bnx2x_sfp_module_detection(phy, params);
4213 break;
4214
4215 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4216 if (vars->line_speed != SPEED_20000) {
4217 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4218 return;
4219 }
4220 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4221 bnx2x_warpcore_set_20G_KR2(bp, phy);
4222 break;
4223
4224 default:
4225 DP(NETIF_MSG_LINK,
4226 "Unsupported Serdes Net Interface 0x%x\n",
4227 serdes_net_if);
4228 return;
4229 }
4230 }
4231
4232 /* Take lane out of reset after configuration is finished */
4233 bnx2x_warpcore_reset_lane(bp, phy, 0);
4234 DP(NETIF_MSG_LINK, "Exit config init\n");
4235 }
4236
4237 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4238 struct bnx2x_phy *phy,
4239 u8 tx_en)
4240 {
4241 struct bnx2x *bp = params->bp;
4242 u32 cfg_pin;
4243 u8 port = params->port;
4244
4245 cfg_pin = REG_RD(bp, params->shmem_base +
4246 offsetof(struct shmem_region,
4247 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4248 PORT_HW_CFG_TX_LASER_MASK;
4249 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4250 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4251 /* For 20G, the expected pin to be used is 3 pins after the current */
4252
4253 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4254 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4255 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4256 }
4257
4258 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4259 struct link_params *params)
4260 {
4261 struct bnx2x *bp = params->bp;
4262 u16 val16;
4263 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4264 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4265 bnx2x_set_aer_mmd(params, phy);
4266 /* Global register */
4267 bnx2x_warpcore_reset_lane(bp, phy, 1);
4268
4269 /* Clear loopback settings (if any) */
4270 /* 10G & 20G */
4271 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4272 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4273 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4274 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4275 0xBFFF);
4276
4277 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4278 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4279 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4280 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4281
4282 /* Update those 1-copy registers */
4283 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4284 MDIO_AER_BLOCK_AER_REG, 0);
4285 /* Enable 1G MDIO (1-copy) */
4286 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4287 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4288 &val16);
4289 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4290 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4291 val16 & ~0x10);
4292
4293 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4294 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4295 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4296 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4297 val16 & 0xff00);
4298
4299 }
4300
4301 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4302 struct link_params *params)
4303 {
4304 struct bnx2x *bp = params->bp;
4305 u16 val16;
4306 u32 lane;
4307 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4308 params->loopback_mode, phy->req_line_speed);
4309
4310 if (phy->req_line_speed < SPEED_10000) {
4311 /* 10/100/1000 */
4312
4313 /* Update those 1-copy registers */
4314 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4315 MDIO_AER_BLOCK_AER_REG, 0);
4316 /* Enable 1G MDIO (1-copy) */
4317 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4318 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4319 &val16);
4320 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4321 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4322 val16 | 0x10);
4323 /* Set 1G loopback based on lane (1-copy) */
4324 lane = bnx2x_get_warpcore_lane(phy, params);
4325 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4326 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4327 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4328 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4329 val16 | (1<<lane));
4330
4331 /* Switch back to 4-copy registers */
4332 bnx2x_set_aer_mmd(params, phy);
4333 /* Global loopback, not recommended. */
4334 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4335 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4336 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4337 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4338 0x4000);
4339 } else {
4340 /* 10G & 20G */
4341 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4342 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4343 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4344 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4345 0x4000);
4346
4347 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4348 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4349 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4350 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4351 }
4352 }
4353
4354
4355 void bnx2x_link_status_update(struct link_params *params,
4356 struct link_vars *vars)
4357 {
4358 struct bnx2x *bp = params->bp;
4359 u8 link_10g_plus;
4360 u8 port = params->port;
4361 u32 sync_offset, media_types;
4362 /* Update PHY configuration */
4363 set_phy_vars(params, vars);
4364
4365 vars->link_status = REG_RD(bp, params->shmem_base +
4366 offsetof(struct shmem_region,
4367 port_mb[port].link_status));
4368
4369 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4370 vars->phy_flags = PHY_XGXS_FLAG;
4371 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4372 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4373
4374 if (vars->link_up) {
4375 DP(NETIF_MSG_LINK, "phy link up\n");
4376
4377 vars->phy_link_up = 1;
4378 vars->duplex = DUPLEX_FULL;
4379 switch (vars->link_status &
4380 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4381 case LINK_10THD:
4382 vars->duplex = DUPLEX_HALF;
4383 /* fall thru */
4384 case LINK_10TFD:
4385 vars->line_speed = SPEED_10;
4386 break;
4387
4388 case LINK_100TXHD:
4389 vars->duplex = DUPLEX_HALF;
4390 /* fall thru */
4391 case LINK_100T4:
4392 case LINK_100TXFD:
4393 vars->line_speed = SPEED_100;
4394 break;
4395
4396 case LINK_1000THD:
4397 vars->duplex = DUPLEX_HALF;
4398 /* fall thru */
4399 case LINK_1000TFD:
4400 vars->line_speed = SPEED_1000;
4401 break;
4402
4403 case LINK_2500THD:
4404 vars->duplex = DUPLEX_HALF;
4405 /* fall thru */
4406 case LINK_2500TFD:
4407 vars->line_speed = SPEED_2500;
4408 break;
4409
4410 case LINK_10GTFD:
4411 vars->line_speed = SPEED_10000;
4412 break;
4413 case LINK_20GTFD:
4414 vars->line_speed = SPEED_20000;
4415 break;
4416 default:
4417 break;
4418 }
4419 vars->flow_ctrl = 0;
4420 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4421 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4422
4423 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4424 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4425
4426 if (!vars->flow_ctrl)
4427 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4428
4429 if (vars->line_speed &&
4430 ((vars->line_speed == SPEED_10) ||
4431 (vars->line_speed == SPEED_100))) {
4432 vars->phy_flags |= PHY_SGMII_FLAG;
4433 } else {
4434 vars->phy_flags &= ~PHY_SGMII_FLAG;
4435 }
4436 if (vars->line_speed &&
4437 USES_WARPCORE(bp) &&
4438 (vars->line_speed == SPEED_1000))
4439 vars->phy_flags |= PHY_SGMII_FLAG;
4440 /* anything 10 and over uses the bmac */
4441 link_10g_plus = (vars->line_speed >= SPEED_10000);
4442
4443 if (link_10g_plus) {
4444 if (USES_WARPCORE(bp))
4445 vars->mac_type = MAC_TYPE_XMAC;
4446 else
4447 vars->mac_type = MAC_TYPE_BMAC;
4448 } else {
4449 if (USES_WARPCORE(bp))
4450 vars->mac_type = MAC_TYPE_UMAC;
4451 else
4452 vars->mac_type = MAC_TYPE_EMAC;
4453 }
4454 } else { /* link down */
4455 DP(NETIF_MSG_LINK, "phy link down\n");
4456
4457 vars->phy_link_up = 0;
4458
4459 vars->line_speed = 0;
4460 vars->duplex = DUPLEX_FULL;
4461 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4462
4463 /* indicate no mac active */
4464 vars->mac_type = MAC_TYPE_NONE;
4465 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4466 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4467 }
4468
4469 /* Sync media type */
4470 sync_offset = params->shmem_base +
4471 offsetof(struct shmem_region,
4472 dev_info.port_hw_config[port].media_type);
4473 media_types = REG_RD(bp, sync_offset);
4474
4475 params->phy[INT_PHY].media_type =
4476 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4477 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4478 params->phy[EXT_PHY1].media_type =
4479 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4480 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4481 params->phy[EXT_PHY2].media_type =
4482 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4483 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4484 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4485
4486 /* Sync AEU offset */
4487 sync_offset = params->shmem_base +
4488 offsetof(struct shmem_region,
4489 dev_info.port_hw_config[port].aeu_int_mask);
4490
4491 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4492
4493 /* Sync PFC status */
4494 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4495 params->feature_config_flags |=
4496 FEATURE_CONFIG_PFC_ENABLED;
4497 else
4498 params->feature_config_flags &=
4499 ~FEATURE_CONFIG_PFC_ENABLED;
4500
4501 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4502 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4503 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4504 vars->line_speed, vars->duplex, vars->flow_ctrl);
4505 }
4506
4507
4508 static void bnx2x_set_master_ln(struct link_params *params,
4509 struct bnx2x_phy *phy)
4510 {
4511 struct bnx2x *bp = params->bp;
4512 u16 new_master_ln, ser_lane;
4513 ser_lane = ((params->lane_config &
4514 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4515 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4516
4517 /* set the master_ln for AN */
4518 CL22_RD_OVER_CL45(bp, phy,
4519 MDIO_REG_BANK_XGXS_BLOCK2,
4520 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4521 &new_master_ln);
4522
4523 CL22_WR_OVER_CL45(bp, phy,
4524 MDIO_REG_BANK_XGXS_BLOCK2 ,
4525 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4526 (new_master_ln | ser_lane));
4527 }
4528
4529 static int bnx2x_reset_unicore(struct link_params *params,
4530 struct bnx2x_phy *phy,
4531 u8 set_serdes)
4532 {
4533 struct bnx2x *bp = params->bp;
4534 u16 mii_control;
4535 u16 i;
4536 CL22_RD_OVER_CL45(bp, phy,
4537 MDIO_REG_BANK_COMBO_IEEE0,
4538 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4539
4540 /* reset the unicore */
4541 CL22_WR_OVER_CL45(bp, phy,
4542 MDIO_REG_BANK_COMBO_IEEE0,
4543 MDIO_COMBO_IEEE0_MII_CONTROL,
4544 (mii_control |
4545 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4546 if (set_serdes)
4547 bnx2x_set_serdes_access(bp, params->port);
4548
4549 /* wait for the reset to self clear */
4550 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4551 udelay(5);
4552
4553 /* the reset erased the previous bank value */
4554 CL22_RD_OVER_CL45(bp, phy,
4555 MDIO_REG_BANK_COMBO_IEEE0,
4556 MDIO_COMBO_IEEE0_MII_CONTROL,
4557 &mii_control);
4558
4559 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4560 udelay(5);
4561 return 0;
4562 }
4563 }
4564
4565 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4566 " Port %d\n",
4567 params->port);
4568 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4569 return -EINVAL;
4570
4571 }
4572
4573 static void bnx2x_set_swap_lanes(struct link_params *params,
4574 struct bnx2x_phy *phy)
4575 {
4576 struct bnx2x *bp = params->bp;
4577 /*
4578 * Each two bits represents a lane number:
4579 * No swap is 0123 => 0x1b no need to enable the swap
4580 */
4581 u16 ser_lane, rx_lane_swap, tx_lane_swap;
4582
4583 ser_lane = ((params->lane_config &
4584 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4585 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4586 rx_lane_swap = ((params->lane_config &
4587 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4588 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4589 tx_lane_swap = ((params->lane_config &
4590 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4591 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4592
4593 if (rx_lane_swap != 0x1b) {
4594 CL22_WR_OVER_CL45(bp, phy,
4595 MDIO_REG_BANK_XGXS_BLOCK2,
4596 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4597 (rx_lane_swap |
4598 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4599 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4600 } else {
4601 CL22_WR_OVER_CL45(bp, phy,
4602 MDIO_REG_BANK_XGXS_BLOCK2,
4603 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4604 }
4605
4606 if (tx_lane_swap != 0x1b) {
4607 CL22_WR_OVER_CL45(bp, phy,
4608 MDIO_REG_BANK_XGXS_BLOCK2,
4609 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4610 (tx_lane_swap |
4611 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4612 } else {
4613 CL22_WR_OVER_CL45(bp, phy,
4614 MDIO_REG_BANK_XGXS_BLOCK2,
4615 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4616 }
4617 }
4618
4619 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4620 struct link_params *params)
4621 {
4622 struct bnx2x *bp = params->bp;
4623 u16 control2;
4624 CL22_RD_OVER_CL45(bp, phy,
4625 MDIO_REG_BANK_SERDES_DIGITAL,
4626 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4627 &control2);
4628 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4629 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4630 else
4631 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4632 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4633 phy->speed_cap_mask, control2);
4634 CL22_WR_OVER_CL45(bp, phy,
4635 MDIO_REG_BANK_SERDES_DIGITAL,
4636 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4637 control2);
4638
4639 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4640 (phy->speed_cap_mask &
4641 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4642 DP(NETIF_MSG_LINK, "XGXS\n");
4643
4644 CL22_WR_OVER_CL45(bp, phy,
4645 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4646 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4647 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4648
4649 CL22_RD_OVER_CL45(bp, phy,
4650 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4651 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4652 &control2);
4653
4654
4655 control2 |=
4656 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4657
4658 CL22_WR_OVER_CL45(bp, phy,
4659 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4660 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4661 control2);
4662
4663 /* Disable parallel detection of HiG */
4664 CL22_WR_OVER_CL45(bp, phy,
4665 MDIO_REG_BANK_XGXS_BLOCK2,
4666 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4667 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4668 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4669 }
4670 }
4671
4672 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4673 struct link_params *params,
4674 struct link_vars *vars,
4675 u8 enable_cl73)
4676 {
4677 struct bnx2x *bp = params->bp;
4678 u16 reg_val;
4679
4680 /* CL37 Autoneg */
4681 CL22_RD_OVER_CL45(bp, phy,
4682 MDIO_REG_BANK_COMBO_IEEE0,
4683 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4684
4685 /* CL37 Autoneg Enabled */
4686 if (vars->line_speed == SPEED_AUTO_NEG)
4687 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4688 else /* CL37 Autoneg Disabled */
4689 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4690 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4691
4692 CL22_WR_OVER_CL45(bp, phy,
4693 MDIO_REG_BANK_COMBO_IEEE0,
4694 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4695
4696 /* Enable/Disable Autodetection */
4697
4698 CL22_RD_OVER_CL45(bp, phy,
4699 MDIO_REG_BANK_SERDES_DIGITAL,
4700 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4701 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4702 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4703 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4704 if (vars->line_speed == SPEED_AUTO_NEG)
4705 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4706 else
4707 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4708
4709 CL22_WR_OVER_CL45(bp, phy,
4710 MDIO_REG_BANK_SERDES_DIGITAL,
4711 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4712
4713 /* Enable TetonII and BAM autoneg */
4714 CL22_RD_OVER_CL45(bp, phy,
4715 MDIO_REG_BANK_BAM_NEXT_PAGE,
4716 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4717 &reg_val);
4718 if (vars->line_speed == SPEED_AUTO_NEG) {
4719 /* Enable BAM aneg Mode and TetonII aneg Mode */
4720 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4721 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4722 } else {
4723 /* TetonII and BAM Autoneg Disabled */
4724 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4725 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4726 }
4727 CL22_WR_OVER_CL45(bp, phy,
4728 MDIO_REG_BANK_BAM_NEXT_PAGE,
4729 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4730 reg_val);
4731
4732 if (enable_cl73) {
4733 /* Enable Cl73 FSM status bits */
4734 CL22_WR_OVER_CL45(bp, phy,
4735 MDIO_REG_BANK_CL73_USERB0,
4736 MDIO_CL73_USERB0_CL73_UCTRL,
4737 0xe);
4738
4739 /* Enable BAM Station Manager*/
4740 CL22_WR_OVER_CL45(bp, phy,
4741 MDIO_REG_BANK_CL73_USERB0,
4742 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4743 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4744 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4745 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4746
4747 /* Advertise CL73 link speeds */
4748 CL22_RD_OVER_CL45(bp, phy,
4749 MDIO_REG_BANK_CL73_IEEEB1,
4750 MDIO_CL73_IEEEB1_AN_ADV2,
4751 &reg_val);
4752 if (phy->speed_cap_mask &
4753 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4754 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4755 if (phy->speed_cap_mask &
4756 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4757 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4758
4759 CL22_WR_OVER_CL45(bp, phy,
4760 MDIO_REG_BANK_CL73_IEEEB1,
4761 MDIO_CL73_IEEEB1_AN_ADV2,
4762 reg_val);
4763
4764 /* CL73 Autoneg Enabled */
4765 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4766
4767 } else /* CL73 Autoneg Disabled */
4768 reg_val = 0;
4769
4770 CL22_WR_OVER_CL45(bp, phy,
4771 MDIO_REG_BANK_CL73_IEEEB0,
4772 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4773 }
4774
4775 /* program SerDes, forced speed */
4776 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4777 struct link_params *params,
4778 struct link_vars *vars)
4779 {
4780 struct bnx2x *bp = params->bp;
4781 u16 reg_val;
4782
4783 /* program duplex, disable autoneg and sgmii*/
4784 CL22_RD_OVER_CL45(bp, phy,
4785 MDIO_REG_BANK_COMBO_IEEE0,
4786 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4787 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4788 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4789 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4790 if (phy->req_duplex == DUPLEX_FULL)
4791 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4792 CL22_WR_OVER_CL45(bp, phy,
4793 MDIO_REG_BANK_COMBO_IEEE0,
4794 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4795
4796 /*
4797 * program speed
4798 * - needed only if the speed is greater than 1G (2.5G or 10G)
4799 */
4800 CL22_RD_OVER_CL45(bp, phy,
4801 MDIO_REG_BANK_SERDES_DIGITAL,
4802 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4803 /* clearing the speed value before setting the right speed */
4804 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4805
4806 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4807 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4808
4809 if (!((vars->line_speed == SPEED_1000) ||
4810 (vars->line_speed == SPEED_100) ||
4811 (vars->line_speed == SPEED_10))) {
4812
4813 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4814 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4815 if (vars->line_speed == SPEED_10000)
4816 reg_val |=
4817 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4818 }
4819
4820 CL22_WR_OVER_CL45(bp, phy,
4821 MDIO_REG_BANK_SERDES_DIGITAL,
4822 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4823
4824 }
4825
4826 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4827 struct link_params *params)
4828 {
4829 struct bnx2x *bp = params->bp;
4830 u16 val = 0;
4831
4832 /* configure the 48 bits for BAM AN */
4833
4834 /* set extended capabilities */
4835 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4836 val |= MDIO_OVER_1G_UP1_2_5G;
4837 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4838 val |= MDIO_OVER_1G_UP1_10G;
4839 CL22_WR_OVER_CL45(bp, phy,
4840 MDIO_REG_BANK_OVER_1G,
4841 MDIO_OVER_1G_UP1, val);
4842
4843 CL22_WR_OVER_CL45(bp, phy,
4844 MDIO_REG_BANK_OVER_1G,
4845 MDIO_OVER_1G_UP3, 0x400);
4846 }
4847
4848 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4849 struct link_params *params,
4850 u16 ieee_fc)
4851 {
4852 struct bnx2x *bp = params->bp;
4853 u16 val;
4854 /* for AN, we are always publishing full duplex */
4855
4856 CL22_WR_OVER_CL45(bp, phy,
4857 MDIO_REG_BANK_COMBO_IEEE0,
4858 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4859 CL22_RD_OVER_CL45(bp, phy,
4860 MDIO_REG_BANK_CL73_IEEEB1,
4861 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4862 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4863 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4864 CL22_WR_OVER_CL45(bp, phy,
4865 MDIO_REG_BANK_CL73_IEEEB1,
4866 MDIO_CL73_IEEEB1_AN_ADV1, val);
4867 }
4868
4869 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4870 struct link_params *params,
4871 u8 enable_cl73)
4872 {
4873 struct bnx2x *bp = params->bp;
4874 u16 mii_control;
4875
4876 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4877 /* Enable and restart BAM/CL37 aneg */
4878
4879 if (enable_cl73) {
4880 CL22_RD_OVER_CL45(bp, phy,
4881 MDIO_REG_BANK_CL73_IEEEB0,
4882 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4883 &mii_control);
4884
4885 CL22_WR_OVER_CL45(bp, phy,
4886 MDIO_REG_BANK_CL73_IEEEB0,
4887 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4888 (mii_control |
4889 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4890 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4891 } else {
4892
4893 CL22_RD_OVER_CL45(bp, phy,
4894 MDIO_REG_BANK_COMBO_IEEE0,
4895 MDIO_COMBO_IEEE0_MII_CONTROL,
4896 &mii_control);
4897 DP(NETIF_MSG_LINK,
4898 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4899 mii_control);
4900 CL22_WR_OVER_CL45(bp, phy,
4901 MDIO_REG_BANK_COMBO_IEEE0,
4902 MDIO_COMBO_IEEE0_MII_CONTROL,
4903 (mii_control |
4904 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4905 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4906 }
4907 }
4908
4909 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4910 struct link_params *params,
4911 struct link_vars *vars)
4912 {
4913 struct bnx2x *bp = params->bp;
4914 u16 control1;
4915
4916 /* in SGMII mode, the unicore is always slave */
4917
4918 CL22_RD_OVER_CL45(bp, phy,
4919 MDIO_REG_BANK_SERDES_DIGITAL,
4920 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4921 &control1);
4922 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4923 /* set sgmii mode (and not fiber) */
4924 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4925 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4926 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4927 CL22_WR_OVER_CL45(bp, phy,
4928 MDIO_REG_BANK_SERDES_DIGITAL,
4929 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4930 control1);
4931
4932 /* if forced speed */
4933 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4934 /* set speed, disable autoneg */
4935 u16 mii_control;
4936
4937 CL22_RD_OVER_CL45(bp, phy,
4938 MDIO_REG_BANK_COMBO_IEEE0,
4939 MDIO_COMBO_IEEE0_MII_CONTROL,
4940 &mii_control);
4941 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4942 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4943 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4944
4945 switch (vars->line_speed) {
4946 case SPEED_100:
4947 mii_control |=
4948 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4949 break;
4950 case SPEED_1000:
4951 mii_control |=
4952 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4953 break;
4954 case SPEED_10:
4955 /* there is nothing to set for 10M */
4956 break;
4957 default:
4958 /* invalid speed for SGMII */
4959 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4960 vars->line_speed);
4961 break;
4962 }
4963
4964 /* setting the full duplex */
4965 if (phy->req_duplex == DUPLEX_FULL)
4966 mii_control |=
4967 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4968 CL22_WR_OVER_CL45(bp, phy,
4969 MDIO_REG_BANK_COMBO_IEEE0,
4970 MDIO_COMBO_IEEE0_MII_CONTROL,
4971 mii_control);
4972
4973 } else { /* AN mode */
4974 /* enable and restart AN */
4975 bnx2x_restart_autoneg(phy, params, 0);
4976 }
4977 }
4978
4979
4980 /*
4981 * link management
4982 */
4983
4984 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4985 struct link_params *params)
4986 {
4987 struct bnx2x *bp = params->bp;
4988 u16 pd_10g, status2_1000x;
4989 if (phy->req_line_speed != SPEED_AUTO_NEG)
4990 return 0;
4991 CL22_RD_OVER_CL45(bp, phy,
4992 MDIO_REG_BANK_SERDES_DIGITAL,
4993 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4994 &status2_1000x);
4995 CL22_RD_OVER_CL45(bp, phy,
4996 MDIO_REG_BANK_SERDES_DIGITAL,
4997 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4998 &status2_1000x);
4999 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5000 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5001 params->port);
5002 return 1;
5003 }
5004
5005 CL22_RD_OVER_CL45(bp, phy,
5006 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5007 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5008 &pd_10g);
5009
5010 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5011 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5012 params->port);
5013 return 1;
5014 }
5015 return 0;
5016 }
5017
5018 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5019 struct link_params *params,
5020 struct link_vars *vars,
5021 u32 gp_status)
5022 {
5023 struct bnx2x *bp = params->bp;
5024 u16 ld_pause; /* local driver */
5025 u16 lp_pause; /* link partner */
5026 u16 pause_result;
5027
5028 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5029
5030 /* resolve from gp_status in case of AN complete and not sgmii */
5031 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5032 vars->flow_ctrl = phy->req_flow_ctrl;
5033 else if (phy->req_line_speed != SPEED_AUTO_NEG)
5034 vars->flow_ctrl = params->req_fc_auto_adv;
5035 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5036 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5037 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5038 vars->flow_ctrl = params->req_fc_auto_adv;
5039 return;
5040 }
5041 if ((gp_status &
5042 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5043 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5044 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5045 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5046
5047 CL22_RD_OVER_CL45(bp, phy,
5048 MDIO_REG_BANK_CL73_IEEEB1,
5049 MDIO_CL73_IEEEB1_AN_ADV1,
5050 &ld_pause);
5051 CL22_RD_OVER_CL45(bp, phy,
5052 MDIO_REG_BANK_CL73_IEEEB1,
5053 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5054 &lp_pause);
5055 pause_result = (ld_pause &
5056 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5057 >> 8;
5058 pause_result |= (lp_pause &
5059 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5060 >> 10;
5061 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5062 pause_result);
5063 } else {
5064 CL22_RD_OVER_CL45(bp, phy,
5065 MDIO_REG_BANK_COMBO_IEEE0,
5066 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5067 &ld_pause);
5068 CL22_RD_OVER_CL45(bp, phy,
5069 MDIO_REG_BANK_COMBO_IEEE0,
5070 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5071 &lp_pause);
5072 pause_result = (ld_pause &
5073 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5074 pause_result |= (lp_pause &
5075 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5076 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5077 pause_result);
5078 }
5079 bnx2x_pause_resolve(vars, pause_result);
5080 }
5081 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5082 }
5083
5084 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5085 struct link_params *params)
5086 {
5087 struct bnx2x *bp = params->bp;
5088 u16 rx_status, ustat_val, cl37_fsm_received;
5089 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5090 /* Step 1: Make sure signal is detected */
5091 CL22_RD_OVER_CL45(bp, phy,
5092 MDIO_REG_BANK_RX0,
5093 MDIO_RX0_RX_STATUS,
5094 &rx_status);
5095 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5096 (MDIO_RX0_RX_STATUS_SIGDET)) {
5097 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5098 "rx_status(0x80b0) = 0x%x\n", rx_status);
5099 CL22_WR_OVER_CL45(bp, phy,
5100 MDIO_REG_BANK_CL73_IEEEB0,
5101 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5102 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5103 return;
5104 }
5105 /* Step 2: Check CL73 state machine */
5106 CL22_RD_OVER_CL45(bp, phy,
5107 MDIO_REG_BANK_CL73_USERB0,
5108 MDIO_CL73_USERB0_CL73_USTAT1,
5109 &ustat_val);
5110 if ((ustat_val &
5111 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5112 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5113 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5114 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5115 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5116 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5117 return;
5118 }
5119 /*
5120 * Step 3: Check CL37 Message Pages received to indicate LP
5121 * supports only CL37
5122 */
5123 CL22_RD_OVER_CL45(bp, phy,
5124 MDIO_REG_BANK_REMOTE_PHY,
5125 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5126 &cl37_fsm_received);
5127 if ((cl37_fsm_received &
5128 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5129 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5130 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5131 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5132 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5133 "misc_rx_status(0x8330) = 0x%x\n",
5134 cl37_fsm_received);
5135 return;
5136 }
5137 /*
5138 * The combined cl37/cl73 fsm state information indicating that
5139 * we are connected to a device which does not support cl73, but
5140 * does support cl37 BAM. In this case we disable cl73 and
5141 * restart cl37 auto-neg
5142 */
5143
5144 /* Disable CL73 */
5145 CL22_WR_OVER_CL45(bp, phy,
5146 MDIO_REG_BANK_CL73_IEEEB0,
5147 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5148 0);
5149 /* Restart CL37 autoneg */
5150 bnx2x_restart_autoneg(phy, params, 0);
5151 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5152 }
5153
5154 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5155 struct link_params *params,
5156 struct link_vars *vars,
5157 u32 gp_status)
5158 {
5159 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5160 vars->link_status |=
5161 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5162
5163 if (bnx2x_direct_parallel_detect_used(phy, params))
5164 vars->link_status |=
5165 LINK_STATUS_PARALLEL_DETECTION_USED;
5166 }
5167 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5168 struct link_params *params,
5169 struct link_vars *vars,
5170 u16 is_link_up,
5171 u16 speed_mask,
5172 u16 is_duplex)
5173 {
5174 struct bnx2x *bp = params->bp;
5175 if (phy->req_line_speed == SPEED_AUTO_NEG)
5176 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5177 if (is_link_up) {
5178 DP(NETIF_MSG_LINK, "phy link up\n");
5179
5180 vars->phy_link_up = 1;
5181 vars->link_status |= LINK_STATUS_LINK_UP;
5182
5183 switch (speed_mask) {
5184 case GP_STATUS_10M:
5185 vars->line_speed = SPEED_10;
5186 if (vars->duplex == DUPLEX_FULL)
5187 vars->link_status |= LINK_10TFD;
5188 else
5189 vars->link_status |= LINK_10THD;
5190 break;
5191
5192 case GP_STATUS_100M:
5193 vars->line_speed = SPEED_100;
5194 if (vars->duplex == DUPLEX_FULL)
5195 vars->link_status |= LINK_100TXFD;
5196 else
5197 vars->link_status |= LINK_100TXHD;
5198 break;
5199
5200 case GP_STATUS_1G:
5201 case GP_STATUS_1G_KX:
5202 vars->line_speed = SPEED_1000;
5203 if (vars->duplex == DUPLEX_FULL)
5204 vars->link_status |= LINK_1000TFD;
5205 else
5206 vars->link_status |= LINK_1000THD;
5207 break;
5208
5209 case GP_STATUS_2_5G:
5210 vars->line_speed = SPEED_2500;
5211 if (vars->duplex == DUPLEX_FULL)
5212 vars->link_status |= LINK_2500TFD;
5213 else
5214 vars->link_status |= LINK_2500THD;
5215 break;
5216
5217 case GP_STATUS_5G:
5218 case GP_STATUS_6G:
5219 DP(NETIF_MSG_LINK,
5220 "link speed unsupported gp_status 0x%x\n",
5221 speed_mask);
5222 return -EINVAL;
5223
5224 case GP_STATUS_10G_KX4:
5225 case GP_STATUS_10G_HIG:
5226 case GP_STATUS_10G_CX4:
5227 case GP_STATUS_10G_KR:
5228 case GP_STATUS_10G_SFI:
5229 case GP_STATUS_10G_XFI:
5230 vars->line_speed = SPEED_10000;
5231 vars->link_status |= LINK_10GTFD;
5232 break;
5233 case GP_STATUS_20G_DXGXS:
5234 vars->line_speed = SPEED_20000;
5235 vars->link_status |= LINK_20GTFD;
5236 break;
5237 default:
5238 DP(NETIF_MSG_LINK,
5239 "link speed unsupported gp_status 0x%x\n",
5240 speed_mask);
5241 return -EINVAL;
5242 }
5243 } else { /* link_down */
5244 DP(NETIF_MSG_LINK, "phy link down\n");
5245
5246 vars->phy_link_up = 0;
5247
5248 vars->duplex = DUPLEX_FULL;
5249 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5250 vars->mac_type = MAC_TYPE_NONE;
5251 }
5252 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5253 vars->phy_link_up, vars->line_speed);
5254 return 0;
5255 }
5256
5257 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5258 struct link_params *params,
5259 struct link_vars *vars)
5260 {
5261
5262 struct bnx2x *bp = params->bp;
5263
5264 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5265 int rc = 0;
5266
5267 /* Read gp_status */
5268 CL22_RD_OVER_CL45(bp, phy,
5269 MDIO_REG_BANK_GP_STATUS,
5270 MDIO_GP_STATUS_TOP_AN_STATUS1,
5271 &gp_status);
5272 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5273 duplex = DUPLEX_FULL;
5274 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5275 link_up = 1;
5276 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5277 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5278 gp_status, link_up, speed_mask);
5279 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5280 duplex);
5281 if (rc == -EINVAL)
5282 return rc;
5283
5284 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5285 if (SINGLE_MEDIA_DIRECT(params)) {
5286 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5287 if (phy->req_line_speed == SPEED_AUTO_NEG)
5288 bnx2x_xgxs_an_resolve(phy, params, vars,
5289 gp_status);
5290 }
5291 } else { /* link_down */
5292 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5293 SINGLE_MEDIA_DIRECT(params)) {
5294 /* Check signal is detected */
5295 bnx2x_check_fallback_to_cl37(phy, params);
5296 }
5297 }
5298
5299 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5300 vars->duplex, vars->flow_ctrl, vars->link_status);
5301 return rc;
5302 }
5303
5304 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5305 struct link_params *params,
5306 struct link_vars *vars)
5307 {
5308
5309 struct bnx2x *bp = params->bp;
5310
5311 u8 lane;
5312 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5313 int rc = 0;
5314 lane = bnx2x_get_warpcore_lane(phy, params);
5315 /* Read gp_status */
5316 if (phy->req_line_speed > SPEED_10000) {
5317 u16 temp_link_up;
5318 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5319 1, &temp_link_up);
5320 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5321 1, &link_up);
5322 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5323 temp_link_up, link_up);
5324 link_up &= (1<<2);
5325 if (link_up)
5326 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5327 } else {
5328 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5329 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5330 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5331 /* Check for either KR or generic link up. */
5332 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5333 ((gp_status1 >> 12) & 0xf);
5334 link_up = gp_status1 & (1 << lane);
5335 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5336 u16 pd, gp_status4;
5337 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5338 /* Check Autoneg complete */
5339 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5340 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5341 &gp_status4);
5342 if (gp_status4 & ((1<<12)<<lane))
5343 vars->link_status |=
5344 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5345
5346 /* Check parallel detect used */
5347 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5348 MDIO_WC_REG_PAR_DET_10G_STATUS,
5349 &pd);
5350 if (pd & (1<<15))
5351 vars->link_status |=
5352 LINK_STATUS_PARALLEL_DETECTION_USED;
5353 }
5354 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5355 }
5356 }
5357
5358 if (lane < 2) {
5359 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5360 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5361 } else {
5362 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5363 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5364 }
5365 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5366
5367 if ((lane & 1) == 0)
5368 gp_speed <<= 8;
5369 gp_speed &= 0x3f00;
5370
5371
5372 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5373 duplex);
5374
5375 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5376 vars->duplex, vars->flow_ctrl, vars->link_status);
5377 return rc;
5378 }
5379 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5380 {
5381 struct bnx2x *bp = params->bp;
5382 struct bnx2x_phy *phy = &params->phy[INT_PHY];
5383 u16 lp_up2;
5384 u16 tx_driver;
5385 u16 bank;
5386
5387 /* read precomp */
5388 CL22_RD_OVER_CL45(bp, phy,
5389 MDIO_REG_BANK_OVER_1G,
5390 MDIO_OVER_1G_LP_UP2, &lp_up2);
5391
5392 /* bits [10:7] at lp_up2, positioned at [15:12] */
5393 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5394 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5395 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5396
5397 if (lp_up2 == 0)
5398 return;
5399
5400 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5401 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5402 CL22_RD_OVER_CL45(bp, phy,
5403 bank,
5404 MDIO_TX0_TX_DRIVER, &tx_driver);
5405
5406 /* replace tx_driver bits [15:12] */
5407 if (lp_up2 !=
5408 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5409 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5410 tx_driver |= lp_up2;
5411 CL22_WR_OVER_CL45(bp, phy,
5412 bank,
5413 MDIO_TX0_TX_DRIVER, tx_driver);
5414 }
5415 }
5416 }
5417
5418 static int bnx2x_emac_program(struct link_params *params,
5419 struct link_vars *vars)
5420 {
5421 struct bnx2x *bp = params->bp;
5422 u8 port = params->port;
5423 u16 mode = 0;
5424
5425 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5426 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5427 EMAC_REG_EMAC_MODE,
5428 (EMAC_MODE_25G_MODE |
5429 EMAC_MODE_PORT_MII_10M |
5430 EMAC_MODE_HALF_DUPLEX));
5431 switch (vars->line_speed) {
5432 case SPEED_10:
5433 mode |= EMAC_MODE_PORT_MII_10M;
5434 break;
5435
5436 case SPEED_100:
5437 mode |= EMAC_MODE_PORT_MII;
5438 break;
5439
5440 case SPEED_1000:
5441 mode |= EMAC_MODE_PORT_GMII;
5442 break;
5443
5444 case SPEED_2500:
5445 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5446 break;
5447
5448 default:
5449 /* 10G not valid for EMAC */
5450 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5451 vars->line_speed);
5452 return -EINVAL;
5453 }
5454
5455 if (vars->duplex == DUPLEX_HALF)
5456 mode |= EMAC_MODE_HALF_DUPLEX;
5457 bnx2x_bits_en(bp,
5458 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5459 mode);
5460
5461 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5462 return 0;
5463 }
5464
5465 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5466 struct link_params *params)
5467 {
5468
5469 u16 bank, i = 0;
5470 struct bnx2x *bp = params->bp;
5471
5472 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5473 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5474 CL22_WR_OVER_CL45(bp, phy,
5475 bank,
5476 MDIO_RX0_RX_EQ_BOOST,
5477 phy->rx_preemphasis[i]);
5478 }
5479
5480 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5481 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5482 CL22_WR_OVER_CL45(bp, phy,
5483 bank,
5484 MDIO_TX0_TX_DRIVER,
5485 phy->tx_preemphasis[i]);
5486 }
5487 }
5488
5489 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5490 struct link_params *params,
5491 struct link_vars *vars)
5492 {
5493 struct bnx2x *bp = params->bp;
5494 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5495 (params->loopback_mode == LOOPBACK_XGXS));
5496 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5497 if (SINGLE_MEDIA_DIRECT(params) &&
5498 (params->feature_config_flags &
5499 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5500 bnx2x_set_preemphasis(phy, params);
5501
5502 /* forced speed requested? */
5503 if (vars->line_speed != SPEED_AUTO_NEG ||
5504 (SINGLE_MEDIA_DIRECT(params) &&
5505 params->loopback_mode == LOOPBACK_EXT)) {
5506 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5507
5508 /* disable autoneg */
5509 bnx2x_set_autoneg(phy, params, vars, 0);
5510
5511 /* program speed and duplex */
5512 bnx2x_program_serdes(phy, params, vars);
5513
5514 } else { /* AN_mode */
5515 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5516
5517 /* AN enabled */
5518 bnx2x_set_brcm_cl37_advertisement(phy, params);
5519
5520 /* program duplex & pause advertisement (for aneg) */
5521 bnx2x_set_ieee_aneg_advertisement(phy, params,
5522 vars->ieee_fc);
5523
5524 /* enable autoneg */
5525 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5526
5527 /* enable and restart AN */
5528 bnx2x_restart_autoneg(phy, params, enable_cl73);
5529 }
5530
5531 } else { /* SGMII mode */
5532 DP(NETIF_MSG_LINK, "SGMII\n");
5533
5534 bnx2x_initialize_sgmii_process(phy, params, vars);
5535 }
5536 }
5537
5538 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5539 struct link_params *params,
5540 struct link_vars *vars)
5541 {
5542 int rc;
5543 vars->phy_flags |= PHY_XGXS_FLAG;
5544 if ((phy->req_line_speed &&
5545 ((phy->req_line_speed == SPEED_100) ||
5546 (phy->req_line_speed == SPEED_10))) ||
5547 (!phy->req_line_speed &&
5548 (phy->speed_cap_mask >=
5549 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5550 (phy->speed_cap_mask <
5551 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5552 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5553 vars->phy_flags |= PHY_SGMII_FLAG;
5554 else
5555 vars->phy_flags &= ~PHY_SGMII_FLAG;
5556
5557 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5558 bnx2x_set_aer_mmd(params, phy);
5559 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5560 bnx2x_set_master_ln(params, phy);
5561
5562 rc = bnx2x_reset_unicore(params, phy, 0);
5563 /* reset the SerDes and wait for reset bit return low */
5564 if (rc != 0)
5565 return rc;
5566
5567 bnx2x_set_aer_mmd(params, phy);
5568 /* setting the masterLn_def again after the reset */
5569 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5570 bnx2x_set_master_ln(params, phy);
5571 bnx2x_set_swap_lanes(params, phy);
5572 }
5573
5574 return rc;
5575 }
5576
5577 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5578 struct bnx2x_phy *phy,
5579 struct link_params *params)
5580 {
5581 u16 cnt, ctrl;
5582 /* Wait for soft reset to get cleared up to 1 sec */
5583 for (cnt = 0; cnt < 1000; cnt++) {
5584 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5585 bnx2x_cl22_read(bp, phy,
5586 MDIO_PMA_REG_CTRL, &ctrl);
5587 else
5588 bnx2x_cl45_read(bp, phy,
5589 MDIO_PMA_DEVAD,
5590 MDIO_PMA_REG_CTRL, &ctrl);
5591 if (!(ctrl & (1<<15)))
5592 break;
5593 msleep(1);
5594 }
5595
5596 if (cnt == 1000)
5597 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5598 " Port %d\n",
5599 params->port);
5600 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5601 return cnt;
5602 }
5603
5604 static void bnx2x_link_int_enable(struct link_params *params)
5605 {
5606 u8 port = params->port;
5607 u32 mask;
5608 struct bnx2x *bp = params->bp;
5609
5610 /* Setting the status to report on link up for either XGXS or SerDes */
5611 if (CHIP_IS_E3(bp)) {
5612 mask = NIG_MASK_XGXS0_LINK_STATUS;
5613 if (!(SINGLE_MEDIA_DIRECT(params)))
5614 mask |= NIG_MASK_MI_INT;
5615 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5616 mask = (NIG_MASK_XGXS0_LINK10G |
5617 NIG_MASK_XGXS0_LINK_STATUS);
5618 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5619 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5620 params->phy[INT_PHY].type !=
5621 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5622 mask |= NIG_MASK_MI_INT;
5623 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5624 }
5625
5626 } else { /* SerDes */
5627 mask = NIG_MASK_SERDES0_LINK_STATUS;
5628 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5629 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5630 params->phy[INT_PHY].type !=
5631 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5632 mask |= NIG_MASK_MI_INT;
5633 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5634 }
5635 }
5636 bnx2x_bits_en(bp,
5637 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5638 mask);
5639
5640 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5641 (params->switch_cfg == SWITCH_CFG_10G),
5642 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5643 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5644 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5645 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5646 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5647 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5648 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5649 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5650 }
5651
5652 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5653 u8 exp_mi_int)
5654 {
5655 u32 latch_status = 0;
5656
5657 /*
5658 * Disable the MI INT ( external phy int ) by writing 1 to the
5659 * status register. Link down indication is high-active-signal,
5660 * so in this case we need to write the status to clear the XOR
5661 */
5662 /* Read Latched signals */
5663 latch_status = REG_RD(bp,
5664 NIG_REG_LATCH_STATUS_0 + port*8);
5665 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5666 /* Handle only those with latched-signal=up.*/
5667 if (exp_mi_int)
5668 bnx2x_bits_en(bp,
5669 NIG_REG_STATUS_INTERRUPT_PORT0
5670 + port*4,
5671 NIG_STATUS_EMAC0_MI_INT);
5672 else
5673 bnx2x_bits_dis(bp,
5674 NIG_REG_STATUS_INTERRUPT_PORT0
5675 + port*4,
5676 NIG_STATUS_EMAC0_MI_INT);
5677
5678 if (latch_status & 1) {
5679
5680 /* For all latched-signal=up : Re-Arm Latch signals */
5681 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5682 (latch_status & 0xfffe) | (latch_status & 1));
5683 }
5684 /* For all latched-signal=up,Write original_signal to status */
5685 }
5686
5687 static void bnx2x_link_int_ack(struct link_params *params,
5688 struct link_vars *vars, u8 is_10g_plus)
5689 {
5690 struct bnx2x *bp = params->bp;
5691 u8 port = params->port;
5692 u32 mask;
5693 /*
5694 * First reset all status we assume only one line will be
5695 * change at a time
5696 */
5697 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5698 (NIG_STATUS_XGXS0_LINK10G |
5699 NIG_STATUS_XGXS0_LINK_STATUS |
5700 NIG_STATUS_SERDES0_LINK_STATUS));
5701 if (vars->phy_link_up) {
5702 if (USES_WARPCORE(bp))
5703 mask = NIG_STATUS_XGXS0_LINK_STATUS;
5704 else {
5705 if (is_10g_plus)
5706 mask = NIG_STATUS_XGXS0_LINK10G;
5707 else if (params->switch_cfg == SWITCH_CFG_10G) {
5708 /*
5709 * Disable the link interrupt by writing 1 to
5710 * the relevant lane in the status register
5711 */
5712 u32 ser_lane =
5713 ((params->lane_config &
5714 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5715 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5716 mask = ((1 << ser_lane) <<
5717 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5718 } else
5719 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5720 }
5721 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5722 mask);
5723 bnx2x_bits_en(bp,
5724 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5725 mask);
5726 }
5727 }
5728
5729 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5730 {
5731 u8 *str_ptr = str;
5732 u32 mask = 0xf0000000;
5733 u8 shift = 8*4;
5734 u8 digit;
5735 u8 remove_leading_zeros = 1;
5736 if (*len < 10) {
5737 /* Need more than 10chars for this format */
5738 *str_ptr = '\0';
5739 (*len)--;
5740 return -EINVAL;
5741 }
5742 while (shift > 0) {
5743
5744 shift -= 4;
5745 digit = ((num & mask) >> shift);
5746 if (digit == 0 && remove_leading_zeros) {
5747 mask = mask >> 4;
5748 continue;
5749 } else if (digit < 0xa)
5750 *str_ptr = digit + '0';
5751 else
5752 *str_ptr = digit - 0xa + 'a';
5753 remove_leading_zeros = 0;
5754 str_ptr++;
5755 (*len)--;
5756 mask = mask >> 4;
5757 if (shift == 4*4) {
5758 *str_ptr = '.';
5759 str_ptr++;
5760 (*len)--;
5761 remove_leading_zeros = 1;
5762 }
5763 }
5764 return 0;
5765 }
5766
5767
5768 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5769 {
5770 str[0] = '\0';
5771 (*len)--;
5772 return 0;
5773 }
5774
5775 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5776 u8 *version, u16 len)
5777 {
5778 struct bnx2x *bp;
5779 u32 spirom_ver = 0;
5780 int status = 0;
5781 u8 *ver_p = version;
5782 u16 remain_len = len;
5783 if (version == NULL || params == NULL)
5784 return -EINVAL;
5785 bp = params->bp;
5786
5787 /* Extract first external phy*/
5788 version[0] = '\0';
5789 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5790
5791 if (params->phy[EXT_PHY1].format_fw_ver) {
5792 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5793 ver_p,
5794 &remain_len);
5795 ver_p += (len - remain_len);
5796 }
5797 if ((params->num_phys == MAX_PHYS) &&
5798 (params->phy[EXT_PHY2].ver_addr != 0)) {
5799 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5800 if (params->phy[EXT_PHY2].format_fw_ver) {
5801 *ver_p = '/';
5802 ver_p++;
5803 remain_len--;
5804 status |= params->phy[EXT_PHY2].format_fw_ver(
5805 spirom_ver,
5806 ver_p,
5807 &remain_len);
5808 ver_p = version + (len - remain_len);
5809 }
5810 }
5811 *ver_p = '\0';
5812 return status;
5813 }
5814
5815 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5816 struct link_params *params)
5817 {
5818 u8 port = params->port;
5819 struct bnx2x *bp = params->bp;
5820
5821 if (phy->req_line_speed != SPEED_1000) {
5822 u32 md_devad = 0;
5823
5824 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5825
5826 if (!CHIP_IS_E3(bp)) {
5827 /* change the uni_phy_addr in the nig */
5828 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5829 port*0x18));
5830
5831 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5832 0x5);
5833 }
5834
5835 bnx2x_cl45_write(bp, phy,
5836 5,
5837 (MDIO_REG_BANK_AER_BLOCK +
5838 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5839 0x2800);
5840
5841 bnx2x_cl45_write(bp, phy,
5842 5,
5843 (MDIO_REG_BANK_CL73_IEEEB0 +
5844 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5845 0x6041);
5846 msleep(200);
5847 /* set aer mmd back */
5848 bnx2x_set_aer_mmd(params, phy);
5849
5850 if (!CHIP_IS_E3(bp)) {
5851 /* and md_devad */
5852 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5853 md_devad);
5854 }
5855 } else {
5856 u16 mii_ctrl;
5857 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5858 bnx2x_cl45_read(bp, phy, 5,
5859 (MDIO_REG_BANK_COMBO_IEEE0 +
5860 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5861 &mii_ctrl);
5862 bnx2x_cl45_write(bp, phy, 5,
5863 (MDIO_REG_BANK_COMBO_IEEE0 +
5864 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5865 mii_ctrl |
5866 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5867 }
5868 }
5869
5870 int bnx2x_set_led(struct link_params *params,
5871 struct link_vars *vars, u8 mode, u32 speed)
5872 {
5873 u8 port = params->port;
5874 u16 hw_led_mode = params->hw_led_mode;
5875 int rc = 0;
5876 u8 phy_idx;
5877 u32 tmp;
5878 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5879 struct bnx2x *bp = params->bp;
5880 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5881 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5882 speed, hw_led_mode);
5883 /* In case */
5884 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5885 if (params->phy[phy_idx].set_link_led) {
5886 params->phy[phy_idx].set_link_led(
5887 &params->phy[phy_idx], params, mode);
5888 }
5889 }
5890
5891 switch (mode) {
5892 case LED_MODE_FRONT_PANEL_OFF:
5893 case LED_MODE_OFF:
5894 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5895 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5896 SHARED_HW_CFG_LED_MAC1);
5897
5898 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5899 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5900 break;
5901
5902 case LED_MODE_OPER:
5903 /*
5904 * For all other phys, OPER mode is same as ON, so in case
5905 * link is down, do nothing
5906 */
5907 if (!vars->link_up)
5908 break;
5909 case LED_MODE_ON:
5910 if (((params->phy[EXT_PHY1].type ==
5911 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5912 (params->phy[EXT_PHY1].type ==
5913 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5914 CHIP_IS_E2(bp) && params->num_phys == 2) {
5915 /*
5916 * This is a work-around for E2+8727 Configurations
5917 */
5918 if (mode == LED_MODE_ON ||
5919 speed == SPEED_10000){
5920 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5921 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5922
5923 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5924 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5925 (tmp | EMAC_LED_OVERRIDE));
5926 /*
5927 * return here without enabling traffic
5928 * LED blink and setting rate in ON mode.
5929 * In oper mode, enabling LED blink
5930 * and setting rate is needed.
5931 */
5932 if (mode == LED_MODE_ON)
5933 return rc;
5934 }
5935 } else if (SINGLE_MEDIA_DIRECT(params)) {
5936 /*
5937 * This is a work-around for HW issue found when link
5938 * is up in CL73
5939 */
5940 if ((!CHIP_IS_E3(bp)) ||
5941 (CHIP_IS_E3(bp) &&
5942 mode == LED_MODE_ON))
5943 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5944
5945 if (CHIP_IS_E1x(bp) ||
5946 CHIP_IS_E2(bp) ||
5947 (mode == LED_MODE_ON))
5948 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5949 else
5950 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5951 hw_led_mode);
5952 } else
5953 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5954
5955 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5956 /* Set blinking rate to ~15.9Hz */
5957 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5958 LED_BLINK_RATE_VAL);
5959 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5960 port*4, 1);
5961 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5962 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5963
5964 if (CHIP_IS_E1(bp) &&
5965 ((speed == SPEED_2500) ||
5966 (speed == SPEED_1000) ||
5967 (speed == SPEED_100) ||
5968 (speed == SPEED_10))) {
5969 /*
5970 * On Everest 1 Ax chip versions for speeds less than
5971 * 10G LED scheme is different
5972 */
5973 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5974 + port*4, 1);
5975 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5976 port*4, 0);
5977 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5978 port*4, 1);
5979 }
5980 break;
5981
5982 default:
5983 rc = -EINVAL;
5984 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5985 mode);
5986 break;
5987 }
5988 return rc;
5989
5990 }
5991
5992 /*
5993 * This function comes to reflect the actual link state read DIRECTLY from the
5994 * HW
5995 */
5996 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5997 u8 is_serdes)
5998 {
5999 struct bnx2x *bp = params->bp;
6000 u16 gp_status = 0, phy_index = 0;
6001 u8 ext_phy_link_up = 0, serdes_phy_type;
6002 struct link_vars temp_vars;
6003 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6004
6005 if (CHIP_IS_E3(bp)) {
6006 u16 link_up;
6007 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6008 > SPEED_10000) {
6009 /* Check 20G link */
6010 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6011 1, &link_up);
6012 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6013 1, &link_up);
6014 link_up &= (1<<2);
6015 } else {
6016 /* Check 10G link and below*/
6017 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6018 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6019 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6020 &gp_status);
6021 gp_status = ((gp_status >> 8) & 0xf) |
6022 ((gp_status >> 12) & 0xf);
6023 link_up = gp_status & (1 << lane);
6024 }
6025 if (!link_up)
6026 return -ESRCH;
6027 } else {
6028 CL22_RD_OVER_CL45(bp, int_phy,
6029 MDIO_REG_BANK_GP_STATUS,
6030 MDIO_GP_STATUS_TOP_AN_STATUS1,
6031 &gp_status);
6032 /* link is up only if both local phy and external phy are up */
6033 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6034 return -ESRCH;
6035 }
6036 /* In XGXS loopback mode, do not check external PHY */
6037 if (params->loopback_mode == LOOPBACK_XGXS)
6038 return 0;
6039
6040 switch (params->num_phys) {
6041 case 1:
6042 /* No external PHY */
6043 return 0;
6044 case 2:
6045 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6046 &params->phy[EXT_PHY1],
6047 params, &temp_vars);
6048 break;
6049 case 3: /* Dual Media */
6050 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6051 phy_index++) {
6052 serdes_phy_type = ((params->phy[phy_index].media_type ==
6053 ETH_PHY_SFP_FIBER) ||
6054 (params->phy[phy_index].media_type ==
6055 ETH_PHY_XFP_FIBER) ||
6056 (params->phy[phy_index].media_type ==
6057 ETH_PHY_DA_TWINAX));
6058
6059 if (is_serdes != serdes_phy_type)
6060 continue;
6061 if (params->phy[phy_index].read_status) {
6062 ext_phy_link_up |=
6063 params->phy[phy_index].read_status(
6064 &params->phy[phy_index],
6065 params, &temp_vars);
6066 }
6067 }
6068 break;
6069 }
6070 if (ext_phy_link_up)
6071 return 0;
6072 return -ESRCH;
6073 }
6074
6075 static int bnx2x_link_initialize(struct link_params *params,
6076 struct link_vars *vars)
6077 {
6078 int rc = 0;
6079 u8 phy_index, non_ext_phy;
6080 struct bnx2x *bp = params->bp;
6081 /*
6082 * In case of external phy existence, the line speed would be the
6083 * line speed linked up by the external phy. In case it is direct
6084 * only, then the line_speed during initialization will be
6085 * equal to the req_line_speed
6086 */
6087 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6088
6089 /*
6090 * Initialize the internal phy in case this is a direct board
6091 * (no external phys), or this board has external phy which requires
6092 * to first.
6093 */
6094 if (!USES_WARPCORE(bp))
6095 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6096 /* init ext phy and enable link state int */
6097 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6098 (params->loopback_mode == LOOPBACK_XGXS));
6099
6100 if (non_ext_phy ||
6101 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6102 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6103 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6104 if (vars->line_speed == SPEED_AUTO_NEG &&
6105 (CHIP_IS_E1x(bp) ||
6106 CHIP_IS_E2(bp)))
6107 bnx2x_set_parallel_detection(phy, params);
6108 if (params->phy[INT_PHY].config_init)
6109 params->phy[INT_PHY].config_init(phy,
6110 params,
6111 vars);
6112 }
6113
6114 /* Init external phy*/
6115 if (non_ext_phy) {
6116 if (params->phy[INT_PHY].supported &
6117 SUPPORTED_FIBRE)
6118 vars->link_status |= LINK_STATUS_SERDES_LINK;
6119 } else {
6120 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6121 phy_index++) {
6122 /*
6123 * No need to initialize second phy in case of first
6124 * phy only selection. In case of second phy, we do
6125 * need to initialize the first phy, since they are
6126 * connected.
6127 */
6128 if (params->phy[phy_index].supported &
6129 SUPPORTED_FIBRE)
6130 vars->link_status |= LINK_STATUS_SERDES_LINK;
6131
6132 if (phy_index == EXT_PHY2 &&
6133 (bnx2x_phy_selection(params) ==
6134 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6135 DP(NETIF_MSG_LINK,
6136 "Not initializing second phy\n");
6137 continue;
6138 }
6139 params->phy[phy_index].config_init(
6140 &params->phy[phy_index],
6141 params, vars);
6142 }
6143 }
6144 /* Reset the interrupt indication after phy was initialized */
6145 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6146 params->port*4,
6147 (NIG_STATUS_XGXS0_LINK10G |
6148 NIG_STATUS_XGXS0_LINK_STATUS |
6149 NIG_STATUS_SERDES0_LINK_STATUS |
6150 NIG_MASK_MI_INT));
6151 bnx2x_update_mng(params, vars->link_status);
6152 return rc;
6153 }
6154
6155 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6156 struct link_params *params)
6157 {
6158 /* reset the SerDes/XGXS */
6159 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6160 (0x1ff << (params->port*16)));
6161 }
6162
6163 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6164 struct link_params *params)
6165 {
6166 struct bnx2x *bp = params->bp;
6167 u8 gpio_port;
6168 /* HW reset */
6169 if (CHIP_IS_E2(bp))
6170 gpio_port = BP_PATH(bp);
6171 else
6172 gpio_port = params->port;
6173 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6174 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6175 gpio_port);
6176 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6177 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6178 gpio_port);
6179 DP(NETIF_MSG_LINK, "reset external PHY\n");
6180 }
6181
6182 static int bnx2x_update_link_down(struct link_params *params,
6183 struct link_vars *vars)
6184 {
6185 struct bnx2x *bp = params->bp;
6186 u8 port = params->port;
6187
6188 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6189 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6190 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6191 /* indicate no mac active */
6192 vars->mac_type = MAC_TYPE_NONE;
6193
6194 /* update shared memory */
6195 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6196 LINK_STATUS_LINK_UP |
6197 LINK_STATUS_PHYSICAL_LINK_FLAG |
6198 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6199 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6200 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6201 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6202 vars->line_speed = 0;
6203 bnx2x_update_mng(params, vars->link_status);
6204
6205 /* activate nig drain */
6206 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6207
6208 /* disable emac */
6209 if (!CHIP_IS_E3(bp))
6210 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6211
6212 msleep(10);
6213 /* reset BigMac/Xmac */
6214 if (CHIP_IS_E1x(bp) ||
6215 CHIP_IS_E2(bp)) {
6216 bnx2x_bmac_rx_disable(bp, params->port);
6217 REG_WR(bp, GRCBASE_MISC +
6218 MISC_REGISTERS_RESET_REG_2_CLEAR,
6219 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6220 }
6221 if (CHIP_IS_E3(bp))
6222 bnx2x_xmac_disable(params);
6223
6224 return 0;
6225 }
6226
6227 static int bnx2x_update_link_up(struct link_params *params,
6228 struct link_vars *vars,
6229 u8 link_10g)
6230 {
6231 struct bnx2x *bp = params->bp;
6232 u8 port = params->port;
6233 int rc = 0;
6234
6235 vars->link_status |= (LINK_STATUS_LINK_UP |
6236 LINK_STATUS_PHYSICAL_LINK_FLAG);
6237 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6238
6239 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6240 vars->link_status |=
6241 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6242
6243 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6244 vars->link_status |=
6245 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6246 if (USES_WARPCORE(bp)) {
6247 if (link_10g) {
6248 if (bnx2x_xmac_enable(params, vars, 0) ==
6249 -ESRCH) {
6250 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6251 vars->link_up = 0;
6252 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6253 vars->link_status &= ~LINK_STATUS_LINK_UP;
6254 }
6255 } else
6256 bnx2x_umac_enable(params, vars, 0);
6257 bnx2x_set_led(params, vars,
6258 LED_MODE_OPER, vars->line_speed);
6259 }
6260 if ((CHIP_IS_E1x(bp) ||
6261 CHIP_IS_E2(bp))) {
6262 if (link_10g) {
6263 if (bnx2x_bmac_enable(params, vars, 0) ==
6264 -ESRCH) {
6265 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6266 vars->link_up = 0;
6267 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6268 vars->link_status &= ~LINK_STATUS_LINK_UP;
6269 }
6270
6271 bnx2x_set_led(params, vars,
6272 LED_MODE_OPER, SPEED_10000);
6273 } else {
6274 rc = bnx2x_emac_program(params, vars);
6275 bnx2x_emac_enable(params, vars, 0);
6276
6277 /* AN complete? */
6278 if ((vars->link_status &
6279 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6280 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6281 SINGLE_MEDIA_DIRECT(params))
6282 bnx2x_set_gmii_tx_driver(params);
6283 }
6284 }
6285
6286 /* PBF - link up */
6287 if (CHIP_IS_E1x(bp))
6288 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6289 vars->line_speed);
6290
6291 /* disable drain */
6292 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6293
6294 /* update shared memory */
6295 bnx2x_update_mng(params, vars->link_status);
6296 msleep(20);
6297 return rc;
6298 }
6299 /*
6300 * The bnx2x_link_update function should be called upon link
6301 * interrupt.
6302 * Link is considered up as follows:
6303 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6304 * to be up
6305 * - SINGLE_MEDIA - The link between the 577xx and the external
6306 * phy (XGXS) need to up as well as the external link of the
6307 * phy (PHY_EXT1)
6308 * - DUAL_MEDIA - The link between the 577xx and the first
6309 * external phy needs to be up, and at least one of the 2
6310 * external phy link must be up.
6311 */
6312 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6313 {
6314 struct bnx2x *bp = params->bp;
6315 struct link_vars phy_vars[MAX_PHYS];
6316 u8 port = params->port;
6317 u8 link_10g_plus, phy_index;
6318 u8 ext_phy_link_up = 0, cur_link_up;
6319 int rc = 0;
6320 u8 is_mi_int = 0;
6321 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6322 u8 active_external_phy = INT_PHY;
6323 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6324 for (phy_index = INT_PHY; phy_index < params->num_phys;
6325 phy_index++) {
6326 phy_vars[phy_index].flow_ctrl = 0;
6327 phy_vars[phy_index].link_status = 0;
6328 phy_vars[phy_index].line_speed = 0;
6329 phy_vars[phy_index].duplex = DUPLEX_FULL;
6330 phy_vars[phy_index].phy_link_up = 0;
6331 phy_vars[phy_index].link_up = 0;
6332 phy_vars[phy_index].fault_detected = 0;
6333 }
6334
6335 if (USES_WARPCORE(bp))
6336 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6337
6338 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6339 port, (vars->phy_flags & PHY_XGXS_FLAG),
6340 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6341
6342 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6343 port*0x18) > 0);
6344 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6345 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6346 is_mi_int,
6347 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6348
6349 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6350 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6351 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6352
6353 /* disable emac */
6354 if (!CHIP_IS_E3(bp))
6355 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6356
6357 /*
6358 * Step 1:
6359 * Check external link change only for external phys, and apply
6360 * priority selection between them in case the link on both phys
6361 * is up. Note that instead of the common vars, a temporary
6362 * vars argument is used since each phy may have different link/
6363 * speed/duplex result
6364 */
6365 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6366 phy_index++) {
6367 struct bnx2x_phy *phy = &params->phy[phy_index];
6368 if (!phy->read_status)
6369 continue;
6370 /* Read link status and params of this ext phy */
6371 cur_link_up = phy->read_status(phy, params,
6372 &phy_vars[phy_index]);
6373 if (cur_link_up) {
6374 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6375 phy_index);
6376 } else {
6377 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6378 phy_index);
6379 continue;
6380 }
6381
6382 if (!ext_phy_link_up) {
6383 ext_phy_link_up = 1;
6384 active_external_phy = phy_index;
6385 } else {
6386 switch (bnx2x_phy_selection(params)) {
6387 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6388 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6389 /*
6390 * In this option, the first PHY makes sure to pass the
6391 * traffic through itself only.
6392 * Its not clear how to reset the link on the second phy
6393 */
6394 active_external_phy = EXT_PHY1;
6395 break;
6396 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6397 /*
6398 * In this option, the first PHY makes sure to pass the
6399 * traffic through the second PHY.
6400 */
6401 active_external_phy = EXT_PHY2;
6402 break;
6403 default:
6404 /*
6405 * Link indication on both PHYs with the following cases
6406 * is invalid:
6407 * - FIRST_PHY means that second phy wasn't initialized,
6408 * hence its link is expected to be down
6409 * - SECOND_PHY means that first phy should not be able
6410 * to link up by itself (using configuration)
6411 * - DEFAULT should be overriden during initialiazation
6412 */
6413 DP(NETIF_MSG_LINK, "Invalid link indication"
6414 "mpc=0x%x. DISABLING LINK !!!\n",
6415 params->multi_phy_config);
6416 ext_phy_link_up = 0;
6417 break;
6418 }
6419 }
6420 }
6421 prev_line_speed = vars->line_speed;
6422 /*
6423 * Step 2:
6424 * Read the status of the internal phy. In case of
6425 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6426 * otherwise this is the link between the 577xx and the first
6427 * external phy
6428 */
6429 if (params->phy[INT_PHY].read_status)
6430 params->phy[INT_PHY].read_status(
6431 &params->phy[INT_PHY],
6432 params, vars);
6433 /*
6434 * The INT_PHY flow control reside in the vars. This include the
6435 * case where the speed or flow control are not set to AUTO.
6436 * Otherwise, the active external phy flow control result is set
6437 * to the vars. The ext_phy_line_speed is needed to check if the
6438 * speed is different between the internal phy and external phy.
6439 * This case may be result of intermediate link speed change.
6440 */
6441 if (active_external_phy > INT_PHY) {
6442 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6443 /*
6444 * Link speed is taken from the XGXS. AN and FC result from
6445 * the external phy.
6446 */
6447 vars->link_status |= phy_vars[active_external_phy].link_status;
6448
6449 /*
6450 * if active_external_phy is first PHY and link is up - disable
6451 * disable TX on second external PHY
6452 */
6453 if (active_external_phy == EXT_PHY1) {
6454 if (params->phy[EXT_PHY2].phy_specific_func) {
6455 DP(NETIF_MSG_LINK,
6456 "Disabling TX on EXT_PHY2\n");
6457 params->phy[EXT_PHY2].phy_specific_func(
6458 &params->phy[EXT_PHY2],
6459 params, DISABLE_TX);
6460 }
6461 }
6462
6463 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6464 vars->duplex = phy_vars[active_external_phy].duplex;
6465 if (params->phy[active_external_phy].supported &
6466 SUPPORTED_FIBRE)
6467 vars->link_status |= LINK_STATUS_SERDES_LINK;
6468 else
6469 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6470 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6471 active_external_phy);
6472 }
6473
6474 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6475 phy_index++) {
6476 if (params->phy[phy_index].flags &
6477 FLAGS_REARM_LATCH_SIGNAL) {
6478 bnx2x_rearm_latch_signal(bp, port,
6479 phy_index ==
6480 active_external_phy);
6481 break;
6482 }
6483 }
6484 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6485 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6486 vars->link_status, ext_phy_line_speed);
6487 /*
6488 * Upon link speed change set the NIG into drain mode. Comes to
6489 * deals with possible FIFO glitch due to clk change when speed
6490 * is decreased without link down indicator
6491 */
6492
6493 if (vars->phy_link_up) {
6494 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6495 (ext_phy_line_speed != vars->line_speed)) {
6496 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6497 " different than the external"
6498 " link speed %d\n", vars->line_speed,
6499 ext_phy_line_speed);
6500 vars->phy_link_up = 0;
6501 } else if (prev_line_speed != vars->line_speed) {
6502 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6503 0);
6504 msleep(1);
6505 }
6506 }
6507
6508 /* anything 10 and over uses the bmac */
6509 link_10g_plus = (vars->line_speed >= SPEED_10000);
6510
6511 bnx2x_link_int_ack(params, vars, link_10g_plus);
6512
6513 /*
6514 * In case external phy link is up, and internal link is down
6515 * (not initialized yet probably after link initialization, it
6516 * needs to be initialized.
6517 * Note that after link down-up as result of cable plug, the xgxs
6518 * link would probably become up again without the need
6519 * initialize it
6520 */
6521 if (!(SINGLE_MEDIA_DIRECT(params))) {
6522 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6523 " init_preceding = %d\n", ext_phy_link_up,
6524 vars->phy_link_up,
6525 params->phy[EXT_PHY1].flags &
6526 FLAGS_INIT_XGXS_FIRST);
6527 if (!(params->phy[EXT_PHY1].flags &
6528 FLAGS_INIT_XGXS_FIRST)
6529 && ext_phy_link_up && !vars->phy_link_up) {
6530 vars->line_speed = ext_phy_line_speed;
6531 if (vars->line_speed < SPEED_1000)
6532 vars->phy_flags |= PHY_SGMII_FLAG;
6533 else
6534 vars->phy_flags &= ~PHY_SGMII_FLAG;
6535
6536 if (params->phy[INT_PHY].config_init)
6537 params->phy[INT_PHY].config_init(
6538 &params->phy[INT_PHY], params,
6539 vars);
6540 }
6541 }
6542 /*
6543 * Link is up only if both local phy and external phy (in case of
6544 * non-direct board) are up and no fault detected on active PHY.
6545 */
6546 vars->link_up = (vars->phy_link_up &&
6547 (ext_phy_link_up ||
6548 SINGLE_MEDIA_DIRECT(params)) &&
6549 (phy_vars[active_external_phy].fault_detected == 0));
6550
6551 if (vars->link_up)
6552 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6553 else
6554 rc = bnx2x_update_link_down(params, vars);
6555
6556 return rc;
6557 }
6558
6559
6560 /*****************************************************************************/
6561 /* External Phy section */
6562 /*****************************************************************************/
6563 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6564 {
6565 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6566 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6567 msleep(1);
6568 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6569 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6570 }
6571
6572 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6573 u32 spirom_ver, u32 ver_addr)
6574 {
6575 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6576 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6577
6578 if (ver_addr)
6579 REG_WR(bp, ver_addr, spirom_ver);
6580 }
6581
6582 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6583 struct bnx2x_phy *phy,
6584 u8 port)
6585 {
6586 u16 fw_ver1, fw_ver2;
6587
6588 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6589 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6590 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6591 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6592 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6593 phy->ver_addr);
6594 }
6595
6596 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6597 struct bnx2x_phy *phy,
6598 struct link_vars *vars)
6599 {
6600 u16 val;
6601 bnx2x_cl45_read(bp, phy,
6602 MDIO_AN_DEVAD,
6603 MDIO_AN_REG_STATUS, &val);
6604 bnx2x_cl45_read(bp, phy,
6605 MDIO_AN_DEVAD,
6606 MDIO_AN_REG_STATUS, &val);
6607 if (val & (1<<5))
6608 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6609 if ((val & (1<<0)) == 0)
6610 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6611 }
6612
6613 /******************************************************************/
6614 /* common BCM8073/BCM8727 PHY SECTION */
6615 /******************************************************************/
6616 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6617 struct link_params *params,
6618 struct link_vars *vars)
6619 {
6620 struct bnx2x *bp = params->bp;
6621 if (phy->req_line_speed == SPEED_10 ||
6622 phy->req_line_speed == SPEED_100) {
6623 vars->flow_ctrl = phy->req_flow_ctrl;
6624 return;
6625 }
6626
6627 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6628 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6629 u16 pause_result;
6630 u16 ld_pause; /* local */
6631 u16 lp_pause; /* link partner */
6632 bnx2x_cl45_read(bp, phy,
6633 MDIO_AN_DEVAD,
6634 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6635
6636 bnx2x_cl45_read(bp, phy,
6637 MDIO_AN_DEVAD,
6638 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6639 pause_result = (ld_pause &
6640 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6641 pause_result |= (lp_pause &
6642 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6643
6644 bnx2x_pause_resolve(vars, pause_result);
6645 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6646 pause_result);
6647 }
6648 }
6649 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6650 struct bnx2x_phy *phy,
6651 u8 port)
6652 {
6653 u32 count = 0;
6654 u16 fw_ver1, fw_msgout;
6655 int rc = 0;
6656
6657 /* Boot port from external ROM */
6658 /* EDC grst */
6659 bnx2x_cl45_write(bp, phy,
6660 MDIO_PMA_DEVAD,
6661 MDIO_PMA_REG_GEN_CTRL,
6662 0x0001);
6663
6664 /* ucode reboot and rst */
6665 bnx2x_cl45_write(bp, phy,
6666 MDIO_PMA_DEVAD,
6667 MDIO_PMA_REG_GEN_CTRL,
6668 0x008c);
6669
6670 bnx2x_cl45_write(bp, phy,
6671 MDIO_PMA_DEVAD,
6672 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6673
6674 /* Reset internal microprocessor */
6675 bnx2x_cl45_write(bp, phy,
6676 MDIO_PMA_DEVAD,
6677 MDIO_PMA_REG_GEN_CTRL,
6678 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6679
6680 /* Release srst bit */
6681 bnx2x_cl45_write(bp, phy,
6682 MDIO_PMA_DEVAD,
6683 MDIO_PMA_REG_GEN_CTRL,
6684 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6685
6686 /* Delay 100ms per the PHY specifications */
6687 msleep(100);
6688
6689 /* 8073 sometimes taking longer to download */
6690 do {
6691 count++;
6692 if (count > 300) {
6693 DP(NETIF_MSG_LINK,
6694 "bnx2x_8073_8727_external_rom_boot port %x:"
6695 "Download failed. fw version = 0x%x\n",
6696 port, fw_ver1);
6697 rc = -EINVAL;
6698 break;
6699 }
6700
6701 bnx2x_cl45_read(bp, phy,
6702 MDIO_PMA_DEVAD,
6703 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6704 bnx2x_cl45_read(bp, phy,
6705 MDIO_PMA_DEVAD,
6706 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6707
6708 msleep(1);
6709 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6710 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6711 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6712
6713 /* Clear ser_boot_ctl bit */
6714 bnx2x_cl45_write(bp, phy,
6715 MDIO_PMA_DEVAD,
6716 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6717 bnx2x_save_bcm_spirom_ver(bp, phy, port);
6718
6719 DP(NETIF_MSG_LINK,
6720 "bnx2x_8073_8727_external_rom_boot port %x:"
6721 "Download complete. fw version = 0x%x\n",
6722 port, fw_ver1);
6723
6724 return rc;
6725 }
6726
6727 /******************************************************************/
6728 /* BCM8073 PHY SECTION */
6729 /******************************************************************/
6730 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6731 {
6732 /* This is only required for 8073A1, version 102 only */
6733 u16 val;
6734
6735 /* Read 8073 HW revision*/
6736 bnx2x_cl45_read(bp, phy,
6737 MDIO_PMA_DEVAD,
6738 MDIO_PMA_REG_8073_CHIP_REV, &val);
6739
6740 if (val != 1) {
6741 /* No need to workaround in 8073 A1 */
6742 return 0;
6743 }
6744
6745 bnx2x_cl45_read(bp, phy,
6746 MDIO_PMA_DEVAD,
6747 MDIO_PMA_REG_ROM_VER2, &val);
6748
6749 /* SNR should be applied only for version 0x102 */
6750 if (val != 0x102)
6751 return 0;
6752
6753 return 1;
6754 }
6755
6756 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6757 {
6758 u16 val, cnt, cnt1 ;
6759
6760 bnx2x_cl45_read(bp, phy,
6761 MDIO_PMA_DEVAD,
6762 MDIO_PMA_REG_8073_CHIP_REV, &val);
6763
6764 if (val > 0) {
6765 /* No need to workaround in 8073 A1 */
6766 return 0;
6767 }
6768 /* XAUI workaround in 8073 A0: */
6769
6770 /*
6771 * After loading the boot ROM and restarting Autoneg, poll
6772 * Dev1, Reg $C820:
6773 */
6774
6775 for (cnt = 0; cnt < 1000; cnt++) {
6776 bnx2x_cl45_read(bp, phy,
6777 MDIO_PMA_DEVAD,
6778 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6779 &val);
6780 /*
6781 * If bit [14] = 0 or bit [13] = 0, continue on with
6782 * system initialization (XAUI work-around not required, as
6783 * these bits indicate 2.5G or 1G link up).
6784 */
6785 if (!(val & (1<<14)) || !(val & (1<<13))) {
6786 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6787 return 0;
6788 } else if (!(val & (1<<15))) {
6789 DP(NETIF_MSG_LINK, "bit 15 went off\n");
6790 /*
6791 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6792 * MSB (bit15) goes to 1 (indicating that the XAUI
6793 * workaround has completed), then continue on with
6794 * system initialization.
6795 */
6796 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6797 bnx2x_cl45_read(bp, phy,
6798 MDIO_PMA_DEVAD,
6799 MDIO_PMA_REG_8073_XAUI_WA, &val);
6800 if (val & (1<<15)) {
6801 DP(NETIF_MSG_LINK,
6802 "XAUI workaround has completed\n");
6803 return 0;
6804 }
6805 msleep(3);
6806 }
6807 break;
6808 }
6809 msleep(3);
6810 }
6811 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6812 return -EINVAL;
6813 }
6814
6815 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6816 {
6817 /* Force KR or KX */
6818 bnx2x_cl45_write(bp, phy,
6819 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6820 bnx2x_cl45_write(bp, phy,
6821 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6822 bnx2x_cl45_write(bp, phy,
6823 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6824 bnx2x_cl45_write(bp, phy,
6825 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6826 }
6827
6828 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6829 struct bnx2x_phy *phy,
6830 struct link_vars *vars)
6831 {
6832 u16 cl37_val;
6833 struct bnx2x *bp = params->bp;
6834 bnx2x_cl45_read(bp, phy,
6835 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6836
6837 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6838 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6839 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6840 if ((vars->ieee_fc &
6841 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6842 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6843 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6844 }
6845 if ((vars->ieee_fc &
6846 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6847 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6848 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6849 }
6850 if ((vars->ieee_fc &
6851 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6852 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6853 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6854 }
6855 DP(NETIF_MSG_LINK,
6856 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6857
6858 bnx2x_cl45_write(bp, phy,
6859 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6860 msleep(500);
6861 }
6862
6863 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6864 struct link_params *params,
6865 struct link_vars *vars)
6866 {
6867 struct bnx2x *bp = params->bp;
6868 u16 val = 0, tmp1;
6869 u8 gpio_port;
6870 DP(NETIF_MSG_LINK, "Init 8073\n");
6871
6872 if (CHIP_IS_E2(bp))
6873 gpio_port = BP_PATH(bp);
6874 else
6875 gpio_port = params->port;
6876 /* Restore normal power mode*/
6877 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6878 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6879
6880 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6881 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6882
6883 /* enable LASI */
6884 bnx2x_cl45_write(bp, phy,
6885 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6886 bnx2x_cl45_write(bp, phy,
6887 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
6888
6889 bnx2x_8073_set_pause_cl37(params, phy, vars);
6890
6891 bnx2x_cl45_read(bp, phy,
6892 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6893
6894 bnx2x_cl45_read(bp, phy,
6895 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6896
6897 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6898
6899 /* Swap polarity if required - Must be done only in non-1G mode */
6900 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6901 /* Configure the 8073 to swap _P and _N of the KR lines */
6902 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6903 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6904 bnx2x_cl45_read(bp, phy,
6905 MDIO_PMA_DEVAD,
6906 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6907 bnx2x_cl45_write(bp, phy,
6908 MDIO_PMA_DEVAD,
6909 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6910 (val | (3<<9)));
6911 }
6912
6913
6914 /* Enable CL37 BAM */
6915 if (REG_RD(bp, params->shmem_base +
6916 offsetof(struct shmem_region, dev_info.
6917 port_hw_config[params->port].default_cfg)) &
6918 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6919
6920 bnx2x_cl45_read(bp, phy,
6921 MDIO_AN_DEVAD,
6922 MDIO_AN_REG_8073_BAM, &val);
6923 bnx2x_cl45_write(bp, phy,
6924 MDIO_AN_DEVAD,
6925 MDIO_AN_REG_8073_BAM, val | 1);
6926 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6927 }
6928 if (params->loopback_mode == LOOPBACK_EXT) {
6929 bnx2x_807x_force_10G(bp, phy);
6930 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6931 return 0;
6932 } else {
6933 bnx2x_cl45_write(bp, phy,
6934 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6935 }
6936 if (phy->req_line_speed != SPEED_AUTO_NEG) {
6937 if (phy->req_line_speed == SPEED_10000) {
6938 val = (1<<7);
6939 } else if (phy->req_line_speed == SPEED_2500) {
6940 val = (1<<5);
6941 /*
6942 * Note that 2.5G works only when used with 1G
6943 * advertisement
6944 */
6945 } else
6946 val = (1<<5);
6947 } else {
6948 val = 0;
6949 if (phy->speed_cap_mask &
6950 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6951 val |= (1<<7);
6952
6953 /* Note that 2.5G works only when used with 1G advertisement */
6954 if (phy->speed_cap_mask &
6955 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6956 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6957 val |= (1<<5);
6958 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6959 }
6960
6961 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6962 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6963
6964 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6965 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6966 (phy->req_line_speed == SPEED_2500)) {
6967 u16 phy_ver;
6968 /* Allow 2.5G for A1 and above */
6969 bnx2x_cl45_read(bp, phy,
6970 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6971 &phy_ver);
6972 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6973 if (phy_ver > 0)
6974 tmp1 |= 1;
6975 else
6976 tmp1 &= 0xfffe;
6977 } else {
6978 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6979 tmp1 &= 0xfffe;
6980 }
6981
6982 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6983 /* Add support for CL37 (passive mode) II */
6984
6985 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6986 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6987 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6988 0x20 : 0x40)));
6989
6990 /* Add support for CL37 (passive mode) III */
6991 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6992
6993 /*
6994 * The SNR will improve about 2db by changing BW and FEE main
6995 * tap. Rest commands are executed after link is up
6996 * Change FFE main cursor to 5 in EDC register
6997 */
6998 if (bnx2x_8073_is_snr_needed(bp, phy))
6999 bnx2x_cl45_write(bp, phy,
7000 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7001 0xFB0C);
7002
7003 /* Enable FEC (Forware Error Correction) Request in the AN */
7004 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7005 tmp1 |= (1<<15);
7006 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7007
7008 bnx2x_ext_phy_set_pause(params, phy, vars);
7009
7010 /* Restart autoneg */
7011 msleep(500);
7012 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7013 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7014 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7015 return 0;
7016 }
7017
7018 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7019 struct link_params *params,
7020 struct link_vars *vars)
7021 {
7022 struct bnx2x *bp = params->bp;
7023 u8 link_up = 0;
7024 u16 val1, val2;
7025 u16 link_status = 0;
7026 u16 an1000_status = 0;
7027
7028 bnx2x_cl45_read(bp, phy,
7029 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7030
7031 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7032
7033 /* clear the interrupt LASI status register */
7034 bnx2x_cl45_read(bp, phy,
7035 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7036 bnx2x_cl45_read(bp, phy,
7037 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7038 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7039 /* Clear MSG-OUT */
7040 bnx2x_cl45_read(bp, phy,
7041 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7042
7043 /* Check the LASI */
7044 bnx2x_cl45_read(bp, phy,
7045 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7046
7047 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7048
7049 /* Check the link status */
7050 bnx2x_cl45_read(bp, phy,
7051 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7052 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7053
7054 bnx2x_cl45_read(bp, phy,
7055 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7056 bnx2x_cl45_read(bp, phy,
7057 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7058 link_up = ((val1 & 4) == 4);
7059 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7060
7061 if (link_up &&
7062 ((phy->req_line_speed != SPEED_10000))) {
7063 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7064 return 0;
7065 }
7066 bnx2x_cl45_read(bp, phy,
7067 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7068 bnx2x_cl45_read(bp, phy,
7069 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7070
7071 /* Check the link status on 1.1.2 */
7072 bnx2x_cl45_read(bp, phy,
7073 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7074 bnx2x_cl45_read(bp, phy,
7075 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7076 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7077 "an_link_status=0x%x\n", val2, val1, an1000_status);
7078
7079 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7080 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7081 /*
7082 * The SNR will improve about 2dbby changing the BW and FEE main
7083 * tap. The 1st write to change FFE main tap is set before
7084 * restart AN. Change PLL Bandwidth in EDC register
7085 */
7086 bnx2x_cl45_write(bp, phy,
7087 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7088 0x26BC);
7089
7090 /* Change CDR Bandwidth in EDC register */
7091 bnx2x_cl45_write(bp, phy,
7092 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7093 0x0333);
7094 }
7095 bnx2x_cl45_read(bp, phy,
7096 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7097 &link_status);
7098
7099 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7100 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7101 link_up = 1;
7102 vars->line_speed = SPEED_10000;
7103 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7104 params->port);
7105 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7106 link_up = 1;
7107 vars->line_speed = SPEED_2500;
7108 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7109 params->port);
7110 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7111 link_up = 1;
7112 vars->line_speed = SPEED_1000;
7113 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7114 params->port);
7115 } else {
7116 link_up = 0;
7117 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7118 params->port);
7119 }
7120
7121 if (link_up) {
7122 /* Swap polarity if required */
7123 if (params->lane_config &
7124 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7125 /* Configure the 8073 to swap P and N of the KR lines */
7126 bnx2x_cl45_read(bp, phy,
7127 MDIO_XS_DEVAD,
7128 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7129 /*
7130 * Set bit 3 to invert Rx in 1G mode and clear this bit
7131 * when it`s in 10G mode.
7132 */
7133 if (vars->line_speed == SPEED_1000) {
7134 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7135 "the 8073\n");
7136 val1 |= (1<<3);
7137 } else
7138 val1 &= ~(1<<3);
7139
7140 bnx2x_cl45_write(bp, phy,
7141 MDIO_XS_DEVAD,
7142 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7143 val1);
7144 }
7145 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7146 bnx2x_8073_resolve_fc(phy, params, vars);
7147 vars->duplex = DUPLEX_FULL;
7148 }
7149 return link_up;
7150 }
7151
7152 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7153 struct link_params *params)
7154 {
7155 struct bnx2x *bp = params->bp;
7156 u8 gpio_port;
7157 if (CHIP_IS_E2(bp))
7158 gpio_port = BP_PATH(bp);
7159 else
7160 gpio_port = params->port;
7161 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7162 gpio_port);
7163 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7164 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7165 gpio_port);
7166 }
7167
7168 /******************************************************************/
7169 /* BCM8705 PHY SECTION */
7170 /******************************************************************/
7171 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7172 struct link_params *params,
7173 struct link_vars *vars)
7174 {
7175 struct bnx2x *bp = params->bp;
7176 DP(NETIF_MSG_LINK, "init 8705\n");
7177 /* Restore normal power mode*/
7178 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7179 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7180 /* HW reset */
7181 bnx2x_ext_phy_hw_reset(bp, params->port);
7182 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7183 bnx2x_wait_reset_complete(bp, phy, params);
7184
7185 bnx2x_cl45_write(bp, phy,
7186 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7187 bnx2x_cl45_write(bp, phy,
7188 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7189 bnx2x_cl45_write(bp, phy,
7190 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7191 bnx2x_cl45_write(bp, phy,
7192 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7193 /* BCM8705 doesn't have microcode, hence the 0 */
7194 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7195 return 0;
7196 }
7197
7198 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7199 struct link_params *params,
7200 struct link_vars *vars)
7201 {
7202 u8 link_up = 0;
7203 u16 val1, rx_sd;
7204 struct bnx2x *bp = params->bp;
7205 DP(NETIF_MSG_LINK, "read status 8705\n");
7206 bnx2x_cl45_read(bp, phy,
7207 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7208 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7209
7210 bnx2x_cl45_read(bp, phy,
7211 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7212 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7213
7214 bnx2x_cl45_read(bp, phy,
7215 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7216
7217 bnx2x_cl45_read(bp, phy,
7218 MDIO_PMA_DEVAD, 0xc809, &val1);
7219 bnx2x_cl45_read(bp, phy,
7220 MDIO_PMA_DEVAD, 0xc809, &val1);
7221
7222 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7223 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7224 if (link_up) {
7225 vars->line_speed = SPEED_10000;
7226 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7227 }
7228 return link_up;
7229 }
7230
7231 /******************************************************************/
7232 /* SFP+ module Section */
7233 /******************************************************************/
7234 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7235 struct bnx2x_phy *phy,
7236 u8 pmd_dis)
7237 {
7238 struct bnx2x *bp = params->bp;
7239 /*
7240 * Disable transmitter only for bootcodes which can enable it afterwards
7241 * (for D3 link)
7242 */
7243 if (pmd_dis) {
7244 if (params->feature_config_flags &
7245 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7246 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7247 else {
7248 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7249 return;
7250 }
7251 } else
7252 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7253 bnx2x_cl45_write(bp, phy,
7254 MDIO_PMA_DEVAD,
7255 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7256 }
7257
7258 static u8 bnx2x_get_gpio_port(struct link_params *params)
7259 {
7260 u8 gpio_port;
7261 u32 swap_val, swap_override;
7262 struct bnx2x *bp = params->bp;
7263 if (CHIP_IS_E2(bp))
7264 gpio_port = BP_PATH(bp);
7265 else
7266 gpio_port = params->port;
7267 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7268 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7269 return gpio_port ^ (swap_val && swap_override);
7270 }
7271
7272 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7273 struct bnx2x_phy *phy,
7274 u8 tx_en)
7275 {
7276 u16 val;
7277 u8 port = params->port;
7278 struct bnx2x *bp = params->bp;
7279 u32 tx_en_mode;
7280
7281 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7282 tx_en_mode = REG_RD(bp, params->shmem_base +
7283 offsetof(struct shmem_region,
7284 dev_info.port_hw_config[port].sfp_ctrl)) &
7285 PORT_HW_CFG_TX_LASER_MASK;
7286 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7287 "mode = %x\n", tx_en, port, tx_en_mode);
7288 switch (tx_en_mode) {
7289 case PORT_HW_CFG_TX_LASER_MDIO:
7290
7291 bnx2x_cl45_read(bp, phy,
7292 MDIO_PMA_DEVAD,
7293 MDIO_PMA_REG_PHY_IDENTIFIER,
7294 &val);
7295
7296 if (tx_en)
7297 val &= ~(1<<15);
7298 else
7299 val |= (1<<15);
7300
7301 bnx2x_cl45_write(bp, phy,
7302 MDIO_PMA_DEVAD,
7303 MDIO_PMA_REG_PHY_IDENTIFIER,
7304 val);
7305 break;
7306 case PORT_HW_CFG_TX_LASER_GPIO0:
7307 case PORT_HW_CFG_TX_LASER_GPIO1:
7308 case PORT_HW_CFG_TX_LASER_GPIO2:
7309 case PORT_HW_CFG_TX_LASER_GPIO3:
7310 {
7311 u16 gpio_pin;
7312 u8 gpio_port, gpio_mode;
7313 if (tx_en)
7314 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7315 else
7316 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7317
7318 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7319 gpio_port = bnx2x_get_gpio_port(params);
7320 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7321 break;
7322 }
7323 default:
7324 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7325 break;
7326 }
7327 }
7328
7329 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7330 struct bnx2x_phy *phy,
7331 u8 tx_en)
7332 {
7333 struct bnx2x *bp = params->bp;
7334 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7335 if (CHIP_IS_E3(bp))
7336 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7337 else
7338 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7339 }
7340
7341 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7342 struct link_params *params,
7343 u16 addr, u8 byte_cnt, u8 *o_buf)
7344 {
7345 struct bnx2x *bp = params->bp;
7346 u16 val = 0;
7347 u16 i;
7348 if (byte_cnt > 16) {
7349 DP(NETIF_MSG_LINK,
7350 "Reading from eeprom is limited to 0xf\n");
7351 return -EINVAL;
7352 }
7353 /* Set the read command byte count */
7354 bnx2x_cl45_write(bp, phy,
7355 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7356 (byte_cnt | 0xa000));
7357
7358 /* Set the read command address */
7359 bnx2x_cl45_write(bp, phy,
7360 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7361 addr);
7362
7363 /* Activate read command */
7364 bnx2x_cl45_write(bp, phy,
7365 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7366 0x2c0f);
7367
7368 /* Wait up to 500us for command complete status */
7369 for (i = 0; i < 100; i++) {
7370 bnx2x_cl45_read(bp, phy,
7371 MDIO_PMA_DEVAD,
7372 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7373 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7374 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7375 break;
7376 udelay(5);
7377 }
7378
7379 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7380 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7381 DP(NETIF_MSG_LINK,
7382 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7383 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7384 return -EINVAL;
7385 }
7386
7387 /* Read the buffer */
7388 for (i = 0; i < byte_cnt; i++) {
7389 bnx2x_cl45_read(bp, phy,
7390 MDIO_PMA_DEVAD,
7391 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7392 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7393 }
7394
7395 for (i = 0; i < 100; i++) {
7396 bnx2x_cl45_read(bp, phy,
7397 MDIO_PMA_DEVAD,
7398 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7399 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7400 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7401 return 0;
7402 msleep(1);
7403 }
7404 return -EINVAL;
7405 }
7406
7407 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7408 struct link_params *params,
7409 u16 addr, u8 byte_cnt,
7410 u8 *o_buf)
7411 {
7412 int rc = 0;
7413 u8 i, j = 0, cnt = 0;
7414 u32 data_array[4];
7415 u16 addr32;
7416 struct bnx2x *bp = params->bp;
7417 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7418 " addr %d, cnt %d\n",
7419 addr, byte_cnt);*/
7420 if (byte_cnt > 16) {
7421 DP(NETIF_MSG_LINK,
7422 "Reading from eeprom is limited to 16 bytes\n");
7423 return -EINVAL;
7424 }
7425
7426 /* 4 byte aligned address */
7427 addr32 = addr & (~0x3);
7428 do {
7429 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7430 data_array);
7431 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7432
7433 if (rc == 0) {
7434 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7435 o_buf[j] = *((u8 *)data_array + i);
7436 j++;
7437 }
7438 }
7439
7440 return rc;
7441 }
7442
7443 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7444 struct link_params *params,
7445 u16 addr, u8 byte_cnt, u8 *o_buf)
7446 {
7447 struct bnx2x *bp = params->bp;
7448 u16 val, i;
7449
7450 if (byte_cnt > 16) {
7451 DP(NETIF_MSG_LINK,
7452 "Reading from eeprom is limited to 0xf\n");
7453 return -EINVAL;
7454 }
7455
7456 /* Need to read from 1.8000 to clear it */
7457 bnx2x_cl45_read(bp, phy,
7458 MDIO_PMA_DEVAD,
7459 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7460 &val);
7461
7462 /* Set the read command byte count */
7463 bnx2x_cl45_write(bp, phy,
7464 MDIO_PMA_DEVAD,
7465 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7466 ((byte_cnt < 2) ? 2 : byte_cnt));
7467
7468 /* Set the read command address */
7469 bnx2x_cl45_write(bp, phy,
7470 MDIO_PMA_DEVAD,
7471 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7472 addr);
7473 /* Set the destination address */
7474 bnx2x_cl45_write(bp, phy,
7475 MDIO_PMA_DEVAD,
7476 0x8004,
7477 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7478
7479 /* Activate read command */
7480 bnx2x_cl45_write(bp, phy,
7481 MDIO_PMA_DEVAD,
7482 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7483 0x8002);
7484 /*
7485 * Wait appropriate time for two-wire command to finish before
7486 * polling the status register
7487 */
7488 msleep(1);
7489
7490 /* Wait up to 500us for command complete status */
7491 for (i = 0; i < 100; i++) {
7492 bnx2x_cl45_read(bp, phy,
7493 MDIO_PMA_DEVAD,
7494 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7495 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7496 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7497 break;
7498 udelay(5);
7499 }
7500
7501 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7502 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7503 DP(NETIF_MSG_LINK,
7504 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7505 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7506 return -EFAULT;
7507 }
7508
7509 /* Read the buffer */
7510 for (i = 0; i < byte_cnt; i++) {
7511 bnx2x_cl45_read(bp, phy,
7512 MDIO_PMA_DEVAD,
7513 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7514 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7515 }
7516
7517 for (i = 0; i < 100; i++) {
7518 bnx2x_cl45_read(bp, phy,
7519 MDIO_PMA_DEVAD,
7520 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7521 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7522 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7523 return 0;
7524 msleep(1);
7525 }
7526
7527 return -EINVAL;
7528 }
7529
7530 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7531 struct link_params *params, u16 addr,
7532 u8 byte_cnt, u8 *o_buf)
7533 {
7534 int rc = -EINVAL;
7535 switch (phy->type) {
7536 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7537 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7538 byte_cnt, o_buf);
7539 break;
7540 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7541 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7542 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7543 byte_cnt, o_buf);
7544 break;
7545 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7546 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7547 byte_cnt, o_buf);
7548 break;
7549 }
7550 return rc;
7551 }
7552
7553 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7554 struct link_params *params,
7555 u16 *edc_mode)
7556 {
7557 struct bnx2x *bp = params->bp;
7558 u32 sync_offset = 0, phy_idx, media_types;
7559 u8 val, check_limiting_mode = 0;
7560 *edc_mode = EDC_MODE_LIMITING;
7561
7562 phy->media_type = ETH_PHY_UNSPECIFIED;
7563 /* First check for copper cable */
7564 if (bnx2x_read_sfp_module_eeprom(phy,
7565 params,
7566 SFP_EEPROM_CON_TYPE_ADDR,
7567 1,
7568 &val) != 0) {
7569 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7570 return -EINVAL;
7571 }
7572
7573 switch (val) {
7574 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7575 {
7576 u8 copper_module_type;
7577 phy->media_type = ETH_PHY_DA_TWINAX;
7578 /*
7579 * Check if its active cable (includes SFP+ module)
7580 * of passive cable
7581 */
7582 if (bnx2x_read_sfp_module_eeprom(phy,
7583 params,
7584 SFP_EEPROM_FC_TX_TECH_ADDR,
7585 1,
7586 &copper_module_type) != 0) {
7587 DP(NETIF_MSG_LINK,
7588 "Failed to read copper-cable-type"
7589 " from SFP+ EEPROM\n");
7590 return -EINVAL;
7591 }
7592
7593 if (copper_module_type &
7594 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7595 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7596 check_limiting_mode = 1;
7597 } else if (copper_module_type &
7598 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7599 DP(NETIF_MSG_LINK,
7600 "Passive Copper cable detected\n");
7601 *edc_mode =
7602 EDC_MODE_PASSIVE_DAC;
7603 } else {
7604 DP(NETIF_MSG_LINK,
7605 "Unknown copper-cable-type 0x%x !!!\n",
7606 copper_module_type);
7607 return -EINVAL;
7608 }
7609 break;
7610 }
7611 case SFP_EEPROM_CON_TYPE_VAL_LC:
7612 phy->media_type = ETH_PHY_SFP_FIBER;
7613 DP(NETIF_MSG_LINK, "Optic module detected\n");
7614 check_limiting_mode = 1;
7615 break;
7616 default:
7617 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7618 val);
7619 return -EINVAL;
7620 }
7621 sync_offset = params->shmem_base +
7622 offsetof(struct shmem_region,
7623 dev_info.port_hw_config[params->port].media_type);
7624 media_types = REG_RD(bp, sync_offset);
7625 /* Update media type for non-PMF sync */
7626 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7627 if (&(params->phy[phy_idx]) == phy) {
7628 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7629 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7630 media_types |= ((phy->media_type &
7631 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7632 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7633 break;
7634 }
7635 }
7636 REG_WR(bp, sync_offset, media_types);
7637 if (check_limiting_mode) {
7638 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7639 if (bnx2x_read_sfp_module_eeprom(phy,
7640 params,
7641 SFP_EEPROM_OPTIONS_ADDR,
7642 SFP_EEPROM_OPTIONS_SIZE,
7643 options) != 0) {
7644 DP(NETIF_MSG_LINK,
7645 "Failed to read Option field from module EEPROM\n");
7646 return -EINVAL;
7647 }
7648 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7649 *edc_mode = EDC_MODE_LINEAR;
7650 else
7651 *edc_mode = EDC_MODE_LIMITING;
7652 }
7653 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7654 return 0;
7655 }
7656 /*
7657 * This function read the relevant field from the module (SFP+), and verify it
7658 * is compliant with this board
7659 */
7660 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7661 struct link_params *params)
7662 {
7663 struct bnx2x *bp = params->bp;
7664 u32 val, cmd;
7665 u32 fw_resp, fw_cmd_param;
7666 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7667 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7668 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7669 val = REG_RD(bp, params->shmem_base +
7670 offsetof(struct shmem_region, dev_info.
7671 port_feature_config[params->port].config));
7672 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7673 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7674 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7675 return 0;
7676 }
7677
7678 if (params->feature_config_flags &
7679 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7680 /* Use specific phy request */
7681 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7682 } else if (params->feature_config_flags &
7683 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7684 /* Use first phy request only in case of non-dual media*/
7685 if (DUAL_MEDIA(params)) {
7686 DP(NETIF_MSG_LINK,
7687 "FW does not support OPT MDL verification\n");
7688 return -EINVAL;
7689 }
7690 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7691 } else {
7692 /* No support in OPT MDL detection */
7693 DP(NETIF_MSG_LINK,
7694 "FW does not support OPT MDL verification\n");
7695 return -EINVAL;
7696 }
7697
7698 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7699 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7700 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7701 DP(NETIF_MSG_LINK, "Approved module\n");
7702 return 0;
7703 }
7704
7705 /* format the warning message */
7706 if (bnx2x_read_sfp_module_eeprom(phy,
7707 params,
7708 SFP_EEPROM_VENDOR_NAME_ADDR,
7709 SFP_EEPROM_VENDOR_NAME_SIZE,
7710 (u8 *)vendor_name))
7711 vendor_name[0] = '\0';
7712 else
7713 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7714 if (bnx2x_read_sfp_module_eeprom(phy,
7715 params,
7716 SFP_EEPROM_PART_NO_ADDR,
7717 SFP_EEPROM_PART_NO_SIZE,
7718 (u8 *)vendor_pn))
7719 vendor_pn[0] = '\0';
7720 else
7721 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7722
7723 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
7724 " Port %d from %s part number %s\n",
7725 params->port, vendor_name, vendor_pn);
7726 phy->flags |= FLAGS_SFP_NOT_APPROVED;
7727 return -EINVAL;
7728 }
7729
7730 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7731 struct link_params *params)
7732
7733 {
7734 u8 val;
7735 struct bnx2x *bp = params->bp;
7736 u16 timeout;
7737 /*
7738 * Initialization time after hot-plug may take up to 300ms for
7739 * some phys type ( e.g. JDSU )
7740 */
7741
7742 for (timeout = 0; timeout < 60; timeout++) {
7743 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7744 == 0) {
7745 DP(NETIF_MSG_LINK,
7746 "SFP+ module initialization took %d ms\n",
7747 timeout * 5);
7748 return 0;
7749 }
7750 msleep(5);
7751 }
7752 return -EINVAL;
7753 }
7754
7755 static void bnx2x_8727_power_module(struct bnx2x *bp,
7756 struct bnx2x_phy *phy,
7757 u8 is_power_up) {
7758 /* Make sure GPIOs are not using for LED mode */
7759 u16 val;
7760 /*
7761 * In the GPIO register, bit 4 is use to determine if the GPIOs are
7762 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7763 * output
7764 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7765 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7766 * where the 1st bit is the over-current(only input), and 2nd bit is
7767 * for power( only output )
7768 *
7769 * In case of NOC feature is disabled and power is up, set GPIO control
7770 * as input to enable listening of over-current indication
7771 */
7772 if (phy->flags & FLAGS_NOC)
7773 return;
7774 if (is_power_up)
7775 val = (1<<4);
7776 else
7777 /*
7778 * Set GPIO control to OUTPUT, and set the power bit
7779 * to according to the is_power_up
7780 */
7781 val = (1<<1);
7782
7783 bnx2x_cl45_write(bp, phy,
7784 MDIO_PMA_DEVAD,
7785 MDIO_PMA_REG_8727_GPIO_CTRL,
7786 val);
7787 }
7788
7789 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7790 struct bnx2x_phy *phy,
7791 u16 edc_mode)
7792 {
7793 u16 cur_limiting_mode;
7794
7795 bnx2x_cl45_read(bp, phy,
7796 MDIO_PMA_DEVAD,
7797 MDIO_PMA_REG_ROM_VER2,
7798 &cur_limiting_mode);
7799 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7800 cur_limiting_mode);
7801
7802 if (edc_mode == EDC_MODE_LIMITING) {
7803 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7804 bnx2x_cl45_write(bp, phy,
7805 MDIO_PMA_DEVAD,
7806 MDIO_PMA_REG_ROM_VER2,
7807 EDC_MODE_LIMITING);
7808 } else { /* LRM mode ( default )*/
7809
7810 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7811
7812 /*
7813 * Changing to LRM mode takes quite few seconds. So do it only
7814 * if current mode is limiting (default is LRM)
7815 */
7816 if (cur_limiting_mode != EDC_MODE_LIMITING)
7817 return 0;
7818
7819 bnx2x_cl45_write(bp, phy,
7820 MDIO_PMA_DEVAD,
7821 MDIO_PMA_REG_LRM_MODE,
7822 0);
7823 bnx2x_cl45_write(bp, phy,
7824 MDIO_PMA_DEVAD,
7825 MDIO_PMA_REG_ROM_VER2,
7826 0x128);
7827 bnx2x_cl45_write(bp, phy,
7828 MDIO_PMA_DEVAD,
7829 MDIO_PMA_REG_MISC_CTRL0,
7830 0x4008);
7831 bnx2x_cl45_write(bp, phy,
7832 MDIO_PMA_DEVAD,
7833 MDIO_PMA_REG_LRM_MODE,
7834 0xaaaa);
7835 }
7836 return 0;
7837 }
7838
7839 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7840 struct bnx2x_phy *phy,
7841 u16 edc_mode)
7842 {
7843 u16 phy_identifier;
7844 u16 rom_ver2_val;
7845 bnx2x_cl45_read(bp, phy,
7846 MDIO_PMA_DEVAD,
7847 MDIO_PMA_REG_PHY_IDENTIFIER,
7848 &phy_identifier);
7849
7850 bnx2x_cl45_write(bp, phy,
7851 MDIO_PMA_DEVAD,
7852 MDIO_PMA_REG_PHY_IDENTIFIER,
7853 (phy_identifier & ~(1<<9)));
7854
7855 bnx2x_cl45_read(bp, phy,
7856 MDIO_PMA_DEVAD,
7857 MDIO_PMA_REG_ROM_VER2,
7858 &rom_ver2_val);
7859 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7860 bnx2x_cl45_write(bp, phy,
7861 MDIO_PMA_DEVAD,
7862 MDIO_PMA_REG_ROM_VER2,
7863 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7864
7865 bnx2x_cl45_write(bp, phy,
7866 MDIO_PMA_DEVAD,
7867 MDIO_PMA_REG_PHY_IDENTIFIER,
7868 (phy_identifier | (1<<9)));
7869
7870 return 0;
7871 }
7872
7873 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7874 struct link_params *params,
7875 u32 action)
7876 {
7877 struct bnx2x *bp = params->bp;
7878
7879 switch (action) {
7880 case DISABLE_TX:
7881 bnx2x_sfp_set_transmitter(params, phy, 0);
7882 break;
7883 case ENABLE_TX:
7884 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7885 bnx2x_sfp_set_transmitter(params, phy, 1);
7886 break;
7887 default:
7888 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7889 action);
7890 return;
7891 }
7892 }
7893
7894 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7895 u8 gpio_mode)
7896 {
7897 struct bnx2x *bp = params->bp;
7898
7899 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7900 offsetof(struct shmem_region,
7901 dev_info.port_hw_config[params->port].sfp_ctrl)) &
7902 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7903 switch (fault_led_gpio) {
7904 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7905 return;
7906 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7907 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7908 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7909 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7910 {
7911 u8 gpio_port = bnx2x_get_gpio_port(params);
7912 u16 gpio_pin = fault_led_gpio -
7913 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7914 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7915 "pin %x port %x mode %x\n",
7916 gpio_pin, gpio_port, gpio_mode);
7917 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7918 }
7919 break;
7920 default:
7921 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7922 fault_led_gpio);
7923 }
7924 }
7925
7926 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7927 u8 gpio_mode)
7928 {
7929 u32 pin_cfg;
7930 u8 port = params->port;
7931 struct bnx2x *bp = params->bp;
7932 pin_cfg = (REG_RD(bp, params->shmem_base +
7933 offsetof(struct shmem_region,
7934 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7935 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7936 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7937 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7938 gpio_mode, pin_cfg);
7939 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7940 }
7941
7942 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7943 u8 gpio_mode)
7944 {
7945 struct bnx2x *bp = params->bp;
7946 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7947 if (CHIP_IS_E3(bp)) {
7948 /*
7949 * Low ==> if SFP+ module is supported otherwise
7950 * High ==> if SFP+ module is not on the approved vendor list
7951 */
7952 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7953 } else
7954 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7955 }
7956
7957 static void bnx2x_warpcore_power_module(struct link_params *params,
7958 struct bnx2x_phy *phy,
7959 u8 power)
7960 {
7961 u32 pin_cfg;
7962 struct bnx2x *bp = params->bp;
7963
7964 pin_cfg = (REG_RD(bp, params->shmem_base +
7965 offsetof(struct shmem_region,
7966 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7967 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7968 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7969
7970 if (pin_cfg == PIN_CFG_NA)
7971 return;
7972 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7973 power, pin_cfg);
7974 /*
7975 * Low ==> corresponding SFP+ module is powered
7976 * high ==> the SFP+ module is powered down
7977 */
7978 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7979 }
7980
7981 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
7982 struct link_params *params)
7983 {
7984 bnx2x_warpcore_power_module(params, phy, 0);
7985 }
7986
7987 static void bnx2x_power_sfp_module(struct link_params *params,
7988 struct bnx2x_phy *phy,
7989 u8 power)
7990 {
7991 struct bnx2x *bp = params->bp;
7992 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7993
7994 switch (phy->type) {
7995 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7996 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7997 bnx2x_8727_power_module(params->bp, phy, power);
7998 break;
7999 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8000 bnx2x_warpcore_power_module(params, phy, power);
8001 break;
8002 default:
8003 break;
8004 }
8005 }
8006 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8007 struct bnx2x_phy *phy,
8008 u16 edc_mode)
8009 {
8010 u16 val = 0;
8011 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8012 struct bnx2x *bp = params->bp;
8013
8014 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8015 /* This is a global register which controls all lanes */
8016 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8017 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8018 val &= ~(0xf << (lane << 2));
8019
8020 switch (edc_mode) {
8021 case EDC_MODE_LINEAR:
8022 case EDC_MODE_LIMITING:
8023 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8024 break;
8025 case EDC_MODE_PASSIVE_DAC:
8026 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8027 break;
8028 default:
8029 break;
8030 }
8031
8032 val |= (mode << (lane << 2));
8033 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8034 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8035 /* A must read */
8036 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8037 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8038
8039 /* Restart microcode to re-read the new mode */
8040 bnx2x_warpcore_reset_lane(bp, phy, 1);
8041 bnx2x_warpcore_reset_lane(bp, phy, 0);
8042
8043 }
8044
8045 static void bnx2x_set_limiting_mode(struct link_params *params,
8046 struct bnx2x_phy *phy,
8047 u16 edc_mode)
8048 {
8049 switch (phy->type) {
8050 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8051 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8052 break;
8053 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8054 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8055 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8056 break;
8057 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8058 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8059 break;
8060 }
8061 }
8062
8063 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8064 struct link_params *params)
8065 {
8066 struct bnx2x *bp = params->bp;
8067 u16 edc_mode;
8068 int rc = 0;
8069
8070 u32 val = REG_RD(bp, params->shmem_base +
8071 offsetof(struct shmem_region, dev_info.
8072 port_feature_config[params->port].config));
8073
8074 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8075 params->port);
8076 /* Power up module */
8077 bnx2x_power_sfp_module(params, phy, 1);
8078 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8079 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8080 return -EINVAL;
8081 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8082 /* check SFP+ module compatibility */
8083 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8084 rc = -EINVAL;
8085 /* Turn on fault module-detected led */
8086 bnx2x_set_sfp_module_fault_led(params,
8087 MISC_REGISTERS_GPIO_HIGH);
8088
8089 /* Check if need to power down the SFP+ module */
8090 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8091 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8092 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8093 bnx2x_power_sfp_module(params, phy, 0);
8094 return rc;
8095 }
8096 } else {
8097 /* Turn off fault module-detected led */
8098 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8099 }
8100
8101 /*
8102 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8103 * is done automatically
8104 */
8105 bnx2x_set_limiting_mode(params, phy, edc_mode);
8106
8107 /*
8108 * Enable transmit for this module if the module is approved, or
8109 * if unapproved modules should also enable the Tx laser
8110 */
8111 if (rc == 0 ||
8112 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8113 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8114 bnx2x_sfp_set_transmitter(params, phy, 1);
8115 else
8116 bnx2x_sfp_set_transmitter(params, phy, 0);
8117
8118 return rc;
8119 }
8120
8121 void bnx2x_handle_module_detect_int(struct link_params *params)
8122 {
8123 struct bnx2x *bp = params->bp;
8124 struct bnx2x_phy *phy;
8125 u32 gpio_val;
8126 u8 gpio_num, gpio_port;
8127 if (CHIP_IS_E3(bp))
8128 phy = &params->phy[INT_PHY];
8129 else
8130 phy = &params->phy[EXT_PHY1];
8131
8132 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8133 params->port, &gpio_num, &gpio_port) ==
8134 -EINVAL) {
8135 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8136 return;
8137 }
8138
8139 /* Set valid module led off */
8140 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8141
8142 /* Get current gpio val reflecting module plugged in / out*/
8143 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8144
8145 /* Call the handling function in case module is detected */
8146 if (gpio_val == 0) {
8147 bnx2x_power_sfp_module(params, phy, 1);
8148 bnx2x_set_gpio_int(bp, gpio_num,
8149 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8150 gpio_port);
8151 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8152 bnx2x_sfp_module_detection(phy, params);
8153 else
8154 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8155 } else {
8156 u32 val = REG_RD(bp, params->shmem_base +
8157 offsetof(struct shmem_region, dev_info.
8158 port_feature_config[params->port].
8159 config));
8160 bnx2x_set_gpio_int(bp, gpio_num,
8161 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8162 gpio_port);
8163 /*
8164 * Module was plugged out.
8165 * Disable transmit for this module
8166 */
8167 phy->media_type = ETH_PHY_NOT_PRESENT;
8168 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8169 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8170 CHIP_IS_E3(bp))
8171 bnx2x_sfp_set_transmitter(params, phy, 0);
8172 }
8173 }
8174
8175 /******************************************************************/
8176 /* Used by 8706 and 8727 */
8177 /******************************************************************/
8178 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8179 struct bnx2x_phy *phy,
8180 u16 alarm_status_offset,
8181 u16 alarm_ctrl_offset)
8182 {
8183 u16 alarm_status, val;
8184 bnx2x_cl45_read(bp, phy,
8185 MDIO_PMA_DEVAD, alarm_status_offset,
8186 &alarm_status);
8187 bnx2x_cl45_read(bp, phy,
8188 MDIO_PMA_DEVAD, alarm_status_offset,
8189 &alarm_status);
8190 /* Mask or enable the fault event. */
8191 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8192 if (alarm_status & (1<<0))
8193 val &= ~(1<<0);
8194 else
8195 val |= (1<<0);
8196 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8197 }
8198 /******************************************************************/
8199 /* common BCM8706/BCM8726 PHY SECTION */
8200 /******************************************************************/
8201 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8202 struct link_params *params,
8203 struct link_vars *vars)
8204 {
8205 u8 link_up = 0;
8206 u16 val1, val2, rx_sd, pcs_status;
8207 struct bnx2x *bp = params->bp;
8208 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8209 /* Clear RX Alarm*/
8210 bnx2x_cl45_read(bp, phy,
8211 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8212
8213 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8214 MDIO_PMA_LASI_TXCTRL);
8215
8216 /* clear LASI indication*/
8217 bnx2x_cl45_read(bp, phy,
8218 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8219 bnx2x_cl45_read(bp, phy,
8220 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8221 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8222
8223 bnx2x_cl45_read(bp, phy,
8224 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8225 bnx2x_cl45_read(bp, phy,
8226 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8227 bnx2x_cl45_read(bp, phy,
8228 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8229 bnx2x_cl45_read(bp, phy,
8230 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8231
8232 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8233 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8234 /*
8235 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8236 * are set, or if the autoneg bit 1 is set
8237 */
8238 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8239 if (link_up) {
8240 if (val2 & (1<<1))
8241 vars->line_speed = SPEED_1000;
8242 else
8243 vars->line_speed = SPEED_10000;
8244 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8245 vars->duplex = DUPLEX_FULL;
8246 }
8247
8248 /* Capture 10G link fault. Read twice to clear stale value. */
8249 if (vars->line_speed == SPEED_10000) {
8250 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8251 MDIO_PMA_LASI_TXSTAT, &val1);
8252 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8253 MDIO_PMA_LASI_TXSTAT, &val1);
8254 if (val1 & (1<<0))
8255 vars->fault_detected = 1;
8256 }
8257
8258 return link_up;
8259 }
8260
8261 /******************************************************************/
8262 /* BCM8706 PHY SECTION */
8263 /******************************************************************/
8264 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8265 struct link_params *params,
8266 struct link_vars *vars)
8267 {
8268 u32 tx_en_mode;
8269 u16 cnt, val, tmp1;
8270 struct bnx2x *bp = params->bp;
8271
8272 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8273 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8274 /* HW reset */
8275 bnx2x_ext_phy_hw_reset(bp, params->port);
8276 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8277 bnx2x_wait_reset_complete(bp, phy, params);
8278
8279 /* Wait until fw is loaded */
8280 for (cnt = 0; cnt < 100; cnt++) {
8281 bnx2x_cl45_read(bp, phy,
8282 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8283 if (val)
8284 break;
8285 msleep(10);
8286 }
8287 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8288 if ((params->feature_config_flags &
8289 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8290 u8 i;
8291 u16 reg;
8292 for (i = 0; i < 4; i++) {
8293 reg = MDIO_XS_8706_REG_BANK_RX0 +
8294 i*(MDIO_XS_8706_REG_BANK_RX1 -
8295 MDIO_XS_8706_REG_BANK_RX0);
8296 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8297 /* Clear first 3 bits of the control */
8298 val &= ~0x7;
8299 /* Set control bits according to configuration */
8300 val |= (phy->rx_preemphasis[i] & 0x7);
8301 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8302 " reg 0x%x <-- val 0x%x\n", reg, val);
8303 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8304 }
8305 }
8306 /* Force speed */
8307 if (phy->req_line_speed == SPEED_10000) {
8308 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8309
8310 bnx2x_cl45_write(bp, phy,
8311 MDIO_PMA_DEVAD,
8312 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8313 bnx2x_cl45_write(bp, phy,
8314 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8315 0);
8316 /* Arm LASI for link and Tx fault. */
8317 bnx2x_cl45_write(bp, phy,
8318 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8319 } else {
8320 /* Force 1Gbps using autoneg with 1G advertisement */
8321
8322 /* Allow CL37 through CL73 */
8323 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8324 bnx2x_cl45_write(bp, phy,
8325 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8326
8327 /* Enable Full-Duplex advertisement on CL37 */
8328 bnx2x_cl45_write(bp, phy,
8329 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8330 /* Enable CL37 AN */
8331 bnx2x_cl45_write(bp, phy,
8332 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8333 /* 1G support */
8334 bnx2x_cl45_write(bp, phy,
8335 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8336
8337 /* Enable clause 73 AN */
8338 bnx2x_cl45_write(bp, phy,
8339 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8340 bnx2x_cl45_write(bp, phy,
8341 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8342 0x0400);
8343 bnx2x_cl45_write(bp, phy,
8344 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8345 0x0004);
8346 }
8347 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8348
8349 /*
8350 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8351 * power mode, if TX Laser is disabled
8352 */
8353
8354 tx_en_mode = REG_RD(bp, params->shmem_base +
8355 offsetof(struct shmem_region,
8356 dev_info.port_hw_config[params->port].sfp_ctrl))
8357 & PORT_HW_CFG_TX_LASER_MASK;
8358
8359 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8360 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8361 bnx2x_cl45_read(bp, phy,
8362 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8363 tmp1 |= 0x1;
8364 bnx2x_cl45_write(bp, phy,
8365 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8366 }
8367
8368 return 0;
8369 }
8370
8371 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8372 struct link_params *params,
8373 struct link_vars *vars)
8374 {
8375 return bnx2x_8706_8726_read_status(phy, params, vars);
8376 }
8377
8378 /******************************************************************/
8379 /* BCM8726 PHY SECTION */
8380 /******************************************************************/
8381 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8382 struct link_params *params)
8383 {
8384 struct bnx2x *bp = params->bp;
8385 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8386 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8387 }
8388
8389 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8390 struct link_params *params)
8391 {
8392 struct bnx2x *bp = params->bp;
8393 /* Need to wait 100ms after reset */
8394 msleep(100);
8395
8396 /* Micro controller re-boot */
8397 bnx2x_cl45_write(bp, phy,
8398 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8399
8400 /* Set soft reset */
8401 bnx2x_cl45_write(bp, phy,
8402 MDIO_PMA_DEVAD,
8403 MDIO_PMA_REG_GEN_CTRL,
8404 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8405
8406 bnx2x_cl45_write(bp, phy,
8407 MDIO_PMA_DEVAD,
8408 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8409
8410 bnx2x_cl45_write(bp, phy,
8411 MDIO_PMA_DEVAD,
8412 MDIO_PMA_REG_GEN_CTRL,
8413 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8414
8415 /* wait for 150ms for microcode load */
8416 msleep(150);
8417
8418 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8419 bnx2x_cl45_write(bp, phy,
8420 MDIO_PMA_DEVAD,
8421 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8422
8423 msleep(200);
8424 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8425 }
8426
8427 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8428 struct link_params *params,
8429 struct link_vars *vars)
8430 {
8431 struct bnx2x *bp = params->bp;
8432 u16 val1;
8433 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8434 if (link_up) {
8435 bnx2x_cl45_read(bp, phy,
8436 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8437 &val1);
8438 if (val1 & (1<<15)) {
8439 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8440 link_up = 0;
8441 vars->line_speed = 0;
8442 }
8443 }
8444 return link_up;
8445 }
8446
8447
8448 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8449 struct link_params *params,
8450 struct link_vars *vars)
8451 {
8452 struct bnx2x *bp = params->bp;
8453 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8454
8455 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8456 bnx2x_wait_reset_complete(bp, phy, params);
8457
8458 bnx2x_8726_external_rom_boot(phy, params);
8459
8460 /*
8461 * Need to call module detected on initialization since the module
8462 * detection triggered by actual module insertion might occur before
8463 * driver is loaded, and when driver is loaded, it reset all
8464 * registers, including the transmitter
8465 */
8466 bnx2x_sfp_module_detection(phy, params);
8467
8468 if (phy->req_line_speed == SPEED_1000) {
8469 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8470 bnx2x_cl45_write(bp, phy,
8471 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8472 bnx2x_cl45_write(bp, phy,
8473 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8474 bnx2x_cl45_write(bp, phy,
8475 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8476 bnx2x_cl45_write(bp, phy,
8477 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8478 0x400);
8479 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8480 (phy->speed_cap_mask &
8481 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8482 ((phy->speed_cap_mask &
8483 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8484 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8485 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8486 /* Set Flow control */
8487 bnx2x_ext_phy_set_pause(params, phy, vars);
8488 bnx2x_cl45_write(bp, phy,
8489 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8490 bnx2x_cl45_write(bp, phy,
8491 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8492 bnx2x_cl45_write(bp, phy,
8493 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8494 bnx2x_cl45_write(bp, phy,
8495 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8496 bnx2x_cl45_write(bp, phy,
8497 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8498 /*
8499 * Enable RX-ALARM control to receive interrupt for 1G speed
8500 * change
8501 */
8502 bnx2x_cl45_write(bp, phy,
8503 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8504 bnx2x_cl45_write(bp, phy,
8505 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8506 0x400);
8507
8508 } else { /* Default 10G. Set only LASI control */
8509 bnx2x_cl45_write(bp, phy,
8510 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8511 }
8512
8513 /* Set TX PreEmphasis if needed */
8514 if ((params->feature_config_flags &
8515 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8516 DP(NETIF_MSG_LINK,
8517 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8518 phy->tx_preemphasis[0],
8519 phy->tx_preemphasis[1]);
8520 bnx2x_cl45_write(bp, phy,
8521 MDIO_PMA_DEVAD,
8522 MDIO_PMA_REG_8726_TX_CTRL1,
8523 phy->tx_preemphasis[0]);
8524
8525 bnx2x_cl45_write(bp, phy,
8526 MDIO_PMA_DEVAD,
8527 MDIO_PMA_REG_8726_TX_CTRL2,
8528 phy->tx_preemphasis[1]);
8529 }
8530
8531 return 0;
8532
8533 }
8534
8535 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8536 struct link_params *params)
8537 {
8538 struct bnx2x *bp = params->bp;
8539 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8540 /* Set serial boot control for external load */
8541 bnx2x_cl45_write(bp, phy,
8542 MDIO_PMA_DEVAD,
8543 MDIO_PMA_REG_GEN_CTRL, 0x0001);
8544 }
8545
8546 /******************************************************************/
8547 /* BCM8727 PHY SECTION */
8548 /******************************************************************/
8549
8550 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8551 struct link_params *params, u8 mode)
8552 {
8553 struct bnx2x *bp = params->bp;
8554 u16 led_mode_bitmask = 0;
8555 u16 gpio_pins_bitmask = 0;
8556 u16 val;
8557 /* Only NOC flavor requires to set the LED specifically */
8558 if (!(phy->flags & FLAGS_NOC))
8559 return;
8560 switch (mode) {
8561 case LED_MODE_FRONT_PANEL_OFF:
8562 case LED_MODE_OFF:
8563 led_mode_bitmask = 0;
8564 gpio_pins_bitmask = 0x03;
8565 break;
8566 case LED_MODE_ON:
8567 led_mode_bitmask = 0;
8568 gpio_pins_bitmask = 0x02;
8569 break;
8570 case LED_MODE_OPER:
8571 led_mode_bitmask = 0x60;
8572 gpio_pins_bitmask = 0x11;
8573 break;
8574 }
8575 bnx2x_cl45_read(bp, phy,
8576 MDIO_PMA_DEVAD,
8577 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8578 &val);
8579 val &= 0xff8f;
8580 val |= led_mode_bitmask;
8581 bnx2x_cl45_write(bp, phy,
8582 MDIO_PMA_DEVAD,
8583 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8584 val);
8585 bnx2x_cl45_read(bp, phy,
8586 MDIO_PMA_DEVAD,
8587 MDIO_PMA_REG_8727_GPIO_CTRL,
8588 &val);
8589 val &= 0xffe0;
8590 val |= gpio_pins_bitmask;
8591 bnx2x_cl45_write(bp, phy,
8592 MDIO_PMA_DEVAD,
8593 MDIO_PMA_REG_8727_GPIO_CTRL,
8594 val);
8595 }
8596 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8597 struct link_params *params) {
8598 u32 swap_val, swap_override;
8599 u8 port;
8600 /*
8601 * The PHY reset is controlled by GPIO 1. Fake the port number
8602 * to cancel the swap done in set_gpio()
8603 */
8604 struct bnx2x *bp = params->bp;
8605 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8606 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8607 port = (swap_val && swap_override) ^ 1;
8608 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8609 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8610 }
8611
8612 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8613 struct link_params *params,
8614 struct link_vars *vars)
8615 {
8616 u32 tx_en_mode;
8617 u16 tmp1, val, mod_abs, tmp2;
8618 u16 rx_alarm_ctrl_val;
8619 u16 lasi_ctrl_val;
8620 struct bnx2x *bp = params->bp;
8621 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8622
8623 bnx2x_wait_reset_complete(bp, phy, params);
8624 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8625 /* Should be 0x6 to enable XS on Tx side. */
8626 lasi_ctrl_val = 0x0006;
8627
8628 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8629 /* enable LASI */
8630 bnx2x_cl45_write(bp, phy,
8631 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8632 rx_alarm_ctrl_val);
8633 bnx2x_cl45_write(bp, phy,
8634 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8635 0);
8636 bnx2x_cl45_write(bp, phy,
8637 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8638
8639 /*
8640 * Initially configure MOD_ABS to interrupt when module is
8641 * presence( bit 8)
8642 */
8643 bnx2x_cl45_read(bp, phy,
8644 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8645 /*
8646 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8647 * When the EDC is off it locks onto a reference clock and avoids
8648 * becoming 'lost'
8649 */
8650 mod_abs &= ~(1<<8);
8651 if (!(phy->flags & FLAGS_NOC))
8652 mod_abs &= ~(1<<9);
8653 bnx2x_cl45_write(bp, phy,
8654 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8655
8656
8657 /* Enable/Disable PHY transmitter output */
8658 bnx2x_set_disable_pmd_transmit(params, phy, 0);
8659
8660 /* Make MOD_ABS give interrupt on change */
8661 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8662 &val);
8663 val |= (1<<12);
8664 if (phy->flags & FLAGS_NOC)
8665 val |= (3<<5);
8666
8667 /*
8668 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8669 * status which reflect SFP+ module over-current
8670 */
8671 if (!(phy->flags & FLAGS_NOC))
8672 val &= 0xff8f; /* Reset bits 4-6 */
8673 bnx2x_cl45_write(bp, phy,
8674 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8675
8676 bnx2x_8727_power_module(bp, phy, 1);
8677
8678 bnx2x_cl45_read(bp, phy,
8679 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8680
8681 bnx2x_cl45_read(bp, phy,
8682 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8683
8684 /* Set option 1G speed */
8685 if (phy->req_line_speed == SPEED_1000) {
8686 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8687 bnx2x_cl45_write(bp, phy,
8688 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8689 bnx2x_cl45_write(bp, phy,
8690 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8691 bnx2x_cl45_read(bp, phy,
8692 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8693 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8694 /*
8695 * Power down the XAUI until link is up in case of dual-media
8696 * and 1G
8697 */
8698 if (DUAL_MEDIA(params)) {
8699 bnx2x_cl45_read(bp, phy,
8700 MDIO_PMA_DEVAD,
8701 MDIO_PMA_REG_8727_PCS_GP, &val);
8702 val |= (3<<10);
8703 bnx2x_cl45_write(bp, phy,
8704 MDIO_PMA_DEVAD,
8705 MDIO_PMA_REG_8727_PCS_GP, val);
8706 }
8707 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8708 ((phy->speed_cap_mask &
8709 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8710 ((phy->speed_cap_mask &
8711 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8712 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8713
8714 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8715 bnx2x_cl45_write(bp, phy,
8716 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8717 bnx2x_cl45_write(bp, phy,
8718 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8719 } else {
8720 /*
8721 * Since the 8727 has only single reset pin, need to set the 10G
8722 * registers although it is default
8723 */
8724 bnx2x_cl45_write(bp, phy,
8725 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8726 0x0020);
8727 bnx2x_cl45_write(bp, phy,
8728 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8729 bnx2x_cl45_write(bp, phy,
8730 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8731 bnx2x_cl45_write(bp, phy,
8732 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8733 0x0008);
8734 }
8735
8736 /*
8737 * Set 2-wire transfer rate of SFP+ module EEPROM
8738 * to 100Khz since some DACs(direct attached cables) do
8739 * not work at 400Khz.
8740 */
8741 bnx2x_cl45_write(bp, phy,
8742 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8743 0xa001);
8744
8745 /* Set TX PreEmphasis if needed */
8746 if ((params->feature_config_flags &
8747 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8748 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8749 phy->tx_preemphasis[0],
8750 phy->tx_preemphasis[1]);
8751 bnx2x_cl45_write(bp, phy,
8752 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8753 phy->tx_preemphasis[0]);
8754
8755 bnx2x_cl45_write(bp, phy,
8756 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8757 phy->tx_preemphasis[1]);
8758 }
8759
8760 /*
8761 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8762 * power mode, if TX Laser is disabled
8763 */
8764 tx_en_mode = REG_RD(bp, params->shmem_base +
8765 offsetof(struct shmem_region,
8766 dev_info.port_hw_config[params->port].sfp_ctrl))
8767 & PORT_HW_CFG_TX_LASER_MASK;
8768
8769 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8770
8771 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8772 bnx2x_cl45_read(bp, phy,
8773 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8774 tmp2 |= 0x1000;
8775 tmp2 &= 0xFFEF;
8776 bnx2x_cl45_write(bp, phy,
8777 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8778 }
8779
8780 return 0;
8781 }
8782
8783 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8784 struct link_params *params)
8785 {
8786 struct bnx2x *bp = params->bp;
8787 u16 mod_abs, rx_alarm_status;
8788 u32 val = REG_RD(bp, params->shmem_base +
8789 offsetof(struct shmem_region, dev_info.
8790 port_feature_config[params->port].
8791 config));
8792 bnx2x_cl45_read(bp, phy,
8793 MDIO_PMA_DEVAD,
8794 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8795 if (mod_abs & (1<<8)) {
8796
8797 /* Module is absent */
8798 DP(NETIF_MSG_LINK,
8799 "MOD_ABS indication show module is absent\n");
8800 phy->media_type = ETH_PHY_NOT_PRESENT;
8801 /*
8802 * 1. Set mod_abs to detect next module
8803 * presence event
8804 * 2. Set EDC off by setting OPTXLOS signal input to low
8805 * (bit 9).
8806 * When the EDC is off it locks onto a reference clock and
8807 * avoids becoming 'lost'.
8808 */
8809 mod_abs &= ~(1<<8);
8810 if (!(phy->flags & FLAGS_NOC))
8811 mod_abs &= ~(1<<9);
8812 bnx2x_cl45_write(bp, phy,
8813 MDIO_PMA_DEVAD,
8814 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8815
8816 /*
8817 * Clear RX alarm since it stays up as long as
8818 * the mod_abs wasn't changed
8819 */
8820 bnx2x_cl45_read(bp, phy,
8821 MDIO_PMA_DEVAD,
8822 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8823
8824 } else {
8825 /* Module is present */
8826 DP(NETIF_MSG_LINK,
8827 "MOD_ABS indication show module is present\n");
8828 /*
8829 * First disable transmitter, and if the module is ok, the
8830 * module_detection will enable it
8831 * 1. Set mod_abs to detect next module absent event ( bit 8)
8832 * 2. Restore the default polarity of the OPRXLOS signal and
8833 * this signal will then correctly indicate the presence or
8834 * absence of the Rx signal. (bit 9)
8835 */
8836 mod_abs |= (1<<8);
8837 if (!(phy->flags & FLAGS_NOC))
8838 mod_abs |= (1<<9);
8839 bnx2x_cl45_write(bp, phy,
8840 MDIO_PMA_DEVAD,
8841 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8842
8843 /*
8844 * Clear RX alarm since it stays up as long as the mod_abs
8845 * wasn't changed. This is need to be done before calling the
8846 * module detection, otherwise it will clear* the link update
8847 * alarm
8848 */
8849 bnx2x_cl45_read(bp, phy,
8850 MDIO_PMA_DEVAD,
8851 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8852
8853
8854 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8855 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8856 bnx2x_sfp_set_transmitter(params, phy, 0);
8857
8858 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8859 bnx2x_sfp_module_detection(phy, params);
8860 else
8861 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8862 }
8863
8864 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8865 rx_alarm_status);
8866 /* No need to check link status in case of module plugged in/out */
8867 }
8868
8869 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8870 struct link_params *params,
8871 struct link_vars *vars)
8872
8873 {
8874 struct bnx2x *bp = params->bp;
8875 u8 link_up = 0, oc_port = params->port;
8876 u16 link_status = 0;
8877 u16 rx_alarm_status, lasi_ctrl, val1;
8878
8879 /* If PHY is not initialized, do not check link status */
8880 bnx2x_cl45_read(bp, phy,
8881 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8882 &lasi_ctrl);
8883 if (!lasi_ctrl)
8884 return 0;
8885
8886 /* Check the LASI on Rx */
8887 bnx2x_cl45_read(bp, phy,
8888 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8889 &rx_alarm_status);
8890 vars->line_speed = 0;
8891 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
8892
8893 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8894 MDIO_PMA_LASI_TXCTRL);
8895
8896 bnx2x_cl45_read(bp, phy,
8897 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8898
8899 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8900
8901 /* Clear MSG-OUT */
8902 bnx2x_cl45_read(bp, phy,
8903 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8904
8905 /*
8906 * If a module is present and there is need to check
8907 * for over current
8908 */
8909 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8910 /* Check over-current using 8727 GPIO0 input*/
8911 bnx2x_cl45_read(bp, phy,
8912 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8913 &val1);
8914
8915 if ((val1 & (1<<8)) == 0) {
8916 if (!CHIP_IS_E1x(bp))
8917 oc_port = BP_PATH(bp) + (params->port << 1);
8918 DP(NETIF_MSG_LINK,
8919 "8727 Power fault has been detected on port %d\n",
8920 oc_port);
8921 netdev_err(bp->dev, "Error: Power fault on Port %d has"
8922 " been detected and the power to "
8923 "that SFP+ module has been removed"
8924 " to prevent failure of the card."
8925 " Please remove the SFP+ module and"
8926 " restart the system to clear this"
8927 " error.\n",
8928 oc_port);
8929 /* Disable all RX_ALARMs except for mod_abs */
8930 bnx2x_cl45_write(bp, phy,
8931 MDIO_PMA_DEVAD,
8932 MDIO_PMA_LASI_RXCTRL, (1<<5));
8933
8934 bnx2x_cl45_read(bp, phy,
8935 MDIO_PMA_DEVAD,
8936 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8937 /* Wait for module_absent_event */
8938 val1 |= (1<<8);
8939 bnx2x_cl45_write(bp, phy,
8940 MDIO_PMA_DEVAD,
8941 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8942 /* Clear RX alarm */
8943 bnx2x_cl45_read(bp, phy,
8944 MDIO_PMA_DEVAD,
8945 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8946 return 0;
8947 }
8948 } /* Over current check */
8949
8950 /* When module absent bit is set, check module */
8951 if (rx_alarm_status & (1<<5)) {
8952 bnx2x_8727_handle_mod_abs(phy, params);
8953 /* Enable all mod_abs and link detection bits */
8954 bnx2x_cl45_write(bp, phy,
8955 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8956 ((1<<5) | (1<<2)));
8957 }
8958 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8959 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8960 /* If transmitter is disabled, ignore false link up indication */
8961 bnx2x_cl45_read(bp, phy,
8962 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8963 if (val1 & (1<<15)) {
8964 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8965 return 0;
8966 }
8967
8968 bnx2x_cl45_read(bp, phy,
8969 MDIO_PMA_DEVAD,
8970 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8971
8972 /*
8973 * Bits 0..2 --> speed detected,
8974 * Bits 13..15--> link is down
8975 */
8976 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8977 link_up = 1;
8978 vars->line_speed = SPEED_10000;
8979 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8980 params->port);
8981 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8982 link_up = 1;
8983 vars->line_speed = SPEED_1000;
8984 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8985 params->port);
8986 } else {
8987 link_up = 0;
8988 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8989 params->port);
8990 }
8991
8992 /* Capture 10G link fault. */
8993 if (vars->line_speed == SPEED_10000) {
8994 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8995 MDIO_PMA_LASI_TXSTAT, &val1);
8996
8997 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8998 MDIO_PMA_LASI_TXSTAT, &val1);
8999
9000 if (val1 & (1<<0)) {
9001 vars->fault_detected = 1;
9002 }
9003 }
9004
9005 if (link_up) {
9006 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9007 vars->duplex = DUPLEX_FULL;
9008 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9009 }
9010
9011 if ((DUAL_MEDIA(params)) &&
9012 (phy->req_line_speed == SPEED_1000)) {
9013 bnx2x_cl45_read(bp, phy,
9014 MDIO_PMA_DEVAD,
9015 MDIO_PMA_REG_8727_PCS_GP, &val1);
9016 /*
9017 * In case of dual-media board and 1G, power up the XAUI side,
9018 * otherwise power it down. For 10G it is done automatically
9019 */
9020 if (link_up)
9021 val1 &= ~(3<<10);
9022 else
9023 val1 |= (3<<10);
9024 bnx2x_cl45_write(bp, phy,
9025 MDIO_PMA_DEVAD,
9026 MDIO_PMA_REG_8727_PCS_GP, val1);
9027 }
9028 return link_up;
9029 }
9030
9031 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9032 struct link_params *params)
9033 {
9034 struct bnx2x *bp = params->bp;
9035
9036 /* Enable/Disable PHY transmitter output */
9037 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9038
9039 /* Disable Transmitter */
9040 bnx2x_sfp_set_transmitter(params, phy, 0);
9041 /* Clear LASI */
9042 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9043
9044 }
9045
9046 /******************************************************************/
9047 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9048 /******************************************************************/
9049 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9050 struct link_params *params)
9051 {
9052 u16 val, fw_ver1, fw_ver2, cnt;
9053 u8 port;
9054 struct bnx2x *bp = params->bp;
9055
9056 port = params->port;
9057
9058 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9059 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9060 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9061 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9062 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9063 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9064 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9065
9066 for (cnt = 0; cnt < 100; cnt++) {
9067 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9068 if (val & 1)
9069 break;
9070 udelay(5);
9071 }
9072 if (cnt == 100) {
9073 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9074 bnx2x_save_spirom_version(bp, port, 0,
9075 phy->ver_addr);
9076 return;
9077 }
9078
9079
9080 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9081 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9082 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9083 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9084 for (cnt = 0; cnt < 100; cnt++) {
9085 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9086 if (val & 1)
9087 break;
9088 udelay(5);
9089 }
9090 if (cnt == 100) {
9091 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9092 bnx2x_save_spirom_version(bp, port, 0,
9093 phy->ver_addr);
9094 return;
9095 }
9096
9097 /* lower 16 bits of the register SPI_FW_STATUS */
9098 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9099 /* upper 16 bits of register SPI_FW_STATUS */
9100 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9101
9102 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9103 phy->ver_addr);
9104 }
9105
9106 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9107 struct bnx2x_phy *phy)
9108 {
9109 u16 val;
9110
9111 /* PHYC_CTL_LED_CTL */
9112 bnx2x_cl45_read(bp, phy,
9113 MDIO_PMA_DEVAD,
9114 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9115 val &= 0xFE00;
9116 val |= 0x0092;
9117
9118 bnx2x_cl45_write(bp, phy,
9119 MDIO_PMA_DEVAD,
9120 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9121
9122 bnx2x_cl45_write(bp, phy,
9123 MDIO_PMA_DEVAD,
9124 MDIO_PMA_REG_8481_LED1_MASK,
9125 0x80);
9126
9127 bnx2x_cl45_write(bp, phy,
9128 MDIO_PMA_DEVAD,
9129 MDIO_PMA_REG_8481_LED2_MASK,
9130 0x18);
9131
9132 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9133 bnx2x_cl45_write(bp, phy,
9134 MDIO_PMA_DEVAD,
9135 MDIO_PMA_REG_8481_LED3_MASK,
9136 0x0006);
9137
9138 /* Select the closest activity blink rate to that in 10/100/1000 */
9139 bnx2x_cl45_write(bp, phy,
9140 MDIO_PMA_DEVAD,
9141 MDIO_PMA_REG_8481_LED3_BLINK,
9142 0);
9143
9144 bnx2x_cl45_read(bp, phy,
9145 MDIO_PMA_DEVAD,
9146 MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9147 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9148
9149 bnx2x_cl45_write(bp, phy,
9150 MDIO_PMA_DEVAD,
9151 MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9152
9153 /* 'Interrupt Mask' */
9154 bnx2x_cl45_write(bp, phy,
9155 MDIO_AN_DEVAD,
9156 0xFFFB, 0xFFFD);
9157 }
9158
9159 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9160 struct link_params *params,
9161 struct link_vars *vars)
9162 {
9163 struct bnx2x *bp = params->bp;
9164 u16 autoneg_val, an_1000_val, an_10_100_val;
9165 u16 tmp_req_line_speed;
9166
9167 tmp_req_line_speed = phy->req_line_speed;
9168 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9169 if (phy->req_line_speed == SPEED_10000)
9170 phy->req_line_speed = SPEED_AUTO_NEG;
9171
9172 /*
9173 * This phy uses the NIG latch mechanism since link indication
9174 * arrives through its LED4 and not via its LASI signal, so we
9175 * get steady signal instead of clear on read
9176 */
9177 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9178 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9179
9180 bnx2x_cl45_write(bp, phy,
9181 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9182
9183 bnx2x_848xx_set_led(bp, phy);
9184
9185 /* set 1000 speed advertisement */
9186 bnx2x_cl45_read(bp, phy,
9187 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9188 &an_1000_val);
9189
9190 bnx2x_ext_phy_set_pause(params, phy, vars);
9191 bnx2x_cl45_read(bp, phy,
9192 MDIO_AN_DEVAD,
9193 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9194 &an_10_100_val);
9195 bnx2x_cl45_read(bp, phy,
9196 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9197 &autoneg_val);
9198 /* Disable forced speed */
9199 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9200 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9201
9202 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9203 (phy->speed_cap_mask &
9204 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9205 (phy->req_line_speed == SPEED_1000)) {
9206 an_1000_val |= (1<<8);
9207 autoneg_val |= (1<<9 | 1<<12);
9208 if (phy->req_duplex == DUPLEX_FULL)
9209 an_1000_val |= (1<<9);
9210 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9211 } else
9212 an_1000_val &= ~((1<<8) | (1<<9));
9213
9214 bnx2x_cl45_write(bp, phy,
9215 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9216 an_1000_val);
9217
9218 /* set 100 speed advertisement */
9219 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9220 (phy->speed_cap_mask &
9221 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9222 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9223 (phy->supported &
9224 (SUPPORTED_100baseT_Half |
9225 SUPPORTED_100baseT_Full)))) {
9226 an_10_100_val |= (1<<7);
9227 /* Enable autoneg and restart autoneg for legacy speeds */
9228 autoneg_val |= (1<<9 | 1<<12);
9229
9230 if (phy->req_duplex == DUPLEX_FULL)
9231 an_10_100_val |= (1<<8);
9232 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9233 }
9234 /* set 10 speed advertisement */
9235 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9236 (phy->speed_cap_mask &
9237 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9238 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9239 (phy->supported &
9240 (SUPPORTED_10baseT_Half |
9241 SUPPORTED_10baseT_Full)))) {
9242 an_10_100_val |= (1<<5);
9243 autoneg_val |= (1<<9 | 1<<12);
9244 if (phy->req_duplex == DUPLEX_FULL)
9245 an_10_100_val |= (1<<6);
9246 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9247 }
9248
9249 /* Only 10/100 are allowed to work in FORCE mode */
9250 if ((phy->req_line_speed == SPEED_100) &&
9251 (phy->supported &
9252 (SUPPORTED_100baseT_Half |
9253 SUPPORTED_100baseT_Full))) {
9254 autoneg_val |= (1<<13);
9255 /* Enabled AUTO-MDIX when autoneg is disabled */
9256 bnx2x_cl45_write(bp, phy,
9257 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9258 (1<<15 | 1<<9 | 7<<0));
9259 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9260 }
9261 if ((phy->req_line_speed == SPEED_10) &&
9262 (phy->supported &
9263 (SUPPORTED_10baseT_Half |
9264 SUPPORTED_10baseT_Full))) {
9265 /* Enabled AUTO-MDIX when autoneg is disabled */
9266 bnx2x_cl45_write(bp, phy,
9267 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9268 (1<<15 | 1<<9 | 7<<0));
9269 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9270 }
9271
9272 bnx2x_cl45_write(bp, phy,
9273 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9274 an_10_100_val);
9275
9276 if (phy->req_duplex == DUPLEX_FULL)
9277 autoneg_val |= (1<<8);
9278
9279 /*
9280 * Always write this if this is not 84833.
9281 * For 84833, write it only when it's a forced speed.
9282 */
9283 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9284 ((autoneg_val & (1<<12)) == 0))
9285 bnx2x_cl45_write(bp, phy,
9286 MDIO_AN_DEVAD,
9287 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9288
9289 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9290 (phy->speed_cap_mask &
9291 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9292 (phy->req_line_speed == SPEED_10000)) {
9293 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9294 /* Restart autoneg for 10G*/
9295
9296 bnx2x_cl45_write(bp, phy,
9297 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9298 0x3200);
9299 } else
9300 bnx2x_cl45_write(bp, phy,
9301 MDIO_AN_DEVAD,
9302 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9303 1);
9304
9305 /* Save spirom version */
9306 bnx2x_save_848xx_spirom_version(phy, params);
9307
9308 phy->req_line_speed = tmp_req_line_speed;
9309
9310 return 0;
9311 }
9312
9313 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9314 struct link_params *params,
9315 struct link_vars *vars)
9316 {
9317 struct bnx2x *bp = params->bp;
9318 /* Restore normal power mode*/
9319 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9320 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9321
9322 /* HW reset */
9323 bnx2x_ext_phy_hw_reset(bp, params->port);
9324 bnx2x_wait_reset_complete(bp, phy, params);
9325
9326 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9327 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9328 }
9329
9330
9331 #define PHY84833_HDSHK_WAIT 300
9332 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9333 struct link_params *params,
9334 struct link_vars *vars)
9335 {
9336 u32 idx;
9337 u32 pair_swap;
9338 u16 val;
9339 u16 data;
9340 struct bnx2x *bp = params->bp;
9341 /* Do pair swap */
9342
9343 /* Check for configuration. */
9344 pair_swap = REG_RD(bp, params->shmem_base +
9345 offsetof(struct shmem_region,
9346 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9347 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9348
9349 if (pair_swap == 0)
9350 return 0;
9351
9352 data = (u16)pair_swap;
9353
9354 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9355 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9356 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9357 PHY84833_CMD_OPEN_OVERRIDE);
9358 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9359 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9360 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9361 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9362 break;
9363 msleep(1);
9364 }
9365 if (idx >= PHY84833_HDSHK_WAIT) {
9366 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9367 return -EINVAL;
9368 }
9369
9370 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9371 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9372 data);
9373 /* Issue pair swap command */
9374 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9375 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9376 PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9377 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9378 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9379 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9380 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9381 (val == PHY84833_CMD_COMPLETE_ERROR))
9382 break;
9383 msleep(1);
9384 }
9385 if ((idx >= PHY84833_HDSHK_WAIT) ||
9386 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9387 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9388 return -EINVAL;
9389 }
9390 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9391 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9392 PHY84833_CMD_CLEAR_COMPLETE);
9393 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9394 return 0;
9395 }
9396
9397
9398 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9399 u32 shmem_base_path[],
9400 u32 chip_id)
9401 {
9402 u32 reset_pin[2];
9403 u32 idx;
9404 u8 reset_gpios;
9405 if (CHIP_IS_E3(bp)) {
9406 /* Assume that these will be GPIOs, not EPIOs. */
9407 for (idx = 0; idx < 2; idx++) {
9408 /* Map config param to register bit. */
9409 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9410 offsetof(struct shmem_region,
9411 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9412 reset_pin[idx] = (reset_pin[idx] &
9413 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9414 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9415 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9416 reset_pin[idx] = (1 << reset_pin[idx]);
9417 }
9418 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9419 } else {
9420 /* E2, look from diff place of shmem. */
9421 for (idx = 0; idx < 2; idx++) {
9422 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9423 offsetof(struct shmem_region,
9424 dev_info.port_hw_config[0].default_cfg));
9425 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9426 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9427 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9428 reset_pin[idx] = (1 << reset_pin[idx]);
9429 }
9430 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9431 }
9432
9433 return reset_gpios;
9434 }
9435
9436 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9437 struct link_params *params)
9438 {
9439 struct bnx2x *bp = params->bp;
9440 u8 reset_gpios;
9441 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9442 offsetof(struct shmem2_region,
9443 other_shmem_base_addr));
9444
9445 u32 shmem_base_path[2];
9446 shmem_base_path[0] = params->shmem_base;
9447 shmem_base_path[1] = other_shmem_base_addr;
9448
9449 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9450 params->chip_id);
9451
9452 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9453 udelay(10);
9454 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9455 reset_gpios);
9456
9457 return 0;
9458 }
9459
9460 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9461 u32 shmem_base_path[],
9462 u32 chip_id)
9463 {
9464 u8 reset_gpios;
9465
9466 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9467
9468 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9469 udelay(10);
9470 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9471 msleep(800);
9472 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9473 reset_gpios);
9474
9475 return 0;
9476 }
9477
9478 #define PHY84833_CONSTANT_LATENCY 1193
9479 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9480 struct link_params *params,
9481 struct link_vars *vars)
9482 {
9483 struct bnx2x *bp = params->bp;
9484 u8 port, initialize = 1;
9485 u16 val;
9486 u16 temp;
9487 u32 actual_phy_selection, cms_enable, idx;
9488 int rc = 0;
9489
9490 msleep(1);
9491
9492 if (!(CHIP_IS_E1(bp)))
9493 port = BP_PATH(bp);
9494 else
9495 port = params->port;
9496
9497 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9498 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9499 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9500 port);
9501 } else {
9502 /* MDIO reset */
9503 bnx2x_cl45_write(bp, phy,
9504 MDIO_PMA_DEVAD,
9505 MDIO_PMA_REG_CTRL, 0x8000);
9506 /* Bring PHY out of super isolate mode */
9507 bnx2x_cl45_read(bp, phy,
9508 MDIO_CTL_DEVAD,
9509 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9510 val &= ~MDIO_84833_SUPER_ISOLATE;
9511 bnx2x_cl45_write(bp, phy,
9512 MDIO_CTL_DEVAD,
9513 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9514 }
9515
9516 bnx2x_wait_reset_complete(bp, phy, params);
9517
9518 /* Wait for GPHY to come out of reset */
9519 msleep(50);
9520
9521 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9522 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9523
9524 /*
9525 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9526 */
9527 temp = vars->line_speed;
9528 vars->line_speed = SPEED_10000;
9529 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9530 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9531 vars->line_speed = temp;
9532
9533 /* Set dual-media configuration according to configuration */
9534
9535 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9536 MDIO_CTL_REG_84823_MEDIA, &val);
9537 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9538 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9539 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9540 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9541 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9542
9543 if (CHIP_IS_E3(bp)) {
9544 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9545 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9546 } else {
9547 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9548 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9549 }
9550
9551 actual_phy_selection = bnx2x_phy_selection(params);
9552
9553 switch (actual_phy_selection) {
9554 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9555 /* Do nothing. Essentially this is like the priority copper */
9556 break;
9557 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9558 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9559 break;
9560 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9561 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9562 break;
9563 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9564 /* Do nothing here. The first PHY won't be initialized at all */
9565 break;
9566 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9567 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9568 initialize = 0;
9569 break;
9570 }
9571 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9572 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9573
9574 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9575 MDIO_CTL_REG_84823_MEDIA, val);
9576 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9577 params->multi_phy_config, val);
9578
9579 /* AutogrEEEn */
9580 if (params->feature_config_flags &
9581 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9582 /* Ensure that f/w is ready */
9583 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9584 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9585 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9586 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9587 break;
9588 usleep_range(1000, 1000);
9589 }
9590 if (idx >= PHY84833_HDSHK_WAIT) {
9591 DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9592 return -EINVAL;
9593 }
9594
9595 /* Select EEE mode */
9596 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9597 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9598 0x2);
9599
9600 /* Set Idle and Latency */
9601 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9602 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9603 PHY84833_CONSTANT_LATENCY + 1);
9604
9605 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9606 MDIO_84833_TOP_CFG_DATA3_REG,
9607 PHY84833_CONSTANT_LATENCY + 1);
9608
9609 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9610 MDIO_84833_TOP_CFG_DATA4_REG,
9611 PHY84833_CONSTANT_LATENCY);
9612
9613 /* Send EEE instruction to command register */
9614 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9615 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9616 PHY84833_DIAG_CMD_SET_EEE_MODE);
9617
9618 /* Ensure that the command has completed */
9619 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9620 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9621 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9622 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9623 (val == PHY84833_CMD_COMPLETE_ERROR))
9624 break;
9625 usleep_range(1000, 1000);
9626 }
9627 if ((idx >= PHY84833_HDSHK_WAIT) ||
9628 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9629 DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9630 return -EINVAL;
9631 }
9632
9633 /* Reset command handler */
9634 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9635 MDIO_84833_TOP_CFG_SCRATCH_REG2,
9636 PHY84833_CMD_CLEAR_COMPLETE);
9637 }
9638
9639 if (initialize)
9640 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9641 else
9642 bnx2x_save_848xx_spirom_version(phy, params);
9643 /* 84833 PHY has a better feature and doesn't need to support this. */
9644 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9645 cms_enable = REG_RD(bp, params->shmem_base +
9646 offsetof(struct shmem_region,
9647 dev_info.port_hw_config[params->port].default_cfg)) &
9648 PORT_HW_CFG_ENABLE_CMS_MASK;
9649
9650 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9651 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9652 if (cms_enable)
9653 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9654 else
9655 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9656 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9657 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9658 }
9659
9660 return rc;
9661 }
9662
9663 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9664 struct link_params *params,
9665 struct link_vars *vars)
9666 {
9667 struct bnx2x *bp = params->bp;
9668 u16 val, val1, val2;
9669 u8 link_up = 0;
9670
9671
9672 /* Check 10G-BaseT link status */
9673 /* Check PMD signal ok */
9674 bnx2x_cl45_read(bp, phy,
9675 MDIO_AN_DEVAD, 0xFFFA, &val1);
9676 bnx2x_cl45_read(bp, phy,
9677 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9678 &val2);
9679 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9680
9681 /* Check link 10G */
9682 if (val2 & (1<<11)) {
9683 vars->line_speed = SPEED_10000;
9684 vars->duplex = DUPLEX_FULL;
9685 link_up = 1;
9686 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9687 } else { /* Check Legacy speed link */
9688 u16 legacy_status, legacy_speed;
9689
9690 /* Enable expansion register 0x42 (Operation mode status) */
9691 bnx2x_cl45_write(bp, phy,
9692 MDIO_AN_DEVAD,
9693 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9694
9695 /* Get legacy speed operation status */
9696 bnx2x_cl45_read(bp, phy,
9697 MDIO_AN_DEVAD,
9698 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9699 &legacy_status);
9700
9701 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
9702 legacy_status);
9703 link_up = ((legacy_status & (1<<11)) == (1<<11));
9704 if (link_up) {
9705 legacy_speed = (legacy_status & (3<<9));
9706 if (legacy_speed == (0<<9))
9707 vars->line_speed = SPEED_10;
9708 else if (legacy_speed == (1<<9))
9709 vars->line_speed = SPEED_100;
9710 else if (legacy_speed == (2<<9))
9711 vars->line_speed = SPEED_1000;
9712 else /* Should not happen */
9713 vars->line_speed = 0;
9714
9715 if (legacy_status & (1<<8))
9716 vars->duplex = DUPLEX_FULL;
9717 else
9718 vars->duplex = DUPLEX_HALF;
9719
9720 DP(NETIF_MSG_LINK,
9721 "Link is up in %dMbps, is_duplex_full= %d\n",
9722 vars->line_speed,
9723 (vars->duplex == DUPLEX_FULL));
9724 /* Check legacy speed AN resolution */
9725 bnx2x_cl45_read(bp, phy,
9726 MDIO_AN_DEVAD,
9727 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9728 &val);
9729 if (val & (1<<5))
9730 vars->link_status |=
9731 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9732 bnx2x_cl45_read(bp, phy,
9733 MDIO_AN_DEVAD,
9734 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9735 &val);
9736 if ((val & (1<<0)) == 0)
9737 vars->link_status |=
9738 LINK_STATUS_PARALLEL_DETECTION_USED;
9739 }
9740 }
9741 if (link_up) {
9742 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9743 vars->line_speed);
9744 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9745 }
9746
9747 return link_up;
9748 }
9749
9750
9751 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9752 {
9753 int status = 0;
9754 u32 spirom_ver;
9755 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9756 status = bnx2x_format_ver(spirom_ver, str, len);
9757 return status;
9758 }
9759
9760 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9761 struct link_params *params)
9762 {
9763 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9764 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9765 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9766 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9767 }
9768
9769 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9770 struct link_params *params)
9771 {
9772 bnx2x_cl45_write(params->bp, phy,
9773 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9774 bnx2x_cl45_write(params->bp, phy,
9775 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9776 }
9777
9778 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9779 struct link_params *params)
9780 {
9781 struct bnx2x *bp = params->bp;
9782 u8 port;
9783 u16 val16;
9784
9785 if (!(CHIP_IS_E1(bp)))
9786 port = BP_PATH(bp);
9787 else
9788 port = params->port;
9789
9790 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9791 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9792 MISC_REGISTERS_GPIO_OUTPUT_LOW,
9793 port);
9794 } else {
9795 bnx2x_cl45_read(bp, phy,
9796 MDIO_CTL_DEVAD,
9797 0x400f, &val16);
9798 bnx2x_cl45_write(bp, phy,
9799 MDIO_PMA_DEVAD,
9800 MDIO_PMA_REG_CTRL, 0x800);
9801 }
9802 }
9803
9804 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9805 struct link_params *params, u8 mode)
9806 {
9807 struct bnx2x *bp = params->bp;
9808 u16 val;
9809 u8 port;
9810
9811 if (!(CHIP_IS_E1(bp)))
9812 port = BP_PATH(bp);
9813 else
9814 port = params->port;
9815
9816 switch (mode) {
9817 case LED_MODE_OFF:
9818
9819 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9820
9821 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9822 SHARED_HW_CFG_LED_EXTPHY1) {
9823
9824 /* Set LED masks */
9825 bnx2x_cl45_write(bp, phy,
9826 MDIO_PMA_DEVAD,
9827 MDIO_PMA_REG_8481_LED1_MASK,
9828 0x0);
9829
9830 bnx2x_cl45_write(bp, phy,
9831 MDIO_PMA_DEVAD,
9832 MDIO_PMA_REG_8481_LED2_MASK,
9833 0x0);
9834
9835 bnx2x_cl45_write(bp, phy,
9836 MDIO_PMA_DEVAD,
9837 MDIO_PMA_REG_8481_LED3_MASK,
9838 0x0);
9839
9840 bnx2x_cl45_write(bp, phy,
9841 MDIO_PMA_DEVAD,
9842 MDIO_PMA_REG_8481_LED5_MASK,
9843 0x0);
9844
9845 } else {
9846 bnx2x_cl45_write(bp, phy,
9847 MDIO_PMA_DEVAD,
9848 MDIO_PMA_REG_8481_LED1_MASK,
9849 0x0);
9850 }
9851 break;
9852 case LED_MODE_FRONT_PANEL_OFF:
9853
9854 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9855 port);
9856
9857 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9858 SHARED_HW_CFG_LED_EXTPHY1) {
9859
9860 /* Set LED masks */
9861 bnx2x_cl45_write(bp, phy,
9862 MDIO_PMA_DEVAD,
9863 MDIO_PMA_REG_8481_LED1_MASK,
9864 0x0);
9865
9866 bnx2x_cl45_write(bp, phy,
9867 MDIO_PMA_DEVAD,
9868 MDIO_PMA_REG_8481_LED2_MASK,
9869 0x0);
9870
9871 bnx2x_cl45_write(bp, phy,
9872 MDIO_PMA_DEVAD,
9873 MDIO_PMA_REG_8481_LED3_MASK,
9874 0x0);
9875
9876 bnx2x_cl45_write(bp, phy,
9877 MDIO_PMA_DEVAD,
9878 MDIO_PMA_REG_8481_LED5_MASK,
9879 0x20);
9880
9881 } else {
9882 bnx2x_cl45_write(bp, phy,
9883 MDIO_PMA_DEVAD,
9884 MDIO_PMA_REG_8481_LED1_MASK,
9885 0x0);
9886 }
9887 break;
9888 case LED_MODE_ON:
9889
9890 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9891
9892 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9893 SHARED_HW_CFG_LED_EXTPHY1) {
9894 /* Set control reg */
9895 bnx2x_cl45_read(bp, phy,
9896 MDIO_PMA_DEVAD,
9897 MDIO_PMA_REG_8481_LINK_SIGNAL,
9898 &val);
9899 val &= 0x8000;
9900 val |= 0x2492;
9901
9902 bnx2x_cl45_write(bp, phy,
9903 MDIO_PMA_DEVAD,
9904 MDIO_PMA_REG_8481_LINK_SIGNAL,
9905 val);
9906
9907 /* Set LED masks */
9908 bnx2x_cl45_write(bp, phy,
9909 MDIO_PMA_DEVAD,
9910 MDIO_PMA_REG_8481_LED1_MASK,
9911 0x0);
9912
9913 bnx2x_cl45_write(bp, phy,
9914 MDIO_PMA_DEVAD,
9915 MDIO_PMA_REG_8481_LED2_MASK,
9916 0x20);
9917
9918 bnx2x_cl45_write(bp, phy,
9919 MDIO_PMA_DEVAD,
9920 MDIO_PMA_REG_8481_LED3_MASK,
9921 0x20);
9922
9923 bnx2x_cl45_write(bp, phy,
9924 MDIO_PMA_DEVAD,
9925 MDIO_PMA_REG_8481_LED5_MASK,
9926 0x0);
9927 } else {
9928 bnx2x_cl45_write(bp, phy,
9929 MDIO_PMA_DEVAD,
9930 MDIO_PMA_REG_8481_LED1_MASK,
9931 0x20);
9932 }
9933 break;
9934
9935 case LED_MODE_OPER:
9936
9937 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9938
9939 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9940 SHARED_HW_CFG_LED_EXTPHY1) {
9941
9942 /* Set control reg */
9943 bnx2x_cl45_read(bp, phy,
9944 MDIO_PMA_DEVAD,
9945 MDIO_PMA_REG_8481_LINK_SIGNAL,
9946 &val);
9947
9948 if (!((val &
9949 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9950 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9951 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9952 bnx2x_cl45_write(bp, phy,
9953 MDIO_PMA_DEVAD,
9954 MDIO_PMA_REG_8481_LINK_SIGNAL,
9955 0xa492);
9956 }
9957
9958 /* Set LED masks */
9959 bnx2x_cl45_write(bp, phy,
9960 MDIO_PMA_DEVAD,
9961 MDIO_PMA_REG_8481_LED1_MASK,
9962 0x10);
9963
9964 bnx2x_cl45_write(bp, phy,
9965 MDIO_PMA_DEVAD,
9966 MDIO_PMA_REG_8481_LED2_MASK,
9967 0x80);
9968
9969 bnx2x_cl45_write(bp, phy,
9970 MDIO_PMA_DEVAD,
9971 MDIO_PMA_REG_8481_LED3_MASK,
9972 0x98);
9973
9974 bnx2x_cl45_write(bp, phy,
9975 MDIO_PMA_DEVAD,
9976 MDIO_PMA_REG_8481_LED5_MASK,
9977 0x40);
9978
9979 } else {
9980 bnx2x_cl45_write(bp, phy,
9981 MDIO_PMA_DEVAD,
9982 MDIO_PMA_REG_8481_LED1_MASK,
9983 0x80);
9984
9985 /* Tell LED3 to blink on source */
9986 bnx2x_cl45_read(bp, phy,
9987 MDIO_PMA_DEVAD,
9988 MDIO_PMA_REG_8481_LINK_SIGNAL,
9989 &val);
9990 val &= ~(7<<6);
9991 val |= (1<<6); /* A83B[8:6]= 1 */
9992 bnx2x_cl45_write(bp, phy,
9993 MDIO_PMA_DEVAD,
9994 MDIO_PMA_REG_8481_LINK_SIGNAL,
9995 val);
9996 }
9997 break;
9998 }
9999
10000 /*
10001 * This is a workaround for E3+84833 until autoneg
10002 * restart is fixed in f/w
10003 */
10004 if (CHIP_IS_E3(bp)) {
10005 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10006 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10007 }
10008 }
10009
10010 /******************************************************************/
10011 /* 54618SE PHY SECTION */
10012 /******************************************************************/
10013 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10014 struct link_params *params,
10015 struct link_vars *vars)
10016 {
10017 struct bnx2x *bp = params->bp;
10018 u8 port;
10019 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10020 u32 cfg_pin;
10021
10022 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10023 usleep_range(1000, 1000);
10024
10025 /* This works with E3 only, no need to check the chip
10026 before determining the port. */
10027 port = params->port;
10028
10029 cfg_pin = (REG_RD(bp, params->shmem_base +
10030 offsetof(struct shmem_region,
10031 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10032 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10033 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10034
10035 /* Drive pin high to bring the GPHY out of reset. */
10036 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10037
10038 /* wait for GPHY to reset */
10039 msleep(50);
10040
10041 /* reset phy */
10042 bnx2x_cl22_write(bp, phy,
10043 MDIO_PMA_REG_CTRL, 0x8000);
10044 bnx2x_wait_reset_complete(bp, phy, params);
10045
10046 /*wait for GPHY to reset */
10047 msleep(50);
10048
10049 /* Configure LED4: set to INTR (0x6). */
10050 /* Accessing shadow register 0xe. */
10051 bnx2x_cl22_write(bp, phy,
10052 MDIO_REG_GPHY_SHADOW,
10053 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10054 bnx2x_cl22_read(bp, phy,
10055 MDIO_REG_GPHY_SHADOW,
10056 &temp);
10057 temp &= ~(0xf << 4);
10058 temp |= (0x6 << 4);
10059 bnx2x_cl22_write(bp, phy,
10060 MDIO_REG_GPHY_SHADOW,
10061 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10062 /* Configure INTR based on link status change. */
10063 bnx2x_cl22_write(bp, phy,
10064 MDIO_REG_INTR_MASK,
10065 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10066
10067 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10068 bnx2x_cl22_write(bp, phy,
10069 MDIO_REG_GPHY_SHADOW,
10070 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10071 bnx2x_cl22_read(bp, phy,
10072 MDIO_REG_GPHY_SHADOW,
10073 &temp);
10074 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10075 bnx2x_cl22_write(bp, phy,
10076 MDIO_REG_GPHY_SHADOW,
10077 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10078
10079 /* Set up fc */
10080 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10081 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10082 fc_val = 0;
10083 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10084 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10085 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10086
10087 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10088 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10089 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10090
10091 /* read all advertisement */
10092 bnx2x_cl22_read(bp, phy,
10093 0x09,
10094 &an_1000_val);
10095
10096 bnx2x_cl22_read(bp, phy,
10097 0x04,
10098 &an_10_100_val);
10099
10100 bnx2x_cl22_read(bp, phy,
10101 MDIO_PMA_REG_CTRL,
10102 &autoneg_val);
10103
10104 /* Disable forced speed */
10105 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10106 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10107 (1<<11));
10108
10109 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10110 (phy->speed_cap_mask &
10111 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10112 (phy->req_line_speed == SPEED_1000)) {
10113 an_1000_val |= (1<<8);
10114 autoneg_val |= (1<<9 | 1<<12);
10115 if (phy->req_duplex == DUPLEX_FULL)
10116 an_1000_val |= (1<<9);
10117 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10118 } else
10119 an_1000_val &= ~((1<<8) | (1<<9));
10120
10121 bnx2x_cl22_write(bp, phy,
10122 0x09,
10123 an_1000_val);
10124 bnx2x_cl22_read(bp, phy,
10125 0x09,
10126 &an_1000_val);
10127
10128 /* set 100 speed advertisement */
10129 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10130 (phy->speed_cap_mask &
10131 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10132 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10133 an_10_100_val |= (1<<7);
10134 /* Enable autoneg and restart autoneg for legacy speeds */
10135 autoneg_val |= (1<<9 | 1<<12);
10136
10137 if (phy->req_duplex == DUPLEX_FULL)
10138 an_10_100_val |= (1<<8);
10139 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10140 }
10141
10142 /* set 10 speed advertisement */
10143 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10144 (phy->speed_cap_mask &
10145 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10146 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10147 an_10_100_val |= (1<<5);
10148 autoneg_val |= (1<<9 | 1<<12);
10149 if (phy->req_duplex == DUPLEX_FULL)
10150 an_10_100_val |= (1<<6);
10151 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10152 }
10153
10154 /* Only 10/100 are allowed to work in FORCE mode */
10155 if (phy->req_line_speed == SPEED_100) {
10156 autoneg_val |= (1<<13);
10157 /* Enabled AUTO-MDIX when autoneg is disabled */
10158 bnx2x_cl22_write(bp, phy,
10159 0x18,
10160 (1<<15 | 1<<9 | 7<<0));
10161 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10162 }
10163 if (phy->req_line_speed == SPEED_10) {
10164 /* Enabled AUTO-MDIX when autoneg is disabled */
10165 bnx2x_cl22_write(bp, phy,
10166 0x18,
10167 (1<<15 | 1<<9 | 7<<0));
10168 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10169 }
10170
10171 /* Check if we should turn on Auto-GrEEEn */
10172 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10173 if (temp == MDIO_REG_GPHY_ID_54618SE) {
10174 if (params->feature_config_flags &
10175 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10176 temp = 6;
10177 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10178 } else {
10179 temp = 0;
10180 DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10181 }
10182 bnx2x_cl22_write(bp, phy,
10183 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10184 bnx2x_cl22_write(bp, phy,
10185 MDIO_REG_GPHY_CL45_DATA_REG,
10186 MDIO_REG_GPHY_EEE_ADV);
10187 bnx2x_cl22_write(bp, phy,
10188 MDIO_REG_GPHY_CL45_ADDR_REG,
10189 (0x1 << 14) | MDIO_AN_DEVAD);
10190 bnx2x_cl22_write(bp, phy,
10191 MDIO_REG_GPHY_CL45_DATA_REG,
10192 temp);
10193 }
10194
10195 bnx2x_cl22_write(bp, phy,
10196 0x04,
10197 an_10_100_val | fc_val);
10198
10199 if (phy->req_duplex == DUPLEX_FULL)
10200 autoneg_val |= (1<<8);
10201
10202 bnx2x_cl22_write(bp, phy,
10203 MDIO_PMA_REG_CTRL, autoneg_val);
10204
10205 return 0;
10206 }
10207
10208 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10209 struct link_params *params, u8 mode)
10210 {
10211 struct bnx2x *bp = params->bp;
10212 DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10213 switch (mode) {
10214 case LED_MODE_FRONT_PANEL_OFF:
10215 case LED_MODE_OFF:
10216 case LED_MODE_OPER:
10217 case LED_MODE_ON:
10218 default:
10219 break;
10220 }
10221 return;
10222 }
10223
10224 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10225 struct link_params *params)
10226 {
10227 struct bnx2x *bp = params->bp;
10228 u32 cfg_pin;
10229 u8 port;
10230
10231 /*
10232 * In case of no EPIO routed to reset the GPHY, put it
10233 * in low power mode.
10234 */
10235 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10236 /*
10237 * This works with E3 only, no need to check the chip
10238 * before determining the port.
10239 */
10240 port = params->port;
10241 cfg_pin = (REG_RD(bp, params->shmem_base +
10242 offsetof(struct shmem_region,
10243 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10244 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10245 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10246
10247 /* Drive pin low to put GPHY in reset. */
10248 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10249 }
10250
10251 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10252 struct link_params *params,
10253 struct link_vars *vars)
10254 {
10255 struct bnx2x *bp = params->bp;
10256 u16 val;
10257 u8 link_up = 0;
10258 u16 legacy_status, legacy_speed;
10259
10260 /* Get speed operation status */
10261 bnx2x_cl22_read(bp, phy,
10262 0x19,
10263 &legacy_status);
10264 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10265
10266 /* Read status to clear the PHY interrupt. */
10267 bnx2x_cl22_read(bp, phy,
10268 MDIO_REG_INTR_STATUS,
10269 &val);
10270
10271 link_up = ((legacy_status & (1<<2)) == (1<<2));
10272
10273 if (link_up) {
10274 legacy_speed = (legacy_status & (7<<8));
10275 if (legacy_speed == (7<<8)) {
10276 vars->line_speed = SPEED_1000;
10277 vars->duplex = DUPLEX_FULL;
10278 } else if (legacy_speed == (6<<8)) {
10279 vars->line_speed = SPEED_1000;
10280 vars->duplex = DUPLEX_HALF;
10281 } else if (legacy_speed == (5<<8)) {
10282 vars->line_speed = SPEED_100;
10283 vars->duplex = DUPLEX_FULL;
10284 }
10285 /* Omitting 100Base-T4 for now */
10286 else if (legacy_speed == (3<<8)) {
10287 vars->line_speed = SPEED_100;
10288 vars->duplex = DUPLEX_HALF;
10289 } else if (legacy_speed == (2<<8)) {
10290 vars->line_speed = SPEED_10;
10291 vars->duplex = DUPLEX_FULL;
10292 } else if (legacy_speed == (1<<8)) {
10293 vars->line_speed = SPEED_10;
10294 vars->duplex = DUPLEX_HALF;
10295 } else /* Should not happen */
10296 vars->line_speed = 0;
10297
10298 DP(NETIF_MSG_LINK,
10299 "Link is up in %dMbps, is_duplex_full= %d\n",
10300 vars->line_speed,
10301 (vars->duplex == DUPLEX_FULL));
10302
10303 /* Check legacy speed AN resolution */
10304 bnx2x_cl22_read(bp, phy,
10305 0x01,
10306 &val);
10307 if (val & (1<<5))
10308 vars->link_status |=
10309 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10310 bnx2x_cl22_read(bp, phy,
10311 0x06,
10312 &val);
10313 if ((val & (1<<0)) == 0)
10314 vars->link_status |=
10315 LINK_STATUS_PARALLEL_DETECTION_USED;
10316
10317 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10318 vars->line_speed);
10319
10320 /* Report whether EEE is resolved. */
10321 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10322 if (val == MDIO_REG_GPHY_ID_54618SE) {
10323 if (vars->link_status &
10324 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10325 val = 0;
10326 else {
10327 bnx2x_cl22_write(bp, phy,
10328 MDIO_REG_GPHY_CL45_ADDR_REG,
10329 MDIO_AN_DEVAD);
10330 bnx2x_cl22_write(bp, phy,
10331 MDIO_REG_GPHY_CL45_DATA_REG,
10332 MDIO_REG_GPHY_EEE_RESOLVED);
10333 bnx2x_cl22_write(bp, phy,
10334 MDIO_REG_GPHY_CL45_ADDR_REG,
10335 (0x1 << 14) | MDIO_AN_DEVAD);
10336 bnx2x_cl22_read(bp, phy,
10337 MDIO_REG_GPHY_CL45_DATA_REG,
10338 &val);
10339 }
10340 DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10341 }
10342
10343 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10344 }
10345 return link_up;
10346 }
10347
10348 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10349 struct link_params *params)
10350 {
10351 struct bnx2x *bp = params->bp;
10352 u16 val;
10353 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10354
10355 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10356
10357 /* Enable master/slave manual mmode and set to master */
10358 /* mii write 9 [bits set 11 12] */
10359 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10360
10361 /* forced 1G and disable autoneg */
10362 /* set val [mii read 0] */
10363 /* set val [expr $val & [bits clear 6 12 13]] */
10364 /* set val [expr $val | [bits set 6 8]] */
10365 /* mii write 0 $val */
10366 bnx2x_cl22_read(bp, phy, 0x00, &val);
10367 val &= ~((1<<6) | (1<<12) | (1<<13));
10368 val |= (1<<6) | (1<<8);
10369 bnx2x_cl22_write(bp, phy, 0x00, val);
10370
10371 /* Set external loopback and Tx using 6dB coding */
10372 /* mii write 0x18 7 */
10373 /* set val [mii read 0x18] */
10374 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10375 bnx2x_cl22_write(bp, phy, 0x18, 7);
10376 bnx2x_cl22_read(bp, phy, 0x18, &val);
10377 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10378
10379 /* This register opens the gate for the UMAC despite its name */
10380 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10381
10382 /*
10383 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10384 * length used by the MAC receive logic to check frames.
10385 */
10386 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10387 }
10388
10389 /******************************************************************/
10390 /* SFX7101 PHY SECTION */
10391 /******************************************************************/
10392 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10393 struct link_params *params)
10394 {
10395 struct bnx2x *bp = params->bp;
10396 /* SFX7101_XGXS_TEST1 */
10397 bnx2x_cl45_write(bp, phy,
10398 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10399 }
10400
10401 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10402 struct link_params *params,
10403 struct link_vars *vars)
10404 {
10405 u16 fw_ver1, fw_ver2, val;
10406 struct bnx2x *bp = params->bp;
10407 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10408
10409 /* Restore normal power mode*/
10410 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10411 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10412 /* HW reset */
10413 bnx2x_ext_phy_hw_reset(bp, params->port);
10414 bnx2x_wait_reset_complete(bp, phy, params);
10415
10416 bnx2x_cl45_write(bp, phy,
10417 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10418 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10419 bnx2x_cl45_write(bp, phy,
10420 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10421
10422 bnx2x_ext_phy_set_pause(params, phy, vars);
10423 /* Restart autoneg */
10424 bnx2x_cl45_read(bp, phy,
10425 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10426 val |= 0x200;
10427 bnx2x_cl45_write(bp, phy,
10428 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10429
10430 /* Save spirom version */
10431 bnx2x_cl45_read(bp, phy,
10432 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10433
10434 bnx2x_cl45_read(bp, phy,
10435 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10436 bnx2x_save_spirom_version(bp, params->port,
10437 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10438 return 0;
10439 }
10440
10441 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10442 struct link_params *params,
10443 struct link_vars *vars)
10444 {
10445 struct bnx2x *bp = params->bp;
10446 u8 link_up;
10447 u16 val1, val2;
10448 bnx2x_cl45_read(bp, phy,
10449 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10450 bnx2x_cl45_read(bp, phy,
10451 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10452 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10453 val2, val1);
10454 bnx2x_cl45_read(bp, phy,
10455 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10456 bnx2x_cl45_read(bp, phy,
10457 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10458 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10459 val2, val1);
10460 link_up = ((val1 & 4) == 4);
10461 /* if link is up print the AN outcome of the SFX7101 PHY */
10462 if (link_up) {
10463 bnx2x_cl45_read(bp, phy,
10464 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10465 &val2);
10466 vars->line_speed = SPEED_10000;
10467 vars->duplex = DUPLEX_FULL;
10468 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10469 val2, (val2 & (1<<14)));
10470 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10471 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10472 }
10473 return link_up;
10474 }
10475
10476 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10477 {
10478 if (*len < 5)
10479 return -EINVAL;
10480 str[0] = (spirom_ver & 0xFF);
10481 str[1] = (spirom_ver & 0xFF00) >> 8;
10482 str[2] = (spirom_ver & 0xFF0000) >> 16;
10483 str[3] = (spirom_ver & 0xFF000000) >> 24;
10484 str[4] = '\0';
10485 *len -= 5;
10486 return 0;
10487 }
10488
10489 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10490 {
10491 u16 val, cnt;
10492
10493 bnx2x_cl45_read(bp, phy,
10494 MDIO_PMA_DEVAD,
10495 MDIO_PMA_REG_7101_RESET, &val);
10496
10497 for (cnt = 0; cnt < 10; cnt++) {
10498 msleep(50);
10499 /* Writes a self-clearing reset */
10500 bnx2x_cl45_write(bp, phy,
10501 MDIO_PMA_DEVAD,
10502 MDIO_PMA_REG_7101_RESET,
10503 (val | (1<<15)));
10504 /* Wait for clear */
10505 bnx2x_cl45_read(bp, phy,
10506 MDIO_PMA_DEVAD,
10507 MDIO_PMA_REG_7101_RESET, &val);
10508
10509 if ((val & (1<<15)) == 0)
10510 break;
10511 }
10512 }
10513
10514 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10515 struct link_params *params) {
10516 /* Low power mode is controlled by GPIO 2 */
10517 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10518 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10519 /* The PHY reset is controlled by GPIO 1 */
10520 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10521 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10522 }
10523
10524 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10525 struct link_params *params, u8 mode)
10526 {
10527 u16 val = 0;
10528 struct bnx2x *bp = params->bp;
10529 switch (mode) {
10530 case LED_MODE_FRONT_PANEL_OFF:
10531 case LED_MODE_OFF:
10532 val = 2;
10533 break;
10534 case LED_MODE_ON:
10535 val = 1;
10536 break;
10537 case LED_MODE_OPER:
10538 val = 0;
10539 break;
10540 }
10541 bnx2x_cl45_write(bp, phy,
10542 MDIO_PMA_DEVAD,
10543 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10544 val);
10545 }
10546
10547 /******************************************************************/
10548 /* STATIC PHY DECLARATION */
10549 /******************************************************************/
10550
10551 static struct bnx2x_phy phy_null = {
10552 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10553 .addr = 0,
10554 .def_md_devad = 0,
10555 .flags = FLAGS_INIT_XGXS_FIRST,
10556 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10557 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10558 .mdio_ctrl = 0,
10559 .supported = 0,
10560 .media_type = ETH_PHY_NOT_PRESENT,
10561 .ver_addr = 0,
10562 .req_flow_ctrl = 0,
10563 .req_line_speed = 0,
10564 .speed_cap_mask = 0,
10565 .req_duplex = 0,
10566 .rsrv = 0,
10567 .config_init = (config_init_t)NULL,
10568 .read_status = (read_status_t)NULL,
10569 .link_reset = (link_reset_t)NULL,
10570 .config_loopback = (config_loopback_t)NULL,
10571 .format_fw_ver = (format_fw_ver_t)NULL,
10572 .hw_reset = (hw_reset_t)NULL,
10573 .set_link_led = (set_link_led_t)NULL,
10574 .phy_specific_func = (phy_specific_func_t)NULL
10575 };
10576
10577 static struct bnx2x_phy phy_serdes = {
10578 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10579 .addr = 0xff,
10580 .def_md_devad = 0,
10581 .flags = 0,
10582 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10583 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10584 .mdio_ctrl = 0,
10585 .supported = (SUPPORTED_10baseT_Half |
10586 SUPPORTED_10baseT_Full |
10587 SUPPORTED_100baseT_Half |
10588 SUPPORTED_100baseT_Full |
10589 SUPPORTED_1000baseT_Full |
10590 SUPPORTED_2500baseX_Full |
10591 SUPPORTED_TP |
10592 SUPPORTED_Autoneg |
10593 SUPPORTED_Pause |
10594 SUPPORTED_Asym_Pause),
10595 .media_type = ETH_PHY_BASE_T,
10596 .ver_addr = 0,
10597 .req_flow_ctrl = 0,
10598 .req_line_speed = 0,
10599 .speed_cap_mask = 0,
10600 .req_duplex = 0,
10601 .rsrv = 0,
10602 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10603 .read_status = (read_status_t)bnx2x_link_settings_status,
10604 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10605 .config_loopback = (config_loopback_t)NULL,
10606 .format_fw_ver = (format_fw_ver_t)NULL,
10607 .hw_reset = (hw_reset_t)NULL,
10608 .set_link_led = (set_link_led_t)NULL,
10609 .phy_specific_func = (phy_specific_func_t)NULL
10610 };
10611
10612 static struct bnx2x_phy phy_xgxs = {
10613 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10614 .addr = 0xff,
10615 .def_md_devad = 0,
10616 .flags = 0,
10617 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10618 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10619 .mdio_ctrl = 0,
10620 .supported = (SUPPORTED_10baseT_Half |
10621 SUPPORTED_10baseT_Full |
10622 SUPPORTED_100baseT_Half |
10623 SUPPORTED_100baseT_Full |
10624 SUPPORTED_1000baseT_Full |
10625 SUPPORTED_2500baseX_Full |
10626 SUPPORTED_10000baseT_Full |
10627 SUPPORTED_FIBRE |
10628 SUPPORTED_Autoneg |
10629 SUPPORTED_Pause |
10630 SUPPORTED_Asym_Pause),
10631 .media_type = ETH_PHY_CX4,
10632 .ver_addr = 0,
10633 .req_flow_ctrl = 0,
10634 .req_line_speed = 0,
10635 .speed_cap_mask = 0,
10636 .req_duplex = 0,
10637 .rsrv = 0,
10638 .config_init = (config_init_t)bnx2x_xgxs_config_init,
10639 .read_status = (read_status_t)bnx2x_link_settings_status,
10640 .link_reset = (link_reset_t)bnx2x_int_link_reset,
10641 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10642 .format_fw_ver = (format_fw_ver_t)NULL,
10643 .hw_reset = (hw_reset_t)NULL,
10644 .set_link_led = (set_link_led_t)NULL,
10645 .phy_specific_func = (phy_specific_func_t)NULL
10646 };
10647 static struct bnx2x_phy phy_warpcore = {
10648 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10649 .addr = 0xff,
10650 .def_md_devad = 0,
10651 .flags = FLAGS_HW_LOCK_REQUIRED,
10652 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10653 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10654 .mdio_ctrl = 0,
10655 .supported = (SUPPORTED_10baseT_Half |
10656 SUPPORTED_10baseT_Full |
10657 SUPPORTED_100baseT_Half |
10658 SUPPORTED_100baseT_Full |
10659 SUPPORTED_1000baseT_Full |
10660 SUPPORTED_10000baseT_Full |
10661 SUPPORTED_20000baseKR2_Full |
10662 SUPPORTED_20000baseMLD2_Full |
10663 SUPPORTED_FIBRE |
10664 SUPPORTED_Autoneg |
10665 SUPPORTED_Pause |
10666 SUPPORTED_Asym_Pause),
10667 .media_type = ETH_PHY_UNSPECIFIED,
10668 .ver_addr = 0,
10669 .req_flow_ctrl = 0,
10670 .req_line_speed = 0,
10671 .speed_cap_mask = 0,
10672 /* req_duplex = */0,
10673 /* rsrv = */0,
10674 .config_init = (config_init_t)bnx2x_warpcore_config_init,
10675 .read_status = (read_status_t)bnx2x_warpcore_read_status,
10676 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
10677 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10678 .format_fw_ver = (format_fw_ver_t)NULL,
10679 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
10680 .set_link_led = (set_link_led_t)NULL,
10681 .phy_specific_func = (phy_specific_func_t)NULL
10682 };
10683
10684
10685 static struct bnx2x_phy phy_7101 = {
10686 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10687 .addr = 0xff,
10688 .def_md_devad = 0,
10689 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10690 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10691 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10692 .mdio_ctrl = 0,
10693 .supported = (SUPPORTED_10000baseT_Full |
10694 SUPPORTED_TP |
10695 SUPPORTED_Autoneg |
10696 SUPPORTED_Pause |
10697 SUPPORTED_Asym_Pause),
10698 .media_type = ETH_PHY_BASE_T,
10699 .ver_addr = 0,
10700 .req_flow_ctrl = 0,
10701 .req_line_speed = 0,
10702 .speed_cap_mask = 0,
10703 .req_duplex = 0,
10704 .rsrv = 0,
10705 .config_init = (config_init_t)bnx2x_7101_config_init,
10706 .read_status = (read_status_t)bnx2x_7101_read_status,
10707 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10708 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10709 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
10710 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
10711 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
10712 .phy_specific_func = (phy_specific_func_t)NULL
10713 };
10714 static struct bnx2x_phy phy_8073 = {
10715 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10716 .addr = 0xff,
10717 .def_md_devad = 0,
10718 .flags = FLAGS_HW_LOCK_REQUIRED,
10719 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10720 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10721 .mdio_ctrl = 0,
10722 .supported = (SUPPORTED_10000baseT_Full |
10723 SUPPORTED_2500baseX_Full |
10724 SUPPORTED_1000baseT_Full |
10725 SUPPORTED_FIBRE |
10726 SUPPORTED_Autoneg |
10727 SUPPORTED_Pause |
10728 SUPPORTED_Asym_Pause),
10729 .media_type = ETH_PHY_KR,
10730 .ver_addr = 0,
10731 .req_flow_ctrl = 0,
10732 .req_line_speed = 0,
10733 .speed_cap_mask = 0,
10734 .req_duplex = 0,
10735 .rsrv = 0,
10736 .config_init = (config_init_t)bnx2x_8073_config_init,
10737 .read_status = (read_status_t)bnx2x_8073_read_status,
10738 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
10739 .config_loopback = (config_loopback_t)NULL,
10740 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10741 .hw_reset = (hw_reset_t)NULL,
10742 .set_link_led = (set_link_led_t)NULL,
10743 .phy_specific_func = (phy_specific_func_t)NULL
10744 };
10745 static struct bnx2x_phy phy_8705 = {
10746 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10747 .addr = 0xff,
10748 .def_md_devad = 0,
10749 .flags = FLAGS_INIT_XGXS_FIRST,
10750 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10751 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10752 .mdio_ctrl = 0,
10753 .supported = (SUPPORTED_10000baseT_Full |
10754 SUPPORTED_FIBRE |
10755 SUPPORTED_Pause |
10756 SUPPORTED_Asym_Pause),
10757 .media_type = ETH_PHY_XFP_FIBER,
10758 .ver_addr = 0,
10759 .req_flow_ctrl = 0,
10760 .req_line_speed = 0,
10761 .speed_cap_mask = 0,
10762 .req_duplex = 0,
10763 .rsrv = 0,
10764 .config_init = (config_init_t)bnx2x_8705_config_init,
10765 .read_status = (read_status_t)bnx2x_8705_read_status,
10766 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10767 .config_loopback = (config_loopback_t)NULL,
10768 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
10769 .hw_reset = (hw_reset_t)NULL,
10770 .set_link_led = (set_link_led_t)NULL,
10771 .phy_specific_func = (phy_specific_func_t)NULL
10772 };
10773 static struct bnx2x_phy phy_8706 = {
10774 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10775 .addr = 0xff,
10776 .def_md_devad = 0,
10777 .flags = FLAGS_INIT_XGXS_FIRST,
10778 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10779 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10780 .mdio_ctrl = 0,
10781 .supported = (SUPPORTED_10000baseT_Full |
10782 SUPPORTED_1000baseT_Full |
10783 SUPPORTED_FIBRE |
10784 SUPPORTED_Pause |
10785 SUPPORTED_Asym_Pause),
10786 .media_type = ETH_PHY_SFP_FIBER,
10787 .ver_addr = 0,
10788 .req_flow_ctrl = 0,
10789 .req_line_speed = 0,
10790 .speed_cap_mask = 0,
10791 .req_duplex = 0,
10792 .rsrv = 0,
10793 .config_init = (config_init_t)bnx2x_8706_config_init,
10794 .read_status = (read_status_t)bnx2x_8706_read_status,
10795 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
10796 .config_loopback = (config_loopback_t)NULL,
10797 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10798 .hw_reset = (hw_reset_t)NULL,
10799 .set_link_led = (set_link_led_t)NULL,
10800 .phy_specific_func = (phy_specific_func_t)NULL
10801 };
10802
10803 static struct bnx2x_phy phy_8726 = {
10804 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10805 .addr = 0xff,
10806 .def_md_devad = 0,
10807 .flags = (FLAGS_HW_LOCK_REQUIRED |
10808 FLAGS_INIT_XGXS_FIRST),
10809 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10810 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10811 .mdio_ctrl = 0,
10812 .supported = (SUPPORTED_10000baseT_Full |
10813 SUPPORTED_1000baseT_Full |
10814 SUPPORTED_Autoneg |
10815 SUPPORTED_FIBRE |
10816 SUPPORTED_Pause |
10817 SUPPORTED_Asym_Pause),
10818 .media_type = ETH_PHY_NOT_PRESENT,
10819 .ver_addr = 0,
10820 .req_flow_ctrl = 0,
10821 .req_line_speed = 0,
10822 .speed_cap_mask = 0,
10823 .req_duplex = 0,
10824 .rsrv = 0,
10825 .config_init = (config_init_t)bnx2x_8726_config_init,
10826 .read_status = (read_status_t)bnx2x_8726_read_status,
10827 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
10828 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10829 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10830 .hw_reset = (hw_reset_t)NULL,
10831 .set_link_led = (set_link_led_t)NULL,
10832 .phy_specific_func = (phy_specific_func_t)NULL
10833 };
10834
10835 static struct bnx2x_phy phy_8727 = {
10836 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10837 .addr = 0xff,
10838 .def_md_devad = 0,
10839 .flags = FLAGS_FAN_FAILURE_DET_REQ,
10840 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10841 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10842 .mdio_ctrl = 0,
10843 .supported = (SUPPORTED_10000baseT_Full |
10844 SUPPORTED_1000baseT_Full |
10845 SUPPORTED_FIBRE |
10846 SUPPORTED_Pause |
10847 SUPPORTED_Asym_Pause),
10848 .media_type = ETH_PHY_NOT_PRESENT,
10849 .ver_addr = 0,
10850 .req_flow_ctrl = 0,
10851 .req_line_speed = 0,
10852 .speed_cap_mask = 0,
10853 .req_duplex = 0,
10854 .rsrv = 0,
10855 .config_init = (config_init_t)bnx2x_8727_config_init,
10856 .read_status = (read_status_t)bnx2x_8727_read_status,
10857 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
10858 .config_loopback = (config_loopback_t)NULL,
10859 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
10860 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
10861 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
10862 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10863 };
10864 static struct bnx2x_phy phy_8481 = {
10865 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10866 .addr = 0xff,
10867 .def_md_devad = 0,
10868 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10869 FLAGS_REARM_LATCH_SIGNAL,
10870 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10871 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10872 .mdio_ctrl = 0,
10873 .supported = (SUPPORTED_10baseT_Half |
10874 SUPPORTED_10baseT_Full |
10875 SUPPORTED_100baseT_Half |
10876 SUPPORTED_100baseT_Full |
10877 SUPPORTED_1000baseT_Full |
10878 SUPPORTED_10000baseT_Full |
10879 SUPPORTED_TP |
10880 SUPPORTED_Autoneg |
10881 SUPPORTED_Pause |
10882 SUPPORTED_Asym_Pause),
10883 .media_type = ETH_PHY_BASE_T,
10884 .ver_addr = 0,
10885 .req_flow_ctrl = 0,
10886 .req_line_speed = 0,
10887 .speed_cap_mask = 0,
10888 .req_duplex = 0,
10889 .rsrv = 0,
10890 .config_init = (config_init_t)bnx2x_8481_config_init,
10891 .read_status = (read_status_t)bnx2x_848xx_read_status,
10892 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
10893 .config_loopback = (config_loopback_t)NULL,
10894 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10895 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
10896 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10897 .phy_specific_func = (phy_specific_func_t)NULL
10898 };
10899
10900 static struct bnx2x_phy phy_84823 = {
10901 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10902 .addr = 0xff,
10903 .def_md_devad = 0,
10904 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10905 FLAGS_REARM_LATCH_SIGNAL,
10906 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10907 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10908 .mdio_ctrl = 0,
10909 .supported = (SUPPORTED_10baseT_Half |
10910 SUPPORTED_10baseT_Full |
10911 SUPPORTED_100baseT_Half |
10912 SUPPORTED_100baseT_Full |
10913 SUPPORTED_1000baseT_Full |
10914 SUPPORTED_10000baseT_Full |
10915 SUPPORTED_TP |
10916 SUPPORTED_Autoneg |
10917 SUPPORTED_Pause |
10918 SUPPORTED_Asym_Pause),
10919 .media_type = ETH_PHY_BASE_T,
10920 .ver_addr = 0,
10921 .req_flow_ctrl = 0,
10922 .req_line_speed = 0,
10923 .speed_cap_mask = 0,
10924 .req_duplex = 0,
10925 .rsrv = 0,
10926 .config_init = (config_init_t)bnx2x_848x3_config_init,
10927 .read_status = (read_status_t)bnx2x_848xx_read_status,
10928 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10929 .config_loopback = (config_loopback_t)NULL,
10930 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10931 .hw_reset = (hw_reset_t)NULL,
10932 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10933 .phy_specific_func = (phy_specific_func_t)NULL
10934 };
10935
10936 static struct bnx2x_phy phy_84833 = {
10937 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10938 .addr = 0xff,
10939 .def_md_devad = 0,
10940 .flags = FLAGS_FAN_FAILURE_DET_REQ |
10941 FLAGS_REARM_LATCH_SIGNAL,
10942 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10943 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10944 .mdio_ctrl = 0,
10945 .supported = (SUPPORTED_100baseT_Half |
10946 SUPPORTED_100baseT_Full |
10947 SUPPORTED_1000baseT_Full |
10948 SUPPORTED_10000baseT_Full |
10949 SUPPORTED_TP |
10950 SUPPORTED_Autoneg |
10951 SUPPORTED_Pause |
10952 SUPPORTED_Asym_Pause),
10953 .media_type = ETH_PHY_BASE_T,
10954 .ver_addr = 0,
10955 .req_flow_ctrl = 0,
10956 .req_line_speed = 0,
10957 .speed_cap_mask = 0,
10958 .req_duplex = 0,
10959 .rsrv = 0,
10960 .config_init = (config_init_t)bnx2x_848x3_config_init,
10961 .read_status = (read_status_t)bnx2x_848xx_read_status,
10962 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
10963 .config_loopback = (config_loopback_t)NULL,
10964 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
10965 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
10966 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
10967 .phy_specific_func = (phy_specific_func_t)NULL
10968 };
10969
10970 static struct bnx2x_phy phy_54618se = {
10971 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
10972 .addr = 0xff,
10973 .def_md_devad = 0,
10974 .flags = FLAGS_INIT_XGXS_FIRST,
10975 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10976 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10977 .mdio_ctrl = 0,
10978 .supported = (SUPPORTED_10baseT_Half |
10979 SUPPORTED_10baseT_Full |
10980 SUPPORTED_100baseT_Half |
10981 SUPPORTED_100baseT_Full |
10982 SUPPORTED_1000baseT_Full |
10983 SUPPORTED_TP |
10984 SUPPORTED_Autoneg |
10985 SUPPORTED_Pause |
10986 SUPPORTED_Asym_Pause),
10987 .media_type = ETH_PHY_BASE_T,
10988 .ver_addr = 0,
10989 .req_flow_ctrl = 0,
10990 .req_line_speed = 0,
10991 .speed_cap_mask = 0,
10992 /* req_duplex = */0,
10993 /* rsrv = */0,
10994 .config_init = (config_init_t)bnx2x_54618se_config_init,
10995 .read_status = (read_status_t)bnx2x_54618se_read_status,
10996 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
10997 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10998 .format_fw_ver = (format_fw_ver_t)NULL,
10999 .hw_reset = (hw_reset_t)NULL,
11000 .set_link_led = (set_link_led_t)bnx2x_54618se_set_link_led,
11001 .phy_specific_func = (phy_specific_func_t)NULL
11002 };
11003 /*****************************************************************/
11004 /* */
11005 /* Populate the phy according. Main function: bnx2x_populate_phy */
11006 /* */
11007 /*****************************************************************/
11008
11009 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11010 struct bnx2x_phy *phy, u8 port,
11011 u8 phy_index)
11012 {
11013 /* Get the 4 lanes xgxs config rx and tx */
11014 u32 rx = 0, tx = 0, i;
11015 for (i = 0; i < 2; i++) {
11016 /*
11017 * INT_PHY and EXT_PHY1 share the same value location in the
11018 * shmem. When num_phys is greater than 1, than this value
11019 * applies only to EXT_PHY1
11020 */
11021 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11022 rx = REG_RD(bp, shmem_base +
11023 offsetof(struct shmem_region,
11024 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11025
11026 tx = REG_RD(bp, shmem_base +
11027 offsetof(struct shmem_region,
11028 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11029 } else {
11030 rx = REG_RD(bp, shmem_base +
11031 offsetof(struct shmem_region,
11032 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11033
11034 tx = REG_RD(bp, shmem_base +
11035 offsetof(struct shmem_region,
11036 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11037 }
11038
11039 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11040 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11041
11042 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11043 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11044 }
11045 }
11046
11047 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11048 u8 phy_index, u8 port)
11049 {
11050 u32 ext_phy_config = 0;
11051 switch (phy_index) {
11052 case EXT_PHY1:
11053 ext_phy_config = REG_RD(bp, shmem_base +
11054 offsetof(struct shmem_region,
11055 dev_info.port_hw_config[port].external_phy_config));
11056 break;
11057 case EXT_PHY2:
11058 ext_phy_config = REG_RD(bp, shmem_base +
11059 offsetof(struct shmem_region,
11060 dev_info.port_hw_config[port].external_phy_config2));
11061 break;
11062 default:
11063 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11064 return -EINVAL;
11065 }
11066
11067 return ext_phy_config;
11068 }
11069 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11070 struct bnx2x_phy *phy)
11071 {
11072 u32 phy_addr;
11073 u32 chip_id;
11074 u32 switch_cfg = (REG_RD(bp, shmem_base +
11075 offsetof(struct shmem_region,
11076 dev_info.port_feature_config[port].link_config)) &
11077 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11078 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11079 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11080 if (USES_WARPCORE(bp)) {
11081 u32 serdes_net_if;
11082 phy_addr = REG_RD(bp,
11083 MISC_REG_WC0_CTRL_PHY_ADDR);
11084 *phy = phy_warpcore;
11085 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11086 phy->flags |= FLAGS_4_PORT_MODE;
11087 else
11088 phy->flags &= ~FLAGS_4_PORT_MODE;
11089 /* Check Dual mode */
11090 serdes_net_if = (REG_RD(bp, shmem_base +
11091 offsetof(struct shmem_region, dev_info.
11092 port_hw_config[port].default_cfg)) &
11093 PORT_HW_CFG_NET_SERDES_IF_MASK);
11094 /*
11095 * Set the appropriate supported and flags indications per
11096 * interface type of the chip
11097 */
11098 switch (serdes_net_if) {
11099 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11100 phy->supported &= (SUPPORTED_10baseT_Half |
11101 SUPPORTED_10baseT_Full |
11102 SUPPORTED_100baseT_Half |
11103 SUPPORTED_100baseT_Full |
11104 SUPPORTED_1000baseT_Full |
11105 SUPPORTED_FIBRE |
11106 SUPPORTED_Autoneg |
11107 SUPPORTED_Pause |
11108 SUPPORTED_Asym_Pause);
11109 phy->media_type = ETH_PHY_BASE_T;
11110 break;
11111 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11112 phy->media_type = ETH_PHY_XFP_FIBER;
11113 break;
11114 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11115 phy->supported &= (SUPPORTED_1000baseT_Full |
11116 SUPPORTED_10000baseT_Full |
11117 SUPPORTED_FIBRE |
11118 SUPPORTED_Pause |
11119 SUPPORTED_Asym_Pause);
11120 phy->media_type = ETH_PHY_SFP_FIBER;
11121 break;
11122 case PORT_HW_CFG_NET_SERDES_IF_KR:
11123 phy->media_type = ETH_PHY_KR;
11124 phy->supported &= (SUPPORTED_1000baseT_Full |
11125 SUPPORTED_10000baseT_Full |
11126 SUPPORTED_FIBRE |
11127 SUPPORTED_Autoneg |
11128 SUPPORTED_Pause |
11129 SUPPORTED_Asym_Pause);
11130 break;
11131 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11132 phy->media_type = ETH_PHY_KR;
11133 phy->flags |= FLAGS_WC_DUAL_MODE;
11134 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11135 SUPPORTED_FIBRE |
11136 SUPPORTED_Pause |
11137 SUPPORTED_Asym_Pause);
11138 break;
11139 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11140 phy->media_type = ETH_PHY_KR;
11141 phy->flags |= FLAGS_WC_DUAL_MODE;
11142 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11143 SUPPORTED_FIBRE |
11144 SUPPORTED_Pause |
11145 SUPPORTED_Asym_Pause);
11146 break;
11147 default:
11148 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11149 serdes_net_if);
11150 break;
11151 }
11152
11153 /*
11154 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11155 * was not set as expected. For B0, ECO will be enabled so there
11156 * won't be an issue there
11157 */
11158 if (CHIP_REV(bp) == CHIP_REV_Ax)
11159 phy->flags |= FLAGS_MDC_MDIO_WA;
11160 else
11161 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11162 } else {
11163 switch (switch_cfg) {
11164 case SWITCH_CFG_1G:
11165 phy_addr = REG_RD(bp,
11166 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11167 port * 0x10);
11168 *phy = phy_serdes;
11169 break;
11170 case SWITCH_CFG_10G:
11171 phy_addr = REG_RD(bp,
11172 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11173 port * 0x18);
11174 *phy = phy_xgxs;
11175 break;
11176 default:
11177 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11178 return -EINVAL;
11179 }
11180 }
11181 phy->addr = (u8)phy_addr;
11182 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11183 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11184 port);
11185 if (CHIP_IS_E2(bp))
11186 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11187 else
11188 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11189
11190 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11191 port, phy->addr, phy->mdio_ctrl);
11192
11193 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11194 return 0;
11195 }
11196
11197 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11198 u8 phy_index,
11199 u32 shmem_base,
11200 u32 shmem2_base,
11201 u8 port,
11202 struct bnx2x_phy *phy)
11203 {
11204 u32 ext_phy_config, phy_type, config2;
11205 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11206 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11207 phy_index, port);
11208 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11209 /* Select the phy type */
11210 switch (phy_type) {
11211 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11212 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11213 *phy = phy_8073;
11214 break;
11215 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11216 *phy = phy_8705;
11217 break;
11218 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11219 *phy = phy_8706;
11220 break;
11221 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11222 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11223 *phy = phy_8726;
11224 break;
11225 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11226 /* BCM8727_NOC => BCM8727 no over current */
11227 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11228 *phy = phy_8727;
11229 phy->flags |= FLAGS_NOC;
11230 break;
11231 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11232 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11233 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11234 *phy = phy_8727;
11235 break;
11236 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11237 *phy = phy_8481;
11238 break;
11239 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11240 *phy = phy_84823;
11241 break;
11242 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11243 *phy = phy_84833;
11244 break;
11245 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11246 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11247 *phy = phy_54618se;
11248 break;
11249 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11250 *phy = phy_7101;
11251 break;
11252 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11253 *phy = phy_null;
11254 return -EINVAL;
11255 default:
11256 *phy = phy_null;
11257 return 0;
11258 }
11259
11260 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11261 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11262
11263 /*
11264 * The shmem address of the phy version is located on different
11265 * structures. In case this structure is too old, do not set
11266 * the address
11267 */
11268 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11269 dev_info.shared_hw_config.config2));
11270 if (phy_index == EXT_PHY1) {
11271 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11272 port_mb[port].ext_phy_fw_version);
11273
11274 /* Check specific mdc mdio settings */
11275 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11276 mdc_mdio_access = config2 &
11277 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11278 } else {
11279 u32 size = REG_RD(bp, shmem2_base);
11280
11281 if (size >
11282 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11283 phy->ver_addr = shmem2_base +
11284 offsetof(struct shmem2_region,
11285 ext_phy_fw_version2[port]);
11286 }
11287 /* Check specific mdc mdio settings */
11288 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11289 mdc_mdio_access = (config2 &
11290 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11291 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11292 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11293 }
11294 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11295
11296 /*
11297 * In case mdc/mdio_access of the external phy is different than the
11298 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11299 * to prevent one port interfere with another port's CL45 operations.
11300 */
11301 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11302 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11303 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11304 phy_type, port, phy_index);
11305 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
11306 phy->addr, phy->mdio_ctrl);
11307 return 0;
11308 }
11309
11310 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11311 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11312 {
11313 int status = 0;
11314 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11315 if (phy_index == INT_PHY)
11316 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11317 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11318 port, phy);
11319 return status;
11320 }
11321
11322 static void bnx2x_phy_def_cfg(struct link_params *params,
11323 struct bnx2x_phy *phy,
11324 u8 phy_index)
11325 {
11326 struct bnx2x *bp = params->bp;
11327 u32 link_config;
11328 /* Populate the default phy configuration for MF mode */
11329 if (phy_index == EXT_PHY2) {
11330 link_config = REG_RD(bp, params->shmem_base +
11331 offsetof(struct shmem_region, dev_info.
11332 port_feature_config[params->port].link_config2));
11333 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11334 offsetof(struct shmem_region,
11335 dev_info.
11336 port_hw_config[params->port].speed_capability_mask2));
11337 } else {
11338 link_config = REG_RD(bp, params->shmem_base +
11339 offsetof(struct shmem_region, dev_info.
11340 port_feature_config[params->port].link_config));
11341 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11342 offsetof(struct shmem_region,
11343 dev_info.
11344 port_hw_config[params->port].speed_capability_mask));
11345 }
11346 DP(NETIF_MSG_LINK,
11347 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11348 phy_index, link_config, phy->speed_cap_mask);
11349
11350 phy->req_duplex = DUPLEX_FULL;
11351 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11352 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11353 phy->req_duplex = DUPLEX_HALF;
11354 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11355 phy->req_line_speed = SPEED_10;
11356 break;
11357 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11358 phy->req_duplex = DUPLEX_HALF;
11359 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11360 phy->req_line_speed = SPEED_100;
11361 break;
11362 case PORT_FEATURE_LINK_SPEED_1G:
11363 phy->req_line_speed = SPEED_1000;
11364 break;
11365 case PORT_FEATURE_LINK_SPEED_2_5G:
11366 phy->req_line_speed = SPEED_2500;
11367 break;
11368 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11369 phy->req_line_speed = SPEED_10000;
11370 break;
11371 default:
11372 phy->req_line_speed = SPEED_AUTO_NEG;
11373 break;
11374 }
11375
11376 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11377 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11378 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11379 break;
11380 case PORT_FEATURE_FLOW_CONTROL_TX:
11381 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11382 break;
11383 case PORT_FEATURE_FLOW_CONTROL_RX:
11384 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11385 break;
11386 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11387 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11388 break;
11389 default:
11390 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11391 break;
11392 }
11393 }
11394
11395 u32 bnx2x_phy_selection(struct link_params *params)
11396 {
11397 u32 phy_config_swapped, prio_cfg;
11398 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11399
11400 phy_config_swapped = params->multi_phy_config &
11401 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11402
11403 prio_cfg = params->multi_phy_config &
11404 PORT_HW_CFG_PHY_SELECTION_MASK;
11405
11406 if (phy_config_swapped) {
11407 switch (prio_cfg) {
11408 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11409 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11410 break;
11411 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11412 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11413 break;
11414 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11415 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11416 break;
11417 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11418 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11419 break;
11420 }
11421 } else
11422 return_cfg = prio_cfg;
11423
11424 return return_cfg;
11425 }
11426
11427
11428 int bnx2x_phy_probe(struct link_params *params)
11429 {
11430 u8 phy_index, actual_phy_idx, link_cfg_idx;
11431 u32 phy_config_swapped, sync_offset, media_types;
11432 struct bnx2x *bp = params->bp;
11433 struct bnx2x_phy *phy;
11434 params->num_phys = 0;
11435 DP(NETIF_MSG_LINK, "Begin phy probe\n");
11436 phy_config_swapped = params->multi_phy_config &
11437 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11438
11439 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11440 phy_index++) {
11441 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11442 actual_phy_idx = phy_index;
11443 if (phy_config_swapped) {
11444 if (phy_index == EXT_PHY1)
11445 actual_phy_idx = EXT_PHY2;
11446 else if (phy_index == EXT_PHY2)
11447 actual_phy_idx = EXT_PHY1;
11448 }
11449 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11450 " actual_phy_idx %x\n", phy_config_swapped,
11451 phy_index, actual_phy_idx);
11452 phy = &params->phy[actual_phy_idx];
11453 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11454 params->shmem2_base, params->port,
11455 phy) != 0) {
11456 params->num_phys = 0;
11457 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11458 phy_index);
11459 for (phy_index = INT_PHY;
11460 phy_index < MAX_PHYS;
11461 phy_index++)
11462 *phy = phy_null;
11463 return -EINVAL;
11464 }
11465 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11466 break;
11467
11468 sync_offset = params->shmem_base +
11469 offsetof(struct shmem_region,
11470 dev_info.port_hw_config[params->port].media_type);
11471 media_types = REG_RD(bp, sync_offset);
11472
11473 /*
11474 * Update media type for non-PMF sync only for the first time
11475 * In case the media type changes afterwards, it will be updated
11476 * using the update_status function
11477 */
11478 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11479 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11480 actual_phy_idx))) == 0) {
11481 media_types |= ((phy->media_type &
11482 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11483 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11484 actual_phy_idx));
11485 }
11486 REG_WR(bp, sync_offset, media_types);
11487
11488 bnx2x_phy_def_cfg(params, phy, phy_index);
11489 params->num_phys++;
11490 }
11491
11492 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11493 return 0;
11494 }
11495
11496 void bnx2x_init_bmac_loopback(struct link_params *params,
11497 struct link_vars *vars)
11498 {
11499 struct bnx2x *bp = params->bp;
11500 vars->link_up = 1;
11501 vars->line_speed = SPEED_10000;
11502 vars->duplex = DUPLEX_FULL;
11503 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11504 vars->mac_type = MAC_TYPE_BMAC;
11505
11506 vars->phy_flags = PHY_XGXS_FLAG;
11507
11508 bnx2x_xgxs_deassert(params);
11509
11510 /* set bmac loopback */
11511 bnx2x_bmac_enable(params, vars, 1);
11512
11513 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11514 }
11515
11516 void bnx2x_init_emac_loopback(struct link_params *params,
11517 struct link_vars *vars)
11518 {
11519 struct bnx2x *bp = params->bp;
11520 vars->link_up = 1;
11521 vars->line_speed = SPEED_1000;
11522 vars->duplex = DUPLEX_FULL;
11523 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11524 vars->mac_type = MAC_TYPE_EMAC;
11525
11526 vars->phy_flags = PHY_XGXS_FLAG;
11527
11528 bnx2x_xgxs_deassert(params);
11529 /* set bmac loopback */
11530 bnx2x_emac_enable(params, vars, 1);
11531 bnx2x_emac_program(params, vars);
11532 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11533 }
11534
11535 void bnx2x_init_xmac_loopback(struct link_params *params,
11536 struct link_vars *vars)
11537 {
11538 struct bnx2x *bp = params->bp;
11539 vars->link_up = 1;
11540 if (!params->req_line_speed[0])
11541 vars->line_speed = SPEED_10000;
11542 else
11543 vars->line_speed = params->req_line_speed[0];
11544 vars->duplex = DUPLEX_FULL;
11545 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11546 vars->mac_type = MAC_TYPE_XMAC;
11547 vars->phy_flags = PHY_XGXS_FLAG;
11548 /*
11549 * Set WC to loopback mode since link is required to provide clock
11550 * to the XMAC in 20G mode
11551 */
11552 bnx2x_set_aer_mmd(params, &params->phy[0]);
11553 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11554 params->phy[INT_PHY].config_loopback(
11555 &params->phy[INT_PHY],
11556 params);
11557
11558 bnx2x_xmac_enable(params, vars, 1);
11559 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11560 }
11561
11562 void bnx2x_init_umac_loopback(struct link_params *params,
11563 struct link_vars *vars)
11564 {
11565 struct bnx2x *bp = params->bp;
11566 vars->link_up = 1;
11567 vars->line_speed = SPEED_1000;
11568 vars->duplex = DUPLEX_FULL;
11569 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11570 vars->mac_type = MAC_TYPE_UMAC;
11571 vars->phy_flags = PHY_XGXS_FLAG;
11572 bnx2x_umac_enable(params, vars, 1);
11573
11574 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11575 }
11576
11577 void bnx2x_init_xgxs_loopback(struct link_params *params,
11578 struct link_vars *vars)
11579 {
11580 struct bnx2x *bp = params->bp;
11581 vars->link_up = 1;
11582 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11583 vars->duplex = DUPLEX_FULL;
11584 if (params->req_line_speed[0] == SPEED_1000)
11585 vars->line_speed = SPEED_1000;
11586 else
11587 vars->line_speed = SPEED_10000;
11588
11589 if (!USES_WARPCORE(bp))
11590 bnx2x_xgxs_deassert(params);
11591 bnx2x_link_initialize(params, vars);
11592
11593 if (params->req_line_speed[0] == SPEED_1000) {
11594 if (USES_WARPCORE(bp))
11595 bnx2x_umac_enable(params, vars, 0);
11596 else {
11597 bnx2x_emac_program(params, vars);
11598 bnx2x_emac_enable(params, vars, 0);
11599 }
11600 } else {
11601 if (USES_WARPCORE(bp))
11602 bnx2x_xmac_enable(params, vars, 0);
11603 else
11604 bnx2x_bmac_enable(params, vars, 0);
11605 }
11606
11607 if (params->loopback_mode == LOOPBACK_XGXS) {
11608 /* set 10G XGXS loopback */
11609 params->phy[INT_PHY].config_loopback(
11610 &params->phy[INT_PHY],
11611 params);
11612
11613 } else {
11614 /* set external phy loopback */
11615 u8 phy_index;
11616 for (phy_index = EXT_PHY1;
11617 phy_index < params->num_phys; phy_index++) {
11618 if (params->phy[phy_index].config_loopback)
11619 params->phy[phy_index].config_loopback(
11620 &params->phy[phy_index],
11621 params);
11622 }
11623 }
11624 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11625
11626 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11627 }
11628
11629 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11630 {
11631 struct bnx2x *bp = params->bp;
11632 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11633 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11634 params->req_line_speed[0], params->req_flow_ctrl[0]);
11635 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11636 params->req_line_speed[1], params->req_flow_ctrl[1]);
11637 vars->link_status = 0;
11638 vars->phy_link_up = 0;
11639 vars->link_up = 0;
11640 vars->line_speed = 0;
11641 vars->duplex = DUPLEX_FULL;
11642 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11643 vars->mac_type = MAC_TYPE_NONE;
11644 vars->phy_flags = 0;
11645
11646 /* disable attentions */
11647 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11648 (NIG_MASK_XGXS0_LINK_STATUS |
11649 NIG_MASK_XGXS0_LINK10G |
11650 NIG_MASK_SERDES0_LINK_STATUS |
11651 NIG_MASK_MI_INT));
11652
11653 bnx2x_emac_init(params, vars);
11654
11655 if (params->num_phys == 0) {
11656 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11657 return -EINVAL;
11658 }
11659 set_phy_vars(params, vars);
11660
11661 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11662 switch (params->loopback_mode) {
11663 case LOOPBACK_BMAC:
11664 bnx2x_init_bmac_loopback(params, vars);
11665 break;
11666 case LOOPBACK_EMAC:
11667 bnx2x_init_emac_loopback(params, vars);
11668 break;
11669 case LOOPBACK_XMAC:
11670 bnx2x_init_xmac_loopback(params, vars);
11671 break;
11672 case LOOPBACK_UMAC:
11673 bnx2x_init_umac_loopback(params, vars);
11674 break;
11675 case LOOPBACK_XGXS:
11676 case LOOPBACK_EXT_PHY:
11677 bnx2x_init_xgxs_loopback(params, vars);
11678 break;
11679 default:
11680 if (!CHIP_IS_E3(bp)) {
11681 if (params->switch_cfg == SWITCH_CFG_10G)
11682 bnx2x_xgxs_deassert(params);
11683 else
11684 bnx2x_serdes_deassert(bp, params->port);
11685 }
11686 bnx2x_link_initialize(params, vars);
11687 msleep(30);
11688 bnx2x_link_int_enable(params);
11689 break;
11690 }
11691 return 0;
11692 }
11693
11694 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11695 u8 reset_ext_phy)
11696 {
11697 struct bnx2x *bp = params->bp;
11698 u8 phy_index, port = params->port, clear_latch_ind = 0;
11699 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11700 /* disable attentions */
11701 vars->link_status = 0;
11702 bnx2x_update_mng(params, vars->link_status);
11703 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11704 (NIG_MASK_XGXS0_LINK_STATUS |
11705 NIG_MASK_XGXS0_LINK10G |
11706 NIG_MASK_SERDES0_LINK_STATUS |
11707 NIG_MASK_MI_INT));
11708
11709 /* activate nig drain */
11710 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11711
11712 /* disable nig egress interface */
11713 if (!CHIP_IS_E3(bp)) {
11714 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11715 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11716 }
11717
11718 /* Stop BigMac rx */
11719 if (!CHIP_IS_E3(bp))
11720 bnx2x_bmac_rx_disable(bp, port);
11721 else
11722 bnx2x_xmac_disable(params);
11723 /* disable emac */
11724 if (!CHIP_IS_E3(bp))
11725 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11726
11727 msleep(10);
11728 /* The PHY reset is controlled by GPIO 1
11729 * Hold it as vars low
11730 */
11731 /* clear link led */
11732 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11733
11734 if (reset_ext_phy) {
11735 bnx2x_set_mdio_clk(bp, params->chip_id, port);
11736 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11737 phy_index++) {
11738 if (params->phy[phy_index].link_reset) {
11739 bnx2x_set_aer_mmd(params,
11740 &params->phy[phy_index]);
11741 params->phy[phy_index].link_reset(
11742 &params->phy[phy_index],
11743 params);
11744 }
11745 if (params->phy[phy_index].flags &
11746 FLAGS_REARM_LATCH_SIGNAL)
11747 clear_latch_ind = 1;
11748 }
11749 }
11750
11751 if (clear_latch_ind) {
11752 /* Clear latching indication */
11753 bnx2x_rearm_latch_signal(bp, port, 0);
11754 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11755 1 << NIG_LATCH_BC_ENABLE_MI_INT);
11756 }
11757 if (params->phy[INT_PHY].link_reset)
11758 params->phy[INT_PHY].link_reset(
11759 &params->phy[INT_PHY], params);
11760 /* reset BigMac */
11761 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11762 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11763
11764 /* disable nig ingress interface */
11765 if (!CHIP_IS_E3(bp)) {
11766 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11767 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11768 }
11769 vars->link_up = 0;
11770 vars->phy_flags = 0;
11771 return 0;
11772 }
11773
11774 /****************************************************************************/
11775 /* Common function */
11776 /****************************************************************************/
11777 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11778 u32 shmem_base_path[],
11779 u32 shmem2_base_path[], u8 phy_index,
11780 u32 chip_id)
11781 {
11782 struct bnx2x_phy phy[PORT_MAX];
11783 struct bnx2x_phy *phy_blk[PORT_MAX];
11784 u16 val;
11785 s8 port = 0;
11786 s8 port_of_path = 0;
11787 u32 swap_val, swap_override;
11788 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11789 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11790 port ^= (swap_val && swap_override);
11791 bnx2x_ext_phy_hw_reset(bp, port);
11792 /* PART1 - Reset both phys */
11793 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11794 u32 shmem_base, shmem2_base;
11795 /* In E2, same phy is using for port0 of the two paths */
11796 if (CHIP_IS_E1x(bp)) {
11797 shmem_base = shmem_base_path[0];
11798 shmem2_base = shmem2_base_path[0];
11799 port_of_path = port;
11800 } else {
11801 shmem_base = shmem_base_path[port];
11802 shmem2_base = shmem2_base_path[port];
11803 port_of_path = 0;
11804 }
11805
11806 /* Extract the ext phy address for the port */
11807 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11808 port_of_path, &phy[port]) !=
11809 0) {
11810 DP(NETIF_MSG_LINK, "populate_phy failed\n");
11811 return -EINVAL;
11812 }
11813 /* disable attentions */
11814 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11815 port_of_path*4,
11816 (NIG_MASK_XGXS0_LINK_STATUS |
11817 NIG_MASK_XGXS0_LINK10G |
11818 NIG_MASK_SERDES0_LINK_STATUS |
11819 NIG_MASK_MI_INT));
11820
11821 /* Need to take the phy out of low power mode in order
11822 to write to access its registers */
11823 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11824 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11825 port);
11826
11827 /* Reset the phy */
11828 bnx2x_cl45_write(bp, &phy[port],
11829 MDIO_PMA_DEVAD,
11830 MDIO_PMA_REG_CTRL,
11831 1<<15);
11832 }
11833
11834 /* Add delay of 150ms after reset */
11835 msleep(150);
11836
11837 if (phy[PORT_0].addr & 0x1) {
11838 phy_blk[PORT_0] = &(phy[PORT_1]);
11839 phy_blk[PORT_1] = &(phy[PORT_0]);
11840 } else {
11841 phy_blk[PORT_0] = &(phy[PORT_0]);
11842 phy_blk[PORT_1] = &(phy[PORT_1]);
11843 }
11844
11845 /* PART2 - Download firmware to both phys */
11846 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11847 if (CHIP_IS_E1x(bp))
11848 port_of_path = port;
11849 else
11850 port_of_path = 0;
11851
11852 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11853 phy_blk[port]->addr);
11854 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11855 port_of_path))
11856 return -EINVAL;
11857
11858 /* Only set bit 10 = 1 (Tx power down) */
11859 bnx2x_cl45_read(bp, phy_blk[port],
11860 MDIO_PMA_DEVAD,
11861 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11862
11863 /* Phase1 of TX_POWER_DOWN reset */
11864 bnx2x_cl45_write(bp, phy_blk[port],
11865 MDIO_PMA_DEVAD,
11866 MDIO_PMA_REG_TX_POWER_DOWN,
11867 (val | 1<<10));
11868 }
11869
11870 /*
11871 * Toggle Transmitter: Power down and then up with 600ms delay
11872 * between
11873 */
11874 msleep(600);
11875
11876 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11877 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11878 /* Phase2 of POWER_DOWN_RESET */
11879 /* Release bit 10 (Release Tx power down) */
11880 bnx2x_cl45_read(bp, phy_blk[port],
11881 MDIO_PMA_DEVAD,
11882 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11883
11884 bnx2x_cl45_write(bp, phy_blk[port],
11885 MDIO_PMA_DEVAD,
11886 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11887 msleep(15);
11888
11889 /* Read modify write the SPI-ROM version select register */
11890 bnx2x_cl45_read(bp, phy_blk[port],
11891 MDIO_PMA_DEVAD,
11892 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11893 bnx2x_cl45_write(bp, phy_blk[port],
11894 MDIO_PMA_DEVAD,
11895 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11896
11897 /* set GPIO2 back to LOW */
11898 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11899 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11900 }
11901 return 0;
11902 }
11903 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11904 u32 shmem_base_path[],
11905 u32 shmem2_base_path[], u8 phy_index,
11906 u32 chip_id)
11907 {
11908 u32 val;
11909 s8 port;
11910 struct bnx2x_phy phy;
11911 /* Use port1 because of the static port-swap */
11912 /* Enable the module detection interrupt */
11913 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11914 val |= ((1<<MISC_REGISTERS_GPIO_3)|
11915 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11916 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11917
11918 bnx2x_ext_phy_hw_reset(bp, 0);
11919 msleep(5);
11920 for (port = 0; port < PORT_MAX; port++) {
11921 u32 shmem_base, shmem2_base;
11922
11923 /* In E2, same phy is using for port0 of the two paths */
11924 if (CHIP_IS_E1x(bp)) {
11925 shmem_base = shmem_base_path[0];
11926 shmem2_base = shmem2_base_path[0];
11927 } else {
11928 shmem_base = shmem_base_path[port];
11929 shmem2_base = shmem2_base_path[port];
11930 }
11931 /* Extract the ext phy address for the port */
11932 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11933 port, &phy) !=
11934 0) {
11935 DP(NETIF_MSG_LINK, "populate phy failed\n");
11936 return -EINVAL;
11937 }
11938
11939 /* Reset phy*/
11940 bnx2x_cl45_write(bp, &phy,
11941 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11942
11943
11944 /* Set fault module detected LED on */
11945 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11946 MISC_REGISTERS_GPIO_HIGH,
11947 port);
11948 }
11949
11950 return 0;
11951 }
11952 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11953 u8 *io_gpio, u8 *io_port)
11954 {
11955
11956 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11957 offsetof(struct shmem_region,
11958 dev_info.port_hw_config[PORT_0].default_cfg));
11959 switch (phy_gpio_reset) {
11960 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11961 *io_gpio = 0;
11962 *io_port = 0;
11963 break;
11964 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11965 *io_gpio = 1;
11966 *io_port = 0;
11967 break;
11968 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11969 *io_gpio = 2;
11970 *io_port = 0;
11971 break;
11972 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11973 *io_gpio = 3;
11974 *io_port = 0;
11975 break;
11976 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11977 *io_gpio = 0;
11978 *io_port = 1;
11979 break;
11980 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11981 *io_gpio = 1;
11982 *io_port = 1;
11983 break;
11984 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11985 *io_gpio = 2;
11986 *io_port = 1;
11987 break;
11988 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11989 *io_gpio = 3;
11990 *io_port = 1;
11991 break;
11992 default:
11993 /* Don't override the io_gpio and io_port */
11994 break;
11995 }
11996 }
11997
11998 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11999 u32 shmem_base_path[],
12000 u32 shmem2_base_path[], u8 phy_index,
12001 u32 chip_id)
12002 {
12003 s8 port, reset_gpio;
12004 u32 swap_val, swap_override;
12005 struct bnx2x_phy phy[PORT_MAX];
12006 struct bnx2x_phy *phy_blk[PORT_MAX];
12007 s8 port_of_path;
12008 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12009 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12010
12011 reset_gpio = MISC_REGISTERS_GPIO_1;
12012 port = 1;
12013
12014 /*
12015 * Retrieve the reset gpio/port which control the reset.
12016 * Default is GPIO1, PORT1
12017 */
12018 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12019 (u8 *)&reset_gpio, (u8 *)&port);
12020
12021 /* Calculate the port based on port swap */
12022 port ^= (swap_val && swap_override);
12023
12024 /* Initiate PHY reset*/
12025 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12026 port);
12027 msleep(1);
12028 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12029 port);
12030
12031 msleep(5);
12032
12033 /* PART1 - Reset both phys */
12034 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12035 u32 shmem_base, shmem2_base;
12036
12037 /* In E2, same phy is using for port0 of the two paths */
12038 if (CHIP_IS_E1x(bp)) {
12039 shmem_base = shmem_base_path[0];
12040 shmem2_base = shmem2_base_path[0];
12041 port_of_path = port;
12042 } else {
12043 shmem_base = shmem_base_path[port];
12044 shmem2_base = shmem2_base_path[port];
12045 port_of_path = 0;
12046 }
12047
12048 /* Extract the ext phy address for the port */
12049 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12050 port_of_path, &phy[port]) !=
12051 0) {
12052 DP(NETIF_MSG_LINK, "populate phy failed\n");
12053 return -EINVAL;
12054 }
12055 /* disable attentions */
12056 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12057 port_of_path*4,
12058 (NIG_MASK_XGXS0_LINK_STATUS |
12059 NIG_MASK_XGXS0_LINK10G |
12060 NIG_MASK_SERDES0_LINK_STATUS |
12061 NIG_MASK_MI_INT));
12062
12063
12064 /* Reset the phy */
12065 bnx2x_cl45_write(bp, &phy[port],
12066 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12067 }
12068
12069 /* Add delay of 150ms after reset */
12070 msleep(150);
12071 if (phy[PORT_0].addr & 0x1) {
12072 phy_blk[PORT_0] = &(phy[PORT_1]);
12073 phy_blk[PORT_1] = &(phy[PORT_0]);
12074 } else {
12075 phy_blk[PORT_0] = &(phy[PORT_0]);
12076 phy_blk[PORT_1] = &(phy[PORT_1]);
12077 }
12078 /* PART2 - Download firmware to both phys */
12079 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12080 if (CHIP_IS_E1x(bp))
12081 port_of_path = port;
12082 else
12083 port_of_path = 0;
12084 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12085 phy_blk[port]->addr);
12086 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12087 port_of_path))
12088 return -EINVAL;
12089 /* Disable PHY transmitter output */
12090 bnx2x_cl45_write(bp, phy_blk[port],
12091 MDIO_PMA_DEVAD,
12092 MDIO_PMA_REG_TX_DISABLE, 1);
12093
12094 }
12095 return 0;
12096 }
12097
12098 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12099 u32 shmem2_base_path[], u8 phy_index,
12100 u32 ext_phy_type, u32 chip_id)
12101 {
12102 int rc = 0;
12103
12104 switch (ext_phy_type) {
12105 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12106 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12107 shmem2_base_path,
12108 phy_index, chip_id);
12109 break;
12110 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12111 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12112 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12113 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12114 shmem2_base_path,
12115 phy_index, chip_id);
12116 break;
12117
12118 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12119 /*
12120 * GPIO1 affects both ports, so there's need to pull
12121 * it for single port alone
12122 */
12123 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12124 shmem2_base_path,
12125 phy_index, chip_id);
12126 break;
12127 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12128 /*
12129 * GPIO3's are linked, and so both need to be toggled
12130 * to obtain required 2us pulse.
12131 */
12132 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12133 break;
12134 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12135 rc = -EINVAL;
12136 break;
12137 default:
12138 DP(NETIF_MSG_LINK,
12139 "ext_phy 0x%x common init not required\n",
12140 ext_phy_type);
12141 break;
12142 }
12143
12144 if (rc != 0)
12145 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12146 " Port %d\n",
12147 0);
12148 return rc;
12149 }
12150
12151 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12152 u32 shmem2_base_path[], u32 chip_id)
12153 {
12154 int rc = 0;
12155 u32 phy_ver, val;
12156 u8 phy_index = 0;
12157 u32 ext_phy_type, ext_phy_config;
12158 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12159 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12160 DP(NETIF_MSG_LINK, "Begin common phy init\n");
12161 if (CHIP_IS_E3(bp)) {
12162 /* Enable EPIO */
12163 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12164 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12165 }
12166 /* Check if common init was already done */
12167 phy_ver = REG_RD(bp, shmem_base_path[0] +
12168 offsetof(struct shmem_region,
12169 port_mb[PORT_0].ext_phy_fw_version));
12170 if (phy_ver) {
12171 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12172 phy_ver);
12173 return 0;
12174 }
12175
12176 /* Read the ext_phy_type for arbitrary port(0) */
12177 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12178 phy_index++) {
12179 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12180 shmem_base_path[0],
12181 phy_index, 0);
12182 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12183 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12184 shmem2_base_path,
12185 phy_index, ext_phy_type,
12186 chip_id);
12187 }
12188 return rc;
12189 }
12190
12191 static void bnx2x_check_over_curr(struct link_params *params,
12192 struct link_vars *vars)
12193 {
12194 struct bnx2x *bp = params->bp;
12195 u32 cfg_pin;
12196 u8 port = params->port;
12197 u32 pin_val;
12198
12199 cfg_pin = (REG_RD(bp, params->shmem_base +
12200 offsetof(struct shmem_region,
12201 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12202 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12203 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12204
12205 /* Ignore check if no external input PIN available */
12206 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12207 return;
12208
12209 if (!pin_val) {
12210 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12211 netdev_err(bp->dev, "Error: Power fault on Port %d has"
12212 " been detected and the power to "
12213 "that SFP+ module has been removed"
12214 " to prevent failure of the card."
12215 " Please remove the SFP+ module and"
12216 " restart the system to clear this"
12217 " error.\n",
12218 params->port);
12219 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12220 }
12221 } else
12222 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12223 }
12224
12225 static void bnx2x_analyze_link_error(struct link_params *params,
12226 struct link_vars *vars, u32 lss_status)
12227 {
12228 struct bnx2x *bp = params->bp;
12229 /* Compare new value with previous value */
12230 u8 led_mode;
12231 u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12232
12233 if ((lss_status ^ half_open_conn) == 0)
12234 return;
12235
12236 /* If values differ */
12237 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12238 half_open_conn, lss_status);
12239
12240 /*
12241 * a. Update shmem->link_status accordingly
12242 * b. Update link_vars->link_up
12243 */
12244 if (lss_status) {
12245 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12246 vars->link_status &= ~LINK_STATUS_LINK_UP;
12247 vars->link_up = 0;
12248 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12249 /*
12250 * Set LED mode to off since the PHY doesn't know about these
12251 * errors
12252 */
12253 led_mode = LED_MODE_OFF;
12254 } else {
12255 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12256 vars->link_status |= LINK_STATUS_LINK_UP;
12257 vars->link_up = 1;
12258 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12259 led_mode = LED_MODE_OPER;
12260 }
12261 /* Update the LED according to the link state */
12262 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12263
12264 /* Update link status in the shared memory */
12265 bnx2x_update_mng(params, vars->link_status);
12266
12267 /* C. Trigger General Attention */
12268 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12269 bnx2x_notify_link_changed(bp);
12270 }
12271
12272 /******************************************************************************
12273 * Description:
12274 * This function checks for half opened connection change indication.
12275 * When such change occurs, it calls the bnx2x_analyze_link_error
12276 * to check if Remote Fault is set or cleared. Reception of remote fault
12277 * status message in the MAC indicates that the peer's MAC has detected
12278 * a fault, for example, due to break in the TX side of fiber.
12279 *
12280 ******************************************************************************/
12281 static void bnx2x_check_half_open_conn(struct link_params *params,
12282 struct link_vars *vars)
12283 {
12284 struct bnx2x *bp = params->bp;
12285 u32 lss_status = 0;
12286 u32 mac_base;
12287 /* In case link status is physically up @ 10G do */
12288 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12289 return;
12290
12291 if (CHIP_IS_E3(bp) &&
12292 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12293 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12294 /* Check E3 XMAC */
12295 /*
12296 * Note that link speed cannot be queried here, since it may be
12297 * zero while link is down. In case UMAC is active, LSS will
12298 * simply not be set
12299 */
12300 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12301
12302 /* Clear stick bits (Requires rising edge) */
12303 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12304 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12305 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12306 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12307 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12308 lss_status = 1;
12309
12310 bnx2x_analyze_link_error(params, vars, lss_status);
12311 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12312 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12313 /* Check E1X / E2 BMAC */
12314 u32 lss_status_reg;
12315 u32 wb_data[2];
12316 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12317 NIG_REG_INGRESS_BMAC0_MEM;
12318 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12319 if (CHIP_IS_E2(bp))
12320 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12321 else
12322 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12323
12324 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12325 lss_status = (wb_data[0] > 0);
12326
12327 bnx2x_analyze_link_error(params, vars, lss_status);
12328 }
12329 }
12330
12331 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12332 {
12333 struct bnx2x *bp = params->bp;
12334 u16 phy_idx;
12335 if (!params) {
12336 DP(NETIF_MSG_LINK, "Uninitialized params !\n");
12337 return;
12338 }
12339
12340 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12341 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12342 bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12343 bnx2x_check_half_open_conn(params, vars);
12344 break;
12345 }
12346 }
12347
12348 if (CHIP_IS_E3(bp))
12349 bnx2x_check_over_curr(params, vars);
12350 }
12351
12352 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12353 {
12354 u8 phy_index;
12355 struct bnx2x_phy phy;
12356 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12357 phy_index++) {
12358 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12359 0, &phy) != 0) {
12360 DP(NETIF_MSG_LINK, "populate phy failed\n");
12361 return 0;
12362 }
12363
12364 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12365 return 1;
12366 }
12367 return 0;
12368 }
12369
12370 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12371 u32 shmem_base,
12372 u32 shmem2_base,
12373 u8 port)
12374 {
12375 u8 phy_index, fan_failure_det_req = 0;
12376 struct bnx2x_phy phy;
12377 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12378 phy_index++) {
12379 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12380 port, &phy)
12381 != 0) {
12382 DP(NETIF_MSG_LINK, "populate phy failed\n");
12383 return 0;
12384 }
12385 fan_failure_det_req |= (phy.flags &
12386 FLAGS_FAN_FAILURE_DET_REQ);
12387 }
12388 return fan_failure_det_req;
12389 }
12390
12391 void bnx2x_hw_reset_phy(struct link_params *params)
12392 {
12393 u8 phy_index;
12394 struct bnx2x *bp = params->bp;
12395 bnx2x_update_mng(params, 0);
12396 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12397 (NIG_MASK_XGXS0_LINK_STATUS |
12398 NIG_MASK_XGXS0_LINK10G |
12399 NIG_MASK_SERDES0_LINK_STATUS |
12400 NIG_MASK_MI_INT));
12401
12402 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12403 phy_index++) {
12404 if (params->phy[phy_index].hw_reset) {
12405 params->phy[phy_index].hw_reset(
12406 &params->phy[phy_index],
12407 params);
12408 params->phy[phy_index] = phy_null;
12409 }
12410 }
12411 }
12412
12413 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12414 u32 chip_id, u32 shmem_base, u32 shmem2_base,
12415 u8 port)
12416 {
12417 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12418 u32 val;
12419 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12420 if (CHIP_IS_E3(bp)) {
12421 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12422 shmem_base,
12423 port,
12424 &gpio_num,
12425 &gpio_port) != 0)
12426 return;
12427 } else {
12428 struct bnx2x_phy phy;
12429 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12430 phy_index++) {
12431 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12432 shmem2_base, port, &phy)
12433 != 0) {
12434 DP(NETIF_MSG_LINK, "populate phy failed\n");
12435 return;
12436 }
12437 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12438 gpio_num = MISC_REGISTERS_GPIO_3;
12439 gpio_port = port;
12440 break;
12441 }
12442 }
12443 }
12444
12445 if (gpio_num == 0xff)
12446 return;
12447
12448 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12449 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12450
12451 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12452 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12453 gpio_port ^= (swap_val && swap_override);
12454
12455 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12456 (gpio_num + (gpio_port << 2));
12457
12458 sync_offset = shmem_base +
12459 offsetof(struct shmem_region,
12460 dev_info.port_hw_config[port].aeu_int_mask);
12461 REG_WR(bp, sync_offset, vars->aeu_int_mask);
12462
12463 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12464 gpio_num, gpio_port, vars->aeu_int_mask);
12465
12466 if (port == 0)
12467 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12468 else
12469 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12470
12471 /* Open appropriate AEU for interrupts */
12472 aeu_mask = REG_RD(bp, offset);
12473 aeu_mask |= vars->aeu_int_mask;
12474 REG_WR(bp, offset, aeu_mask);
12475
12476 /* Enable the GPIO to trigger interrupt */
12477 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12478 val |= 1 << (gpio_num + (gpio_port << 2));
12479 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12480 }
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