drivers/net/ethernet/intel/ixgbe/ixgbe.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _IXGBE_H_
  29 #define _IXGBE_H_
  30
  31 #include <linux/bitops.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/cpumask.h>
  36 #include <linux/aer.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include "ixgbe_type.h"
  40 #include "ixgbe_common.h"
  41 #include "ixgbe_dcb.h"
  42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
  43 #define IXGBE_FCOE
  44 #include "ixgbe_fcoe.h"
  45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
  46 #ifdef CONFIG_IXGBE_DCA
  47 #include <linux/dca.h>
  48 #endif
  49
  50 /* common prefix used by pr_<> macros */
  51 #undef pr_fmt
  52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  53
  54 /* TX/RX descriptor defines */
  55 #define IXGBE_DEFAULT_TXD                   512
  56 #define IXGBE_DEFAULT_TX_WORK               256
  57 #define IXGBE_MAX_TXD                      4096
  58 #define IXGBE_MIN_TXD                        64
  59
  60 #define IXGBE_DEFAULT_RXD                   512
  61 #define IXGBE_MAX_RXD                      4096
  62 #define IXGBE_MIN_RXD                        64
  63
  64 /* flow control */
  65 #define IXGBE_MIN_FCRTL                    0x40
  66 #define IXGBE_MAX_FCRTL                 0x7FF80
  67 #define IXGBE_MIN_FCRTH                   0x600
  68 #define IXGBE_MAX_FCRTH                 0x7FFF0
  69 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
  70 #define IXGBE_MIN_FCPAUSE                     0
  71 #define IXGBE_MAX_FCPAUSE                0xFFFF
  72
  73 /* Supported Rx Buffer Sizes */
  74 #define IXGBE_RXBUFFER_512   512    /* Used for packet split */
  75 #define IXGBE_RXBUFFER_2K   2048
  76 #define IXGBE_RXBUFFER_3K   3072
  77 #define IXGBE_RXBUFFER_4K   4096
  78 #define IXGBE_RXBUFFER_7K   7168
  79 #define IXGBE_RXBUFFER_8K   8192
  80 #define IXGBE_RXBUFFER_15K  15360
  81 #define IXGBE_MAX_RXBUFFER  16384  /* largest size for a single descriptor */
  82
  83 /*
  84  * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
  85  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  86  * this adds up to 512 bytes of extra data meaning the smallest allocation
  87  * we could have is 1K.
  88  * i.e. RXBUFFER_512 --> size-1024 slab
  89  */
  90 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
  91
  92 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  93
  94 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  95 #define IXGBE_RX_BUFFER_WRITE   16      /* Must be power of 2 */
  96
  97 #define IXGBE_TX_FLAGS_CSUM             (u32)(1)
  98 #define IXGBE_TX_FLAGS_HW_VLAN          (u32)(1 << 1)
  99 #define IXGBE_TX_FLAGS_SW_VLAN          (u32)(1 << 2)
 100 #define IXGBE_TX_FLAGS_TSO              (u32)(1 << 3)
 101 #define IXGBE_TX_FLAGS_IPV4             (u32)(1 << 4)
 102 #define IXGBE_TX_FLAGS_FCOE             (u32)(1 << 5)
 103 #define IXGBE_TX_FLAGS_FSO              (u32)(1 << 6)
 104 #define IXGBE_TX_FLAGS_TXSW             (u32)(1 << 7)
 105 #define IXGBE_TX_FLAGS_MAPPED_AS_PAGE   (u32)(1 << 8)
 106 #define IXGBE_TX_FLAGS_VLAN_MASK        0xffff0000
 107 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0xe0000000
 108 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT  29
 109 #define IXGBE_TX_FLAGS_VLAN_SHIFT       16
 110
 111 #define IXGBE_MAX_RSC_INT_RATE          162760
 112
 113 #define IXGBE_MAX_VF_MC_ENTRIES         30
 114 #define IXGBE_MAX_VF_FUNCTIONS          64
 115 #define IXGBE_MAX_VFTA_ENTRIES          128
 116 #define MAX_EMULATION_MAC_ADDRS         16
 117 #define IXGBE_MAX_PF_MACVLANS           15
 118 #define VMDQ_P(p)   ((p) + adapter->num_vfs)
 119 #define IXGBE_82599_VF_DEVICE_ID        0x10ED
 120 #define IXGBE_X540_VF_DEVICE_ID         0x1515
 121
 122 struct vf_data_storage {
 123         unsigned char vf_mac_addresses[ETH_ALEN];
 124         u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 125         u16 num_vf_mc_hashes;
 126         u16 default_vf_vlan_id;
 127         u16 vlans_enabled;
 128         bool clear_to_send;
 129         bool pf_set_mac;
 130         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 131         u16 pf_qos;
 132         u16 tx_rate;
 133         u16 vlan_count;
 134         u8 spoofchk_enabled;
 135         struct pci_dev *vfdev;
 136 };
 137
 138 struct vf_macvlans {
 139         struct list_head l;
 140         int vf;
 141         int rar_entry;
 142         bool free;
 143         bool is_macvlan;
 144         u8 vf_macvlan[ETH_ALEN];
 145 };
 146
 147 #define IXGBE_MAX_TXD_PWR       14
 148 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 149
 150 /* Tx Descriptors needed, worst case */
 151 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
 152 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
 153
 154 /* wrapper around a pointer to a socket buffer,
 155  * so a DMA handle can be stored along with the buffer */
 156 struct ixgbe_tx_buffer {
 157         union ixgbe_adv_tx_desc *next_to_watch;
 158         unsigned long time_stamp;
 159         dma_addr_t dma;
 160         u32 length;
 161         u32 tx_flags;
 162         struct sk_buff *skb;
 163         u32 bytecount;
 164         u16 gso_segs;
 165 };
 166
 167 struct ixgbe_rx_buffer {
 168         struct sk_buff *skb;
 169         dma_addr_t dma;
 170         struct page *page;
 171         dma_addr_t page_dma;
 172         unsigned int page_offset;
 173 };
 174
 175 struct ixgbe_queue_stats {
 176         u64 packets;
 177         u64 bytes;
 178 };
 179
 180 struct ixgbe_tx_queue_stats {
 181         u64 restart_queue;
 182         u64 tx_busy;
 183         u64 completed;
 184         u64 tx_done_old;
 185 };
 186
 187 struct ixgbe_rx_queue_stats {
 188         u64 rsc_count;
 189         u64 rsc_flush;
 190         u64 non_eop_descs;
 191         u64 alloc_rx_page_failed;
 192         u64 alloc_rx_buff_failed;
 193 };
 194
 195 enum ixbge_ring_state_t {
 196         __IXGBE_TX_FDIR_INIT_DONE,
 197         __IXGBE_TX_DETECT_HANG,
 198         __IXGBE_HANG_CHECK_ARMED,
 199         __IXGBE_RX_PS_ENABLED,
 200         __IXGBE_RX_RSC_ENABLED,
 201 };
 202
 203 #define ring_is_ps_enabled(ring) \
 204         test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 205 #define set_ring_ps_enabled(ring) \
 206         set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 207 #define clear_ring_ps_enabled(ring) \
 208         clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
 209 #define check_for_tx_hang(ring) \
 210         test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 211 #define set_check_for_tx_hang(ring) \
 212         set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 213 #define clear_check_for_tx_hang(ring) \
 214         clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
 215 #define ring_is_rsc_enabled(ring) \
 216         test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 217 #define set_ring_rsc_enabled(ring) \
 218         set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 219 #define clear_ring_rsc_enabled(ring) \
 220         clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 221 struct ixgbe_ring {
 222         struct ixgbe_ring *next;        /* pointer to next ring in q_vector */
 223         void *desc;                     /* descriptor ring memory */
 224         struct device *dev;             /* device for DMA mapping */
 225         struct net_device *netdev;      /* netdev ring belongs to */
 226         union {
 227                 struct ixgbe_tx_buffer *tx_buffer_info;
 228                 struct ixgbe_rx_buffer *rx_buffer_info;
 229         };
 230         unsigned long state;
 231         u8 __iomem *tail;
 232
 233         u16 count;                      /* amount of descriptors */
 234         u16 rx_buf_len;
 235
 236         u8 queue_index; /* needed for multiqueue queue management */
 237         u8 reg_idx;                     /* holds the special value that gets
 238                                          * the hardware register offset
 239                                          * associated with this ring, which is
 240                                          * different for DCB and RSS modes
 241                                          */
 242         u8 atr_sample_rate;
 243         u8 atr_count;
 244
 245         u16 next_to_use;
 246         u16 next_to_clean;
 247
 248         u8 dcb_tc;
 249         struct ixgbe_queue_stats stats;
 250         struct u64_stats_sync syncp;
 251         union {
 252                 struct ixgbe_tx_queue_stats tx_stats;
 253                 struct ixgbe_rx_queue_stats rx_stats;
 254         };
 255         int numa_node;
 256         unsigned int size;              /* length in bytes */
 257         dma_addr_t dma;                 /* phys. address of descriptor ring */
 258         struct rcu_head rcu;
 259         struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 260 } ____cacheline_internodealigned_in_smp;
 261
 262 enum ixgbe_ring_f_enum {
 263         RING_F_NONE = 0,
 264         RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
 265         RING_F_RSS,
 266         RING_F_FDIR,
 267 #ifdef IXGBE_FCOE
 268         RING_F_FCOE,
 269 #endif /* IXGBE_FCOE */
 270
 271         RING_F_ARRAY_SIZE      /* must be last in enum set */
 272 };
 273
 274 #define IXGBE_MAX_RSS_INDICES  16
 275 #define IXGBE_MAX_VMDQ_INDICES 64
 276 #define IXGBE_MAX_FDIR_INDICES 64
 277 #ifdef IXGBE_FCOE
 278 #define IXGBE_MAX_FCOE_INDICES  8
 279 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 280 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
 281 #else
 282 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
 283 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
 284 #endif /* IXGBE_FCOE */
 285 struct ixgbe_ring_feature {
 286         int indices;
 287         int mask;
 288 } ____cacheline_internodealigned_in_smp;
 289
 290 struct ixgbe_ring_container {
 291         struct ixgbe_ring *ring;        /* pointer to linked list of rings */
 292         unsigned int total_bytes;       /* total bytes processed this int */
 293         unsigned int total_packets;     /* total packets processed this int */
 294         u16 work_limit;                 /* total work allowed per interrupt */
 295         u8 count;                       /* total number of rings in vector */
 296         u8 itr;                         /* current ITR setting for ring */
 297 };
 298
 299 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
 300                               ? 8 : 1)
 301 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
 302
 303 /* MAX_MSIX_Q_VECTORS of these are allocated,
 304  * but we only use one per queue-specific vector.
 305  */
 306 struct ixgbe_q_vector {
 307         struct ixgbe_adapter *adapter;
 308 #ifdef CONFIG_IXGBE_DCA
 309         int cpu;            /* CPU for DCA */
 310 #endif
 311         u16 v_idx;              /* index of q_vector within array, also used for
 312                                  * finding the bit in EICR and friends that
 313                                  * represents the vector for this ring */
 314         u16 itr;                /* Interrupt throttle rate written to EITR */
 315         struct ixgbe_ring_container rx, tx;
 316
 317         struct napi_struct napi;
 318         cpumask_var_t affinity_mask;
 319         char name[IFNAMSIZ + 9];
 320 };
 321
 322 /*
 323  * microsecond values for various ITR rates shifted by 2 to fit itr register
 324  * with the first 3 bits reserved 0
 325  */
 326 #define IXGBE_MIN_RSC_ITR       24
 327 #define IXGBE_100K_ITR          40
 328 #define IXGBE_20K_ITR           200
 329 #define IXGBE_10K_ITR           400
 330 #define IXGBE_8K_ITR            500
 331
 332 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
 333 {
 334         u16 ntc = ring->next_to_clean;
 335         u16 ntu = ring->next_to_use;
 336
 337         return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
 338 }
 339
 340 #define IXGBE_RX_DESC_ADV(R, i)     \
 341         (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
 342 #define IXGBE_TX_DESC_ADV(R, i)     \
 343         (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
 344 #define IXGBE_TX_CTXTDESC_ADV(R, i)         \
 345         (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
 346
 347 #define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
 348 #ifdef IXGBE_FCOE
 349 /* Use 3K as the baby jumbo frame size for FCoE */
 350 #define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
 351 #endif /* IXGBE_FCOE */
 352
 353 #define OTHER_VECTOR 1
 354 #define NON_Q_VECTORS (OTHER_VECTOR)
 355
 356 #define MAX_MSIX_VECTORS_82599 64
 357 #define MAX_MSIX_Q_VECTORS_82599 64
 358 #define MAX_MSIX_VECTORS_82598 18
 359 #define MAX_MSIX_Q_VECTORS_82598 16
 360
 361 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
 362 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
 363
 364 #define MIN_MSIX_Q_VECTORS 2
 365 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
 366
 367 /* board specific private data structure */
 368 struct ixgbe_adapter {
 369         unsigned long state;
 370
 371         /* Some features need tri-state capability,
 372          * thus the additional *_CAPABLE flags.
 373          */
 374         u32 flags;
 375 #define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
 376 #define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
 377 #define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
 378 #define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
 379 #define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
 380 #define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
 381 #define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
 382 #define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
 383 #define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
 384 #define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
 385 #define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
 386 #define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
 387 #define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
 388 #define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
 389 #define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
 390 #define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
 391 #define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
 392 #define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
 393 #define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
 394 #define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
 395 #define IXGBE_FLAG_NEED_LINK_CONFIG             (u32)(1 << 23)
 396 #define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 24)
 397 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 25)
 398 #define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 26)
 399 #define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 27)
 400 #define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 28)
 401 #define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 29)
 402
 403         u32 flags2;
 404 #define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
 405 #define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
 406 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
 407 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT           (u32)(1 << 3)
 408 #define IXGBE_FLAG2_SEARCH_FOR_SFP              (u32)(1 << 4)
 409 #define IXGBE_FLAG2_SFP_NEEDS_RESET             (u32)(1 << 5)
 410 #define IXGBE_FLAG2_RESET_REQUESTED             (u32)(1 << 6)
 411 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT        (u32)(1 << 7)
 412
 413         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 414         u16 bd_number;
 415         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
 416
 417         /* DCB parameters */
 418         struct ieee_pfc *ixgbe_ieee_pfc;
 419         struct ieee_ets *ixgbe_ieee_ets;
 420         struct ixgbe_dcb_config dcb_cfg;
 421         struct ixgbe_dcb_config temp_dcb_cfg;
 422         u8 dcb_set_bitmap;
 423         u8 dcbx_cap;
 424         enum ixgbe_fc_mode last_lfc_mode;
 425
 426         /* Interrupt Throttle Rate */
 427         u32 rx_itr_setting;
 428         u32 tx_itr_setting;
 429         u16 eitr_low;
 430         u16 eitr_high;
 431
 432         /* Work limits */
 433         u16 tx_work_limit;
 434
 435         /* TX */
 436         struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 437         int num_tx_queues;
 438         u32 tx_timeout_count;
 439         bool detect_tx_hung;
 440
 441         u64 restart_queue;
 442         u64 lsc_int;
 443
 444         /* RX */
 445         struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
 446         int num_rx_queues;
 447         int num_rx_pools;               /* == num_rx_queues in 82598 */
 448         int num_rx_queues_per_pool;     /* 1 if 82598, can be many if 82599 */
 449         u64 hw_csum_rx_error;
 450         u64 hw_rx_no_dma_resources;
 451         u64 non_eop_descs;
 452         int num_msix_vectors;
 453         int max_msix_q_vectors;         /* true count of q_vectors for device */
 454         struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
 455         struct msix_entry *msix_entries;
 456
 457         u32 alloc_rx_page_failed;
 458         u32 alloc_rx_buff_failed;
 459
 460 /* default to trying for four seconds */
 461 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
 462
 463         /* OS defined structs */
 464         struct net_device *netdev;
 465         struct pci_dev *pdev;
 466
 467         u32 test_icr;
 468         struct ixgbe_ring test_tx_ring;
 469         struct ixgbe_ring test_rx_ring;
 470
 471         /* structs defined in ixgbe_hw.h */
 472         struct ixgbe_hw hw;
 473         u16 msg_enable;
 474         struct ixgbe_hw_stats stats;
 475
 476         /* Interrupt Throttle Rate */
 477         u32 rx_eitr_param;
 478         u32 tx_eitr_param;
 479
 480         u64 tx_busy;
 481         unsigned int tx_ring_count;
 482         unsigned int rx_ring_count;
 483
 484         u32 link_speed;
 485         bool link_up;
 486         unsigned long link_check_timeout;
 487
 488         struct work_struct service_task;
 489         struct timer_list service_timer;
 490         u32 fdir_pballoc;
 491         u32 atr_sample_rate;
 492         unsigned long fdir_overflow; /* number of times ATR was backed off */
 493         spinlock_t fdir_perfect_lock;
 494 #ifdef IXGBE_FCOE
 495         struct ixgbe_fcoe fcoe;
 496 #endif /* IXGBE_FCOE */
 497         u64 rsc_total_count;
 498         u64 rsc_total_flush;
 499         u32 wol;
 500         u16 eeprom_verh;
 501         u16 eeprom_verl;
 502         u16 eeprom_cap;
 503
 504         int node;
 505         u32 led_reg;
 506         u32 interrupt_event;
 507
 508         /* SR-IOV */
 509         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
 510         unsigned int num_vfs;
 511         struct vf_data_storage *vfinfo;
 512         int vf_rate_link_speed;
 513         struct vf_macvlans vf_mvs;
 514         struct vf_macvlans *mv_list;
 515
 516         struct hlist_head fdir_filter_list;
 517         union ixgbe_atr_input fdir_mask;
 518         int fdir_filter_count;
 519         u32 timer_event_accumulator;
 520         u32 vferr_refcount;
 521 };
 522
 523 struct ixgbe_fdir_filter {
 524         struct hlist_node fdir_node;
 525         union ixgbe_atr_input filter;
 526         u16 sw_idx;
 527         u16 action;
 528 };
 529
 530 enum ixbge_state_t {
 531         __IXGBE_TESTING,
 532         __IXGBE_RESETTING,
 533         __IXGBE_DOWN,
 534         __IXGBE_SERVICE_SCHED,
 535         __IXGBE_IN_SFP_INIT,
 536 };
 537
 538 struct ixgbe_rsc_cb {
 539         dma_addr_t dma;
 540         u16 skb_cnt;
 541         bool delay_unmap;
 542 };
 543 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
 544
 545 enum ixgbe_boards {
 546         board_82598,
 547         board_82599,
 548         board_X540,
 549 };
 550
 551 extern struct ixgbe_info ixgbe_82598_info;
 552 extern struct ixgbe_info ixgbe_82599_info;
 553 extern struct ixgbe_info ixgbe_X540_info;
 554 #ifdef CONFIG_IXGBE_DCB
 555 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 556 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
 557                               struct ixgbe_dcb_config *dst_dcb_cfg,
 558                               int tc_max);
 559 #endif
 560
 561 extern char ixgbe_driver_name[];
 562 extern const char ixgbe_driver_version[];
 563
 564 extern void ixgbe_up(struct ixgbe_adapter *adapter);
 565 extern void ixgbe_down(struct ixgbe_adapter *adapter);
 566 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 567 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 568 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
 569 extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
 570 extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
 571 extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 572 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 573 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 574 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 575 extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
 576                                    struct ixgbe_ring *);
 577 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 578 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 579 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 580 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
 581                                          struct ixgbe_adapter *,
 582                                          struct ixgbe_ring *);
 583 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
 584                                              struct ixgbe_tx_buffer *);
 585 extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 586 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 587 extern int ethtool_ioctl(struct ifreq *ifr);
 588 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 589 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 590 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
 591 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 592                                                  union ixgbe_atr_hash_dword input,
 593                                                  union ixgbe_atr_hash_dword common,
 594                                                  u8 queue);
 595 extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 596                                            union ixgbe_atr_input *input_mask);
 597 extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 598                                                  union ixgbe_atr_input *input,
 599                                                  u16 soft_id, u8 queue);
 600 extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 601                                                  union ixgbe_atr_input *input,
 602                                                  u16 soft_id);
 603 extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 604                                                  union ixgbe_atr_input *mask);
 605 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 606 extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
 607 extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
 608 extern void ixgbe_do_reset(struct net_device *netdev);
 609 #ifdef IXGBE_FCOE
 610 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
 611 extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
 612                      u32 tx_flags, u8 *hdr_len);
 613 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
 614 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
 615                           union ixgbe_adv_rx_desc *rx_desc,
 616                           struct sk_buff *skb,
 617                           u32 staterr);
 618 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
 619                               struct scatterlist *sgl, unsigned int sgc);
 620 extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
 621                                  struct scatterlist *sgl, unsigned int sgc);
 622 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
 623 extern int ixgbe_fcoe_enable(struct net_device *netdev);
 624 extern int ixgbe_fcoe_disable(struct net_device *netdev);
 625 #ifdef CONFIG_IXGBE_DCB
 626 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
 627 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
 628 #endif /* CONFIG_IXGBE_DCB */
 629 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
 630 #endif /* IXGBE_FCOE */
 631
 632 #endif /* _IXGBE_H_ */