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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / net / ethernet / octeon / octeon_mgmt.c
blobbc1d946b7971b6c1ede4fc7616aa5609d153b26c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Cavium Networks
7 */
8
9 #include <linux/capability.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/platform_device.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/if.h>
17 #include <linux/if_vlan.h>
18 #include <linux/slab.h>
19 #include <linux/phy.h>
20 #include <linux/spinlock.h>
21
22 #include <asm/octeon/octeon.h>
23 #include <asm/octeon/cvmx-mixx-defs.h>
24 #include <asm/octeon/cvmx-agl-defs.h>
25
26 #define DRV_NAME "octeon_mgmt"
27 #define DRV_VERSION "2.0"
28 #define DRV_DESCRIPTION \
29 "Cavium Networks Octeon MII (management) port Network Driver"
30
31 #define OCTEON_MGMT_NAPI_WEIGHT 16
32
33 /*
34 * Ring sizes that are powers of two allow for more efficient modulo
35 * opertions.
36 */
37 #define OCTEON_MGMT_RX_RING_SIZE 512
38 #define OCTEON_MGMT_TX_RING_SIZE 128
39
40 /* Allow 8 bytes for vlan and FCS. */
41 #define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
42
43 union mgmt_port_ring_entry {
44 u64 d64;
45 struct {
46 u64 reserved_62_63:2;
47 /* Length of the buffer/packet in bytes */
48 u64 len:14;
49 /* For TX, signals that the packet should be timestamped */
50 u64 tstamp:1;
51 /* The RX error code */
52 u64 code:7;
53 #define RING_ENTRY_CODE_DONE 0xf
54 #define RING_ENTRY_CODE_MORE 0x10
55 /* Physical address of the buffer */
56 u64 addr:40;
57 } s;
58 };
59
60 struct octeon_mgmt {
61 struct net_device *netdev;
62 int port;
63 int irq;
64 u64 *tx_ring;
65 dma_addr_t tx_ring_handle;
66 unsigned int tx_next;
67 unsigned int tx_next_clean;
68 unsigned int tx_current_fill;
69 /* The tx_list lock also protects the ring related variables */
70 struct sk_buff_head tx_list;
71
72 /* RX variables only touched in napi_poll. No locking necessary. */
73 u64 *rx_ring;
74 dma_addr_t rx_ring_handle;
75 unsigned int rx_next;
76 unsigned int rx_next_fill;
77 unsigned int rx_current_fill;
78 struct sk_buff_head rx_list;
79
80 spinlock_t lock;
81 unsigned int last_duplex;
82 unsigned int last_link;
83 struct device *dev;
84 struct napi_struct napi;
85 struct tasklet_struct tx_clean_tasklet;
86 struct phy_device *phydev;
87 };
88
89 static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
90 {
91 int port = p->port;
92 union cvmx_mixx_intena mix_intena;
93 unsigned long flags;
94
95 spin_lock_irqsave(&p->lock, flags);
96 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
97 mix_intena.s.ithena = enable ? 1 : 0;
98 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
99 spin_unlock_irqrestore(&p->lock, flags);
100 }
101
102 static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable)
103 {
104 int port = p->port;
105 union cvmx_mixx_intena mix_intena;
106 unsigned long flags;
107
108 spin_lock_irqsave(&p->lock, flags);
109 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
110 mix_intena.s.othena = enable ? 1 : 0;
111 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
112 spin_unlock_irqrestore(&p->lock, flags);
113 }
114
115 static inline void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p)
116 {
117 octeon_mgmt_set_rx_irq(p, 1);
118 }
119
120 static inline void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p)
121 {
122 octeon_mgmt_set_rx_irq(p, 0);
123 }
124
125 static inline void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p)
126 {
127 octeon_mgmt_set_tx_irq(p, 1);
128 }
129
130 static inline void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p)
131 {
132 octeon_mgmt_set_tx_irq(p, 0);
133 }
134
135 static unsigned int ring_max_fill(unsigned int ring_size)
136 {
137 return ring_size - 8;
138 }
139
140 static unsigned int ring_size_to_bytes(unsigned int ring_size)
141 {
142 return ring_size * sizeof(union mgmt_port_ring_entry);
143 }
144
145 static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
146 {
147 struct octeon_mgmt *p = netdev_priv(netdev);
148 int port = p->port;
149
150 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) {
151 unsigned int size;
152 union mgmt_port_ring_entry re;
153 struct sk_buff *skb;
154
155 /* CN56XX pass 1 needs 8 bytes of padding. */
156 size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN;
157
158 skb = netdev_alloc_skb(netdev, size);
159 if (!skb)
160 break;
161 skb_reserve(skb, NET_IP_ALIGN);
162 __skb_queue_tail(&p->rx_list, skb);
163
164 re.d64 = 0;
165 re.s.len = size;
166 re.s.addr = dma_map_single(p->dev, skb->data,
167 size,
168 DMA_FROM_DEVICE);
169
170 /* Put it in the ring. */
171 p->rx_ring[p->rx_next_fill] = re.d64;
172 dma_sync_single_for_device(p->dev, p->rx_ring_handle,
173 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
174 DMA_BIDIRECTIONAL);
175 p->rx_next_fill =
176 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE;
177 p->rx_current_fill++;
178 /* Ring the bell. */
179 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
180 }
181 }
182
183 static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
184 {
185 int port = p->port;
186 union cvmx_mixx_orcnt mix_orcnt;
187 union mgmt_port_ring_entry re;
188 struct sk_buff *skb;
189 int cleaned = 0;
190 unsigned long flags;
191
192 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
193 while (mix_orcnt.s.orcnt) {
194 spin_lock_irqsave(&p->tx_list.lock, flags);
195
196 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
197
198 if (mix_orcnt.s.orcnt == 0) {
199 spin_unlock_irqrestore(&p->tx_list.lock, flags);
200 break;
201 }
202
203 dma_sync_single_for_cpu(p->dev, p->tx_ring_handle,
204 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
205 DMA_BIDIRECTIONAL);
206
207 re.d64 = p->tx_ring[p->tx_next_clean];
208 p->tx_next_clean =
209 (p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE;
210 skb = __skb_dequeue(&p->tx_list);
211
212 mix_orcnt.u64 = 0;
213 mix_orcnt.s.orcnt = 1;
214
215 /* Acknowledge to hardware that we have the buffer. */
216 cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64);
217 p->tx_current_fill--;
218
219 spin_unlock_irqrestore(&p->tx_list.lock, flags);
220
221 dma_unmap_single(p->dev, re.s.addr, re.s.len,
222 DMA_TO_DEVICE);
223 dev_kfree_skb_any(skb);
224 cleaned++;
225
226 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
227 }
228
229 if (cleaned && netif_queue_stopped(p->netdev))
230 netif_wake_queue(p->netdev);
231 }
232
233 static void octeon_mgmt_clean_tx_tasklet(unsigned long arg)
234 {
235 struct octeon_mgmt *p = (struct octeon_mgmt *)arg;
236 octeon_mgmt_clean_tx_buffers(p);
237 octeon_mgmt_enable_tx_irq(p);
238 }
239
240 static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
241 {
242 struct octeon_mgmt *p = netdev_priv(netdev);
243 int port = p->port;
244 unsigned long flags;
245 u64 drop, bad;
246
247 /* These reads also clear the count registers. */
248 drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port));
249 bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port));
250
251 if (drop || bad) {
252 /* Do an atomic update. */
253 spin_lock_irqsave(&p->lock, flags);
254 netdev->stats.rx_errors += bad;
255 netdev->stats.rx_dropped += drop;
256 spin_unlock_irqrestore(&p->lock, flags);
257 }
258 }
259
260 static void octeon_mgmt_update_tx_stats(struct net_device *netdev)
261 {
262 struct octeon_mgmt *p = netdev_priv(netdev);
263 int port = p->port;
264 unsigned long flags;
265
266 union cvmx_agl_gmx_txx_stat0 s0;
267 union cvmx_agl_gmx_txx_stat1 s1;
268
269 /* These reads also clear the count registers. */
270 s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port));
271 s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port));
272
273 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) {
274 /* Do an atomic update. */
275 spin_lock_irqsave(&p->lock, flags);
276 netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol;
277 netdev->stats.collisions += s1.s.scol + s1.s.mcol;
278 spin_unlock_irqrestore(&p->lock, flags);
279 }
280 }
281
282 /*
283 * Dequeue a receive skb and its corresponding ring entry. The ring
284 * entry is returned, *pskb is updated to point to the skb.
285 */
286 static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,
287 struct sk_buff **pskb)
288 {
289 union mgmt_port_ring_entry re;
290
291 dma_sync_single_for_cpu(p->dev, p->rx_ring_handle,
292 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
293 DMA_BIDIRECTIONAL);
294
295 re.d64 = p->rx_ring[p->rx_next];
296 p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE;
297 p->rx_current_fill--;
298 *pskb = __skb_dequeue(&p->rx_list);
299
300 dma_unmap_single(p->dev, re.s.addr,
301 ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM,
302 DMA_FROM_DEVICE);
303
304 return re.d64;
305 }
306
307
308 static int octeon_mgmt_receive_one(struct octeon_mgmt *p)
309 {
310 int port = p->port;
311 struct net_device *netdev = p->netdev;
312 union cvmx_mixx_ircnt mix_ircnt;
313 union mgmt_port_ring_entry re;
314 struct sk_buff *skb;
315 struct sk_buff *skb2;
316 struct sk_buff *skb_new;
317 union mgmt_port_ring_entry re2;
318 int rc = 1;
319
320
321 re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb);
322 if (likely(re.s.code == RING_ENTRY_CODE_DONE)) {
323 /* A good packet, send it up. */
324 skb_put(skb, re.s.len);
325 good:
326 skb->protocol = eth_type_trans(skb, netdev);
327 netdev->stats.rx_packets++;
328 netdev->stats.rx_bytes += skb->len;
329 netif_receive_skb(skb);
330 rc = 0;
331 } else if (re.s.code == RING_ENTRY_CODE_MORE) {
332 /*
333 * Packet split across skbs. This can happen if we
334 * increase the MTU. Buffers that are already in the
335 * rx ring can then end up being too small. As the rx
336 * ring is refilled, buffers sized for the new MTU
337 * will be used and we should go back to the normal
338 * non-split case.
339 */
340 skb_put(skb, re.s.len);
341 do {
342 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
343 if (re2.s.code != RING_ENTRY_CODE_MORE
344 && re2.s.code != RING_ENTRY_CODE_DONE)
345 goto split_error;
346 skb_put(skb2, re2.s.len);
347 skb_new = skb_copy_expand(skb, 0, skb2->len,
348 GFP_ATOMIC);
349 if (!skb_new)
350 goto split_error;
351 if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new),
352 skb2->len))
353 goto split_error;
354 skb_put(skb_new, skb2->len);
355 dev_kfree_skb_any(skb);
356 dev_kfree_skb_any(skb2);
357 skb = skb_new;
358 } while (re2.s.code == RING_ENTRY_CODE_MORE);
359 goto good;
360 } else {
361 /* Some other error, discard it. */
362 dev_kfree_skb_any(skb);
363 /*
364 * Error statistics are accumulated in
365 * octeon_mgmt_update_rx_stats.
366 */
367 }
368 goto done;
369 split_error:
370 /* Discard the whole mess. */
371 dev_kfree_skb_any(skb);
372 dev_kfree_skb_any(skb2);
373 while (re2.s.code == RING_ENTRY_CODE_MORE) {
374 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
375 dev_kfree_skb_any(skb2);
376 }
377 netdev->stats.rx_errors++;
378
379 done:
380 /* Tell the hardware we processed a packet. */
381 mix_ircnt.u64 = 0;
382 mix_ircnt.s.ircnt = 1;
383 cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64);
384 return rc;
385 }
386
387 static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
388 {
389 int port = p->port;
390 unsigned int work_done = 0;
391 union cvmx_mixx_ircnt mix_ircnt;
392 int rc;
393
394 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
395 while (work_done < budget && mix_ircnt.s.ircnt) {
396
397 rc = octeon_mgmt_receive_one(p);
398 if (!rc)
399 work_done++;
400
401 /* Check for more packets. */
402 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
403 }
404
405 octeon_mgmt_rx_fill_ring(p->netdev);
406
407 return work_done;
408 }
409
410 static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget)
411 {
412 struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi);
413 struct net_device *netdev = p->netdev;
414 unsigned int work_done = 0;
415
416 work_done = octeon_mgmt_receive_packets(p, budget);
417
418 if (work_done < budget) {
419 /* We stopped because no more packets were available. */
420 napi_complete(napi);
421 octeon_mgmt_enable_rx_irq(p);
422 }
423 octeon_mgmt_update_rx_stats(netdev);
424
425 return work_done;
426 }
427
428 /* Reset the hardware to clean state. */
429 static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
430 {
431 union cvmx_mixx_ctl mix_ctl;
432 union cvmx_mixx_bist mix_bist;
433 union cvmx_agl_gmx_bist agl_gmx_bist;
434
435 mix_ctl.u64 = 0;
436 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
437 do {
438 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port));
439 } while (mix_ctl.s.busy);
440 mix_ctl.s.reset = 1;
441 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
442 cvmx_read_csr(CVMX_MIXX_CTL(p->port));
443 cvmx_wait(64);
444
445 mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port));
446 if (mix_bist.u64)
447 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n",
448 (unsigned long long)mix_bist.u64);
449
450 agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
451 if (agl_gmx_bist.u64)
452 dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n",
453 (unsigned long long)agl_gmx_bist.u64);
454 }
455
456 struct octeon_mgmt_cam_state {
457 u64 cam[6];
458 u64 cam_mask;
459 int cam_index;
460 };
461
462 static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs,
463 unsigned char *addr)
464 {
465 int i;
466
467 for (i = 0; i < 6; i++)
468 cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index));
469 cs->cam_mask |= (1ULL << cs->cam_index);
470 cs->cam_index++;
471 }
472
473 static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
474 {
475 struct octeon_mgmt *p = netdev_priv(netdev);
476 int port = p->port;
477 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl;
478 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx;
479 unsigned long flags;
480 unsigned int prev_packet_enable;
481 unsigned int cam_mode = 1; /* 1 - Accept on CAM match */
482 unsigned int multicast_mode = 1; /* 1 - Reject all multicast. */
483 struct octeon_mgmt_cam_state cam_state;
484 struct netdev_hw_addr *ha;
485 int available_cam_entries;
486
487 memset(&cam_state, 0, sizeof(cam_state));
488
489 if ((netdev->flags & IFF_PROMISC) || netdev->uc.count > 7) {
490 cam_mode = 0;
491 available_cam_entries = 8;
492 } else {
493 /*
494 * One CAM entry for the primary address, leaves seven
495 * for the secondary addresses.
496 */
497 available_cam_entries = 7 - netdev->uc.count;
498 }
499
500 if (netdev->flags & IFF_MULTICAST) {
501 if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI) ||
502 netdev_mc_count(netdev) > available_cam_entries)
503 multicast_mode = 2; /* 2 - Accept all multicast. */
504 else
505 multicast_mode = 0; /* 0 - Use CAM. */
506 }
507
508 if (cam_mode == 1) {
509 /* Add primary address. */
510 octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr);
511 netdev_for_each_uc_addr(ha, netdev)
512 octeon_mgmt_cam_state_add(&cam_state, ha->addr);
513 }
514 if (multicast_mode == 0) {
515 netdev_for_each_mc_addr(ha, netdev)
516 octeon_mgmt_cam_state_add(&cam_state, ha->addr);
517 }
518
519 spin_lock_irqsave(&p->lock, flags);
520
521 /* Disable packet I/O. */
522 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
523 prev_packet_enable = agl_gmx_prtx.s.en;
524 agl_gmx_prtx.s.en = 0;
525 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
526
527 adr_ctl.u64 = 0;
528 adr_ctl.s.cam_mode = cam_mode;
529 adr_ctl.s.mcst = multicast_mode;
530 adr_ctl.s.bcst = 1; /* Allow broadcast */
531
532 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64);
533
534 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]);
535 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]);
536 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]);
537 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]);
538 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]);
539 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]);
540 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask);
541
542 /* Restore packet I/O. */
543 agl_gmx_prtx.s.en = prev_packet_enable;
544 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
545
546 spin_unlock_irqrestore(&p->lock, flags);
547 }
548
549 static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr)
550 {
551 struct sockaddr *sa = addr;
552
553 if (!is_valid_ether_addr(sa->sa_data))
554 return -EADDRNOTAVAIL;
555
556 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
557
558 octeon_mgmt_set_rx_filtering(netdev);
559
560 return 0;
561 }
562
563 static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
564 {
565 struct octeon_mgmt *p = netdev_priv(netdev);
566 int port = p->port;
567 int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM;
568
569 /*
570 * Limit the MTU to make sure the ethernet packets are between
571 * 64 bytes and 16383 bytes.
572 */
573 if (size_without_fcs < 64 || size_without_fcs > 16383) {
574 dev_warn(p->dev, "MTU must be between %d and %d.\n",
575 64 - OCTEON_MGMT_RX_HEADROOM,
576 16383 - OCTEON_MGMT_RX_HEADROOM);
577 return -EINVAL;
578 }
579
580 netdev->mtu = new_mtu;
581
582 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs);
583 cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port),
584 (size_without_fcs + 7) & 0xfff8);
585
586 return 0;
587 }
588
589 static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id)
590 {
591 struct net_device *netdev = dev_id;
592 struct octeon_mgmt *p = netdev_priv(netdev);
593 int port = p->port;
594 union cvmx_mixx_isr mixx_isr;
595
596 mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port));
597
598 /* Clear any pending interrupts */
599 cvmx_write_csr(CVMX_MIXX_ISR(port), mixx_isr.u64);
600 cvmx_read_csr(CVMX_MIXX_ISR(port));
601
602 if (mixx_isr.s.irthresh) {
603 octeon_mgmt_disable_rx_irq(p);
604 napi_schedule(&p->napi);
605 }
606 if (mixx_isr.s.orthresh) {
607 octeon_mgmt_disable_tx_irq(p);
608 tasklet_schedule(&p->tx_clean_tasklet);
609 }
610
611 return IRQ_HANDLED;
612 }
613
614 static int octeon_mgmt_ioctl(struct net_device *netdev,
615 struct ifreq *rq, int cmd)
616 {
617 struct octeon_mgmt *p = netdev_priv(netdev);
618
619 if (!netif_running(netdev))
620 return -EINVAL;
621
622 if (!p->phydev)
623 return -EINVAL;
624
625 return phy_mii_ioctl(p->phydev, rq, cmd);
626 }
627
628 static void octeon_mgmt_adjust_link(struct net_device *netdev)
629 {
630 struct octeon_mgmt *p = netdev_priv(netdev);
631 int port = p->port;
632 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
633 unsigned long flags;
634 int link_changed = 0;
635
636 spin_lock_irqsave(&p->lock, flags);
637 if (p->phydev->link) {
638 if (!p->last_link)
639 link_changed = 1;
640 if (p->last_duplex != p->phydev->duplex) {
641 p->last_duplex = p->phydev->duplex;
642 prtx_cfg.u64 =
643 cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
644 prtx_cfg.s.duplex = p->phydev->duplex;
645 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port),
646 prtx_cfg.u64);
647 }
648 } else {
649 if (p->last_link)
650 link_changed = -1;
651 }
652 p->last_link = p->phydev->link;
653 spin_unlock_irqrestore(&p->lock, flags);
654
655 if (link_changed != 0) {
656 if (link_changed > 0) {
657 netif_carrier_on(netdev);
658 pr_info("%s: Link is up - %d/%s\n", netdev->name,
659 p->phydev->speed,
660 DUPLEX_FULL == p->phydev->duplex ?
661 "Full" : "Half");
662 } else {
663 netif_carrier_off(netdev);
664 pr_info("%s: Link is down\n", netdev->name);
665 }
666 }
667 }
668
669 static int octeon_mgmt_init_phy(struct net_device *netdev)
670 {
671 struct octeon_mgmt *p = netdev_priv(netdev);
672 char phy_id[20];
673
674 if (octeon_is_simulation()) {
675 /* No PHYs in the simulator. */
676 netif_carrier_on(netdev);
677 return 0;
678 }
679
680 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", p->port);
681
682 p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0,
683 PHY_INTERFACE_MODE_MII);
684
685 if (IS_ERR(p->phydev)) {
686 p->phydev = NULL;
687 return -1;
688 }
689
690 phy_start_aneg(p->phydev);
691
692 return 0;
693 }
694
695 static int octeon_mgmt_open(struct net_device *netdev)
696 {
697 struct octeon_mgmt *p = netdev_priv(netdev);
698 int port = p->port;
699 union cvmx_mixx_ctl mix_ctl;
700 union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode;
701 union cvmx_mixx_oring1 oring1;
702 union cvmx_mixx_iring1 iring1;
703 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
704 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
705 union cvmx_mixx_irhwm mix_irhwm;
706 union cvmx_mixx_orhwm mix_orhwm;
707 union cvmx_mixx_intena mix_intena;
708 struct sockaddr sa;
709
710 /* Allocate ring buffers. */
711 p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
712 GFP_KERNEL);
713 if (!p->tx_ring)
714 return -ENOMEM;
715 p->tx_ring_handle =
716 dma_map_single(p->dev, p->tx_ring,
717 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
718 DMA_BIDIRECTIONAL);
719 p->tx_next = 0;
720 p->tx_next_clean = 0;
721 p->tx_current_fill = 0;
722
723
724 p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
725 GFP_KERNEL);
726 if (!p->rx_ring)
727 goto err_nomem;
728 p->rx_ring_handle =
729 dma_map_single(p->dev, p->rx_ring,
730 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
731 DMA_BIDIRECTIONAL);
732
733 p->rx_next = 0;
734 p->rx_next_fill = 0;
735 p->rx_current_fill = 0;
736
737 octeon_mgmt_reset_hw(p);
738
739 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
740
741 /* Bring it out of reset if needed. */
742 if (mix_ctl.s.reset) {
743 mix_ctl.s.reset = 0;
744 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
745 do {
746 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
747 } while (mix_ctl.s.reset);
748 }
749
750 agl_gmx_inf_mode.u64 = 0;
751 agl_gmx_inf_mode.s.en = 1;
752 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
753
754 oring1.u64 = 0;
755 oring1.s.obase = p->tx_ring_handle >> 3;
756 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE;
757 cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64);
758
759 iring1.u64 = 0;
760 iring1.s.ibase = p->rx_ring_handle >> 3;
761 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
762 cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64);
763
764 /* Disable packet I/O. */
765 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
766 prtx_cfg.s.en = 0;
767 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
768
769 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
770 octeon_mgmt_set_mac_address(netdev, &sa);
771
772 octeon_mgmt_change_mtu(netdev, netdev->mtu);
773
774 /*
775 * Enable the port HW. Packets are not allowed until
776 * cvmx_mgmt_port_enable() is called.
777 */
778 mix_ctl.u64 = 0;
779 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */
780 mix_ctl.s.en = 1; /* Enable the port */
781 mix_ctl.s.nbtarb = 0; /* Arbitration mode */
782 /* MII CB-request FIFO programmable high watermark */
783 mix_ctl.s.mrq_hwm = 1;
784 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
785
786 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
787 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
788 /*
789 * Force compensation values, as they are not
790 * determined properly by HW
791 */
792 union cvmx_agl_gmx_drv_ctl drv_ctl;
793
794 drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
795 if (port) {
796 drv_ctl.s.byp_en1 = 1;
797 drv_ctl.s.nctl1 = 6;
798 drv_ctl.s.pctl1 = 6;
799 } else {
800 drv_ctl.s.byp_en = 1;
801 drv_ctl.s.nctl = 6;
802 drv_ctl.s.pctl = 6;
803 }
804 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
805 }
806
807 octeon_mgmt_rx_fill_ring(netdev);
808
809 /* Clear statistics. */
810 /* Clear on read. */
811 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1);
812 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0);
813 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0);
814
815 cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1);
816 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0);
817 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0);
818
819 /* Clear any pending interrupts */
820 cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port)));
821
822 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name,
823 netdev)) {
824 dev_err(p->dev, "request_irq(%d) failed.\n", p->irq);
825 goto err_noirq;
826 }
827
828 /* Interrupt every single RX packet */
829 mix_irhwm.u64 = 0;
830 mix_irhwm.s.irhwm = 0;
831 cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64);
832
833 /* Interrupt when we have 1 or more packets to clean. */
834 mix_orhwm.u64 = 0;
835 mix_orhwm.s.orhwm = 1;
836 cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64);
837
838 /* Enable receive and transmit interrupts */
839 mix_intena.u64 = 0;
840 mix_intena.s.ithena = 1;
841 mix_intena.s.othena = 1;
842 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
843
844
845 /* Enable packet I/O. */
846
847 rxx_frm_ctl.u64 = 0;
848 rxx_frm_ctl.s.pre_align = 1;
849 /*
850 * When set, disables the length check for non-min sized pkts
851 * with padding in the client data.
852 */
853 rxx_frm_ctl.s.pad_len = 1;
854 /* When set, disables the length check for VLAN pkts */
855 rxx_frm_ctl.s.vlan_len = 1;
856 /* When set, PREAMBLE checking is less strict */
857 rxx_frm_ctl.s.pre_free = 1;
858 /* Control Pause Frames can match station SMAC */
859 rxx_frm_ctl.s.ctl_smac = 0;
860 /* Control Pause Frames can match globally assign Multicast address */
861 rxx_frm_ctl.s.ctl_mcst = 1;
862 /* Forward pause information to TX block */
863 rxx_frm_ctl.s.ctl_bck = 1;
864 /* Drop Control Pause Frames */
865 rxx_frm_ctl.s.ctl_drp = 1;
866 /* Strip off the preamble */
867 rxx_frm_ctl.s.pre_strp = 1;
868 /*
869 * This port is configured to send PREAMBLE+SFD to begin every
870 * frame. GMX checks that the PREAMBLE is sent correctly.
871 */
872 rxx_frm_ctl.s.pre_chk = 1;
873 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
874
875 /* Enable the AGL block */
876 agl_gmx_inf_mode.u64 = 0;
877 agl_gmx_inf_mode.s.en = 1;
878 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
879
880 /* Configure the port duplex and enables */
881 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
882 prtx_cfg.s.tx_en = 1;
883 prtx_cfg.s.rx_en = 1;
884 prtx_cfg.s.en = 1;
885 p->last_duplex = 1;
886 prtx_cfg.s.duplex = p->last_duplex;
887 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
888
889 p->last_link = 0;
890 netif_carrier_off(netdev);
891
892 if (octeon_mgmt_init_phy(netdev)) {
893 dev_err(p->dev, "Cannot initialize PHY.\n");
894 goto err_noirq;
895 }
896
897 netif_wake_queue(netdev);
898 napi_enable(&p->napi);
899
900 return 0;
901 err_noirq:
902 octeon_mgmt_reset_hw(p);
903 dma_unmap_single(p->dev, p->rx_ring_handle,
904 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
905 DMA_BIDIRECTIONAL);
906 kfree(p->rx_ring);
907 err_nomem:
908 dma_unmap_single(p->dev, p->tx_ring_handle,
909 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
910 DMA_BIDIRECTIONAL);
911 kfree(p->tx_ring);
912 return -ENOMEM;
913 }
914
915 static int octeon_mgmt_stop(struct net_device *netdev)
916 {
917 struct octeon_mgmt *p = netdev_priv(netdev);
918
919 napi_disable(&p->napi);
920 netif_stop_queue(netdev);
921
922 if (p->phydev)
923 phy_disconnect(p->phydev);
924
925 netif_carrier_off(netdev);
926
927 octeon_mgmt_reset_hw(p);
928
929 free_irq(p->irq, netdev);
930
931 /* dma_unmap is a nop on Octeon, so just free everything. */
932 skb_queue_purge(&p->tx_list);
933 skb_queue_purge(&p->rx_list);
934
935 dma_unmap_single(p->dev, p->rx_ring_handle,
936 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
937 DMA_BIDIRECTIONAL);
938 kfree(p->rx_ring);
939
940 dma_unmap_single(p->dev, p->tx_ring_handle,
941 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
942 DMA_BIDIRECTIONAL);
943 kfree(p->tx_ring);
944
945 return 0;
946 }
947
948 static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
949 {
950 struct octeon_mgmt *p = netdev_priv(netdev);
951 int port = p->port;
952 union mgmt_port_ring_entry re;
953 unsigned long flags;
954 int rv = NETDEV_TX_BUSY;
955
956 re.d64 = 0;
957 re.s.len = skb->len;
958 re.s.addr = dma_map_single(p->dev, skb->data,
959 skb->len,
960 DMA_TO_DEVICE);
961
962 spin_lock_irqsave(&p->tx_list.lock, flags);
963
964 if (unlikely(p->tx_current_fill >= ring_max_fill(OCTEON_MGMT_TX_RING_SIZE) - 1)) {
965 spin_unlock_irqrestore(&p->tx_list.lock, flags);
966 netif_stop_queue(netdev);
967 spin_lock_irqsave(&p->tx_list.lock, flags);
968 }
969
970 if (unlikely(p->tx_current_fill >=
971 ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) {
972 spin_unlock_irqrestore(&p->tx_list.lock, flags);
973 dma_unmap_single(p->dev, re.s.addr, re.s.len,
974 DMA_TO_DEVICE);
975 goto out;
976 }
977
978 __skb_queue_tail(&p->tx_list, skb);
979
980 /* Put it in the ring. */
981 p->tx_ring[p->tx_next] = re.d64;
982 p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE;
983 p->tx_current_fill++;
984
985 spin_unlock_irqrestore(&p->tx_list.lock, flags);
986
987 dma_sync_single_for_device(p->dev, p->tx_ring_handle,
988 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
989 DMA_BIDIRECTIONAL);
990
991 netdev->stats.tx_packets++;
992 netdev->stats.tx_bytes += skb->len;
993
994 /* Ring the bell. */
995 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
996
997 rv = NETDEV_TX_OK;
998 out:
999 octeon_mgmt_update_tx_stats(netdev);
1000 return rv;
1001 }
1002
1003 #ifdef CONFIG_NET_POLL_CONTROLLER
1004 static void octeon_mgmt_poll_controller(struct net_device *netdev)
1005 {
1006 struct octeon_mgmt *p = netdev_priv(netdev);
1007
1008 octeon_mgmt_receive_packets(p, 16);
1009 octeon_mgmt_update_rx_stats(netdev);
1010 }
1011 #endif
1012
1013 static void octeon_mgmt_get_drvinfo(struct net_device *netdev,
1014 struct ethtool_drvinfo *info)
1015 {
1016 strncpy(info->driver, DRV_NAME, sizeof(info->driver));
1017 strncpy(info->version, DRV_VERSION, sizeof(info->version));
1018 strncpy(info->fw_version, "N/A", sizeof(info->fw_version));
1019 strncpy(info->bus_info, "N/A", sizeof(info->bus_info));
1020 info->n_stats = 0;
1021 info->testinfo_len = 0;
1022 info->regdump_len = 0;
1023 info->eedump_len = 0;
1024 }
1025
1026 static int octeon_mgmt_get_settings(struct net_device *netdev,
1027 struct ethtool_cmd *cmd)
1028 {
1029 struct octeon_mgmt *p = netdev_priv(netdev);
1030
1031 if (p->phydev)
1032 return phy_ethtool_gset(p->phydev, cmd);
1033
1034 return -EINVAL;
1035 }
1036
1037 static int octeon_mgmt_set_settings(struct net_device *netdev,
1038 struct ethtool_cmd *cmd)
1039 {
1040 struct octeon_mgmt *p = netdev_priv(netdev);
1041
1042 if (!capable(CAP_NET_ADMIN))
1043 return -EPERM;
1044
1045 if (p->phydev)
1046 return phy_ethtool_sset(p->phydev, cmd);
1047
1048 return -EINVAL;
1049 }
1050
1051 static const struct ethtool_ops octeon_mgmt_ethtool_ops = {
1052 .get_drvinfo = octeon_mgmt_get_drvinfo,
1053 .get_link = ethtool_op_get_link,
1054 .get_settings = octeon_mgmt_get_settings,
1055 .set_settings = octeon_mgmt_set_settings
1056 };
1057
1058 static const struct net_device_ops octeon_mgmt_ops = {
1059 .ndo_open = octeon_mgmt_open,
1060 .ndo_stop = octeon_mgmt_stop,
1061 .ndo_start_xmit = octeon_mgmt_xmit,
1062 .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering,
1063 .ndo_set_mac_address = octeon_mgmt_set_mac_address,
1064 .ndo_do_ioctl = octeon_mgmt_ioctl,
1065 .ndo_change_mtu = octeon_mgmt_change_mtu,
1066 #ifdef CONFIG_NET_POLL_CONTROLLER
1067 .ndo_poll_controller = octeon_mgmt_poll_controller,
1068 #endif
1069 };
1070
1071 static int __devinit octeon_mgmt_probe(struct platform_device *pdev)
1072 {
1073 struct resource *res_irq;
1074 struct net_device *netdev;
1075 struct octeon_mgmt *p;
1076 int i;
1077
1078 netdev = alloc_etherdev(sizeof(struct octeon_mgmt));
1079 if (netdev == NULL)
1080 return -ENOMEM;
1081
1082 dev_set_drvdata(&pdev->dev, netdev);
1083 p = netdev_priv(netdev);
1084 netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll,
1085 OCTEON_MGMT_NAPI_WEIGHT);
1086
1087 p->netdev = netdev;
1088 p->dev = &pdev->dev;
1089
1090 p->port = pdev->id;
1091 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
1092
1093 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1094 if (!res_irq)
1095 goto err;
1096
1097 p->irq = res_irq->start;
1098 spin_lock_init(&p->lock);
1099
1100 skb_queue_head_init(&p->tx_list);
1101 skb_queue_head_init(&p->rx_list);
1102 tasklet_init(&p->tx_clean_tasklet,
1103 octeon_mgmt_clean_tx_tasklet, (unsigned long)p);
1104
1105 netdev->priv_flags |= IFF_UNICAST_FLT;
1106
1107 netdev->netdev_ops = &octeon_mgmt_ops;
1108 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;
1109
1110 /* The mgmt ports get the first N MACs. */
1111 for (i = 0; i < 6; i++)
1112 netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i];
1113 netdev->dev_addr[5] += p->port;
1114
1115 if (p->port >= octeon_bootinfo->mac_addr_count)
1116 dev_err(&pdev->dev,
1117 "Error %s: Using MAC outside of the assigned range: %pM\n",
1118 netdev->name, netdev->dev_addr);
1119
1120 if (register_netdev(netdev))
1121 goto err;
1122
1123 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
1124 return 0;
1125 err:
1126 free_netdev(netdev);
1127 return -ENOENT;
1128 }
1129
1130 static int __devexit octeon_mgmt_remove(struct platform_device *pdev)
1131 {
1132 struct net_device *netdev = dev_get_drvdata(&pdev->dev);
1133
1134 unregister_netdev(netdev);
1135 free_netdev(netdev);
1136 return 0;
1137 }
1138
1139 static struct platform_driver octeon_mgmt_driver = {
1140 .driver = {
1141 .name = "octeon_mgmt",
1142 .owner = THIS_MODULE,
1143 },
1144 .probe = octeon_mgmt_probe,
1145 .remove = __devexit_p(octeon_mgmt_remove),
1146 };
1147
1148 extern void octeon_mdiobus_force_mod_depencency(void);
1149
1150 static int __init octeon_mgmt_mod_init(void)
1151 {
1152 /* Force our mdiobus driver module to be loaded first. */
1153 octeon_mdiobus_force_mod_depencency();
1154 return platform_driver_register(&octeon_mgmt_driver);
1155 }
1156
1157 static void __exit octeon_mgmt_mod_exit(void)
1158 {
1159 platform_driver_unregister(&octeon_mgmt_driver);
1160 }
1161
1162 module_init(octeon_mgmt_mod_init);
1163 module_exit(octeon_mgmt_mod_exit);
1164
1165 MODULE_DESCRIPTION(DRV_DESCRIPTION);
1166 MODULE_AUTHOR("David Daney");
1167 MODULE_LICENSE("GPL");
1168 MODULE_VERSION(DRV_VERSION);
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