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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / net / ethernet / oki-semi / pch_gbe / pch_gbe_main.c
blobb89f3a684aec4dbb1cb83d0ef7d59e0ffc567330
1 /*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include "pch_gbe.h"
22 #include "pch_gbe_api.h"
23
24 #define DRV_VERSION "1.00"
25 const char pch_driver_version[] = DRV_VERSION;
26
27 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
28 #define PCH_GBE_MAR_ENTRIES 16
29 #define PCH_GBE_SHORT_PKT 64
30 #define DSC_INIT16 0xC000
31 #define PCH_GBE_DMA_ALIGN 0
32 #define PCH_GBE_DMA_PADDING 2
33 #define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */
34 #define PCH_GBE_COPYBREAK_DEFAULT 256
35 #define PCH_GBE_PCI_BAR 1
36 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
37
38 /* Macros for ML7223 */
39 #define PCI_VENDOR_ID_ROHM 0x10db
40 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
41
42 /* Macros for ML7831 */
43 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
44
45 #define PCH_GBE_TX_WEIGHT 64
46 #define PCH_GBE_RX_WEIGHT 64
47 #define PCH_GBE_RX_BUFFER_WRITE 16
48
49 /* Initialize the wake-on-LAN settings */
50 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
51
52 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
53 PCH_GBE_CHIP_TYPE_INTERNAL | \
54 PCH_GBE_RGMII_MODE_RGMII \
55 )
56
57 /* Ethertype field values */
58 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
59 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
60 #define PCH_GBE_FRAME_SIZE_2048 2048
61 #define PCH_GBE_FRAME_SIZE_4096 4096
62 #define PCH_GBE_FRAME_SIZE_8192 8192
63
64 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
65 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
66 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
67 #define PCH_GBE_DESC_UNUSED(R) \
68 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
69 (R)->next_to_clean - (R)->next_to_use - 1)
70
71 /* Pause packet value */
72 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
73 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
74 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
75 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
76
77 #define PCH_GBE_ETH_ALEN 6
78
79 /* This defines the bits that are set in the Interrupt Mask
80 * Set/Read Register. Each bit is documented below:
81 * o RXT0 = Receiver Timer Interrupt (ring 0)
82 * o TXDW = Transmit Descriptor Written Back
83 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
84 * o RXSEQ = Receive Sequence Error
85 * o LSC = Link Status Change
86 */
87 #define PCH_GBE_INT_ENABLE_MASK ( \
88 PCH_GBE_INT_RX_DMA_CMPLT | \
89 PCH_GBE_INT_RX_DSC_EMP | \
90 PCH_GBE_INT_RX_FIFO_ERR | \
91 PCH_GBE_INT_WOL_DET | \
92 PCH_GBE_INT_TX_CMPLT \
93 )
94
95 #define PCH_GBE_INT_DISABLE_ALL 0
96
97 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
98
99 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
100 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
101 int data);
102
103 inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
104 {
105 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
106 }
107
108 /**
109 * pch_gbe_mac_read_mac_addr - Read MAC address
110 * @hw: Pointer to the HW structure
111 * Returns
112 * 0: Successful.
113 */
114 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
115 {
116 u32 adr1a, adr1b;
117
118 adr1a = ioread32(&hw->reg->mac_adr[0].high);
119 adr1b = ioread32(&hw->reg->mac_adr[0].low);
120
121 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
122 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
123 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
124 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
125 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
126 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
127
128 pr_debug("hw->mac.addr : %pM\n", hw->mac.addr);
129 return 0;
130 }
131
132 /**
133 * pch_gbe_wait_clr_bit - Wait to clear a bit
134 * @reg: Pointer of register
135 * @busy: Busy bit
136 */
137 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
138 {
139 u32 tmp;
140 /* wait busy */
141 tmp = 1000;
142 while ((ioread32(reg) & bit) && --tmp)
143 cpu_relax();
144 if (!tmp)
145 pr_err("Error: busy bit is not cleared\n");
146 }
147
148 /**
149 * pch_gbe_wait_clr_bit_irq - Wait to clear a bit for interrupt context
150 * @reg: Pointer of register
151 * @busy: Busy bit
152 */
153 static int pch_gbe_wait_clr_bit_irq(void *reg, u32 bit)
154 {
155 u32 tmp;
156 int ret = -1;
157 /* wait busy */
158 tmp = 20;
159 while ((ioread32(reg) & bit) && --tmp)
160 udelay(5);
161 if (!tmp)
162 pr_err("Error: busy bit is not cleared\n");
163 else
164 ret = 0;
165 return ret;
166 }
167
168 /**
169 * pch_gbe_mac_mar_set - Set MAC address register
170 * @hw: Pointer to the HW structure
171 * @addr: Pointer to the MAC address
172 * @index: MAC address array register
173 */
174 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
175 {
176 u32 mar_low, mar_high, adrmask;
177
178 pr_debug("index : 0x%x\n", index);
179
180 /*
181 * HW expects these in little endian so we reverse the byte order
182 * from network order (big endian) to little endian
183 */
184 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
185 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
186 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
187 /* Stop the MAC Address of index. */
188 adrmask = ioread32(&hw->reg->ADDR_MASK);
189 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
190 /* wait busy */
191 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
192 /* Set the MAC address to the MAC address 1A/1B register */
193 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
194 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
195 /* Start the MAC address of index */
196 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
197 /* wait busy */
198 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
199 }
200
201 /**
202 * pch_gbe_mac_reset_hw - Reset hardware
203 * @hw: Pointer to the HW structure
204 */
205 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
206 {
207 /* Read the MAC address. and store to the private data */
208 pch_gbe_mac_read_mac_addr(hw);
209 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
210 #ifdef PCH_GBE_MAC_IFOP_RGMII
211 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
212 #endif
213 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
214 /* Setup the receive address */
215 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
216 return;
217 }
218
219 static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw)
220 {
221 /* Read the MAC address. and store to the private data */
222 pch_gbe_mac_read_mac_addr(hw);
223 iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET);
224 pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST);
225 /* Setup the MAC address */
226 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
227 return;
228 }
229
230 /**
231 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
232 * @hw: Pointer to the HW structure
233 * @mar_count: Receive address registers
234 */
235 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
236 {
237 u32 i;
238
239 /* Setup the receive address */
240 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
241
242 /* Zero out the other receive addresses */
243 for (i = 1; i < mar_count; i++) {
244 iowrite32(0, &hw->reg->mac_adr[i].high);
245 iowrite32(0, &hw->reg->mac_adr[i].low);
246 }
247 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
248 /* wait busy */
249 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
250 }
251
252
253 /**
254 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
255 * @hw: Pointer to the HW structure
256 * @mc_addr_list: Array of multicast addresses to program
257 * @mc_addr_count: Number of multicast addresses to program
258 * @mar_used_count: The first MAC Address register free to program
259 * @mar_total_num: Total number of supported MAC Address Registers
260 */
261 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
262 u8 *mc_addr_list, u32 mc_addr_count,
263 u32 mar_used_count, u32 mar_total_num)
264 {
265 u32 i, adrmask;
266
267 /* Load the first set of multicast addresses into the exact
268 * filters (RAR). If there are not enough to fill the RAR
269 * array, clear the filters.
270 */
271 for (i = mar_used_count; i < mar_total_num; i++) {
272 if (mc_addr_count) {
273 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
274 mc_addr_count--;
275 mc_addr_list += PCH_GBE_ETH_ALEN;
276 } else {
277 /* Clear MAC address mask */
278 adrmask = ioread32(&hw->reg->ADDR_MASK);
279 iowrite32((adrmask | (0x0001 << i)),
280 &hw->reg->ADDR_MASK);
281 /* wait busy */
282 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
283 /* Clear MAC address */
284 iowrite32(0, &hw->reg->mac_adr[i].high);
285 iowrite32(0, &hw->reg->mac_adr[i].low);
286 }
287 }
288 }
289
290 /**
291 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
292 * @hw: Pointer to the HW structure
293 * Returns
294 * 0: Successful.
295 * Negative value: Failed.
296 */
297 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
298 {
299 struct pch_gbe_mac_info *mac = &hw->mac;
300 u32 rx_fctrl;
301
302 pr_debug("mac->fc = %u\n", mac->fc);
303
304 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
305
306 switch (mac->fc) {
307 case PCH_GBE_FC_NONE:
308 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
309 mac->tx_fc_enable = false;
310 break;
311 case PCH_GBE_FC_RX_PAUSE:
312 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
313 mac->tx_fc_enable = false;
314 break;
315 case PCH_GBE_FC_TX_PAUSE:
316 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
317 mac->tx_fc_enable = true;
318 break;
319 case PCH_GBE_FC_FULL:
320 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
321 mac->tx_fc_enable = true;
322 break;
323 default:
324 pr_err("Flow control param set incorrectly\n");
325 return -EINVAL;
326 }
327 if (mac->link_duplex == DUPLEX_HALF)
328 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
329 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
330 pr_debug("RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
331 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
332 return 0;
333 }
334
335 /**
336 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
337 * @hw: Pointer to the HW structure
338 * @wu_evt: Wake up event
339 */
340 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
341 {
342 u32 addr_mask;
343
344 pr_debug("wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
345 wu_evt, ioread32(&hw->reg->ADDR_MASK));
346
347 if (wu_evt) {
348 /* Set Wake-On-Lan address mask */
349 addr_mask = ioread32(&hw->reg->ADDR_MASK);
350 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
351 /* wait busy */
352 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
353 iowrite32(0, &hw->reg->WOL_ST);
354 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
355 iowrite32(0x02, &hw->reg->TCPIP_ACC);
356 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
357 } else {
358 iowrite32(0, &hw->reg->WOL_CTRL);
359 iowrite32(0, &hw->reg->WOL_ST);
360 }
361 return;
362 }
363
364 /**
365 * pch_gbe_mac_ctrl_miim - Control MIIM interface
366 * @hw: Pointer to the HW structure
367 * @addr: Address of PHY
368 * @dir: Operetion. (Write or Read)
369 * @reg: Access register of PHY
370 * @data: Write data.
371 *
372 * Returns: Read date.
373 */
374 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
375 u16 data)
376 {
377 u32 data_out = 0;
378 unsigned int i;
379 unsigned long flags;
380
381 spin_lock_irqsave(&hw->miim_lock, flags);
382
383 for (i = 100; i; --i) {
384 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
385 break;
386 udelay(20);
387 }
388 if (i == 0) {
389 pr_err("pch-gbe.miim won't go Ready\n");
390 spin_unlock_irqrestore(&hw->miim_lock, flags);
391 return 0; /* No way to indicate timeout error */
392 }
393 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
394 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
395 dir | data), &hw->reg->MIIM);
396 for (i = 0; i < 100; i++) {
397 udelay(20);
398 data_out = ioread32(&hw->reg->MIIM);
399 if ((data_out & PCH_GBE_MIIM_OPER_READY))
400 break;
401 }
402 spin_unlock_irqrestore(&hw->miim_lock, flags);
403
404 pr_debug("PHY %s: reg=%d, data=0x%04X\n",
405 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
406 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
407 return (u16) data_out;
408 }
409
410 /**
411 * pch_gbe_mac_set_pause_packet - Set pause packet
412 * @hw: Pointer to the HW structure
413 */
414 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
415 {
416 unsigned long tmp2, tmp3;
417
418 /* Set Pause packet */
419 tmp2 = hw->mac.addr[1];
420 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
421 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
422
423 tmp3 = hw->mac.addr[5];
424 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
425 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
426 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
427
428 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
429 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
430 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
431 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
432 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
433
434 /* Transmit Pause Packet */
435 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
436
437 pr_debug("PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
438 ioread32(&hw->reg->PAUSE_PKT1), ioread32(&hw->reg->PAUSE_PKT2),
439 ioread32(&hw->reg->PAUSE_PKT3), ioread32(&hw->reg->PAUSE_PKT4),
440 ioread32(&hw->reg->PAUSE_PKT5));
441
442 return;
443 }
444
445
446 /**
447 * pch_gbe_alloc_queues - Allocate memory for all rings
448 * @adapter: Board private structure to initialize
449 * Returns
450 * 0: Successfully
451 * Negative value: Failed
452 */
453 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
454 {
455 int size;
456
457 size = (int)sizeof(struct pch_gbe_tx_ring);
458 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
459 if (!adapter->tx_ring)
460 return -ENOMEM;
461 size = (int)sizeof(struct pch_gbe_rx_ring);
462 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
463 if (!adapter->rx_ring) {
464 kfree(adapter->tx_ring);
465 return -ENOMEM;
466 }
467 return 0;
468 }
469
470 /**
471 * pch_gbe_init_stats - Initialize status
472 * @adapter: Board private structure to initialize
473 */
474 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
475 {
476 memset(&adapter->stats, 0, sizeof(adapter->stats));
477 return;
478 }
479
480 /**
481 * pch_gbe_init_phy - Initialize PHY
482 * @adapter: Board private structure to initialize
483 * Returns
484 * 0: Successfully
485 * Negative value: Failed
486 */
487 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
488 {
489 struct net_device *netdev = adapter->netdev;
490 u32 addr;
491 u16 bmcr, stat;
492
493 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
494 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
495 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
496 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
497 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
498 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
499 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
500 break;
501 }
502 adapter->hw.phy.addr = adapter->mii.phy_id;
503 pr_debug("phy_addr = %d\n", adapter->mii.phy_id);
504 if (addr == 32)
505 return -EAGAIN;
506 /* Selected the phy and isolate the rest */
507 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
508 if (addr != adapter->mii.phy_id) {
509 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
510 BMCR_ISOLATE);
511 } else {
512 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
513 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
514 bmcr & ~BMCR_ISOLATE);
515 }
516 }
517
518 /* MII setup */
519 adapter->mii.phy_id_mask = 0x1F;
520 adapter->mii.reg_num_mask = 0x1F;
521 adapter->mii.dev = adapter->netdev;
522 adapter->mii.mdio_read = pch_gbe_mdio_read;
523 adapter->mii.mdio_write = pch_gbe_mdio_write;
524 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
525 return 0;
526 }
527
528 /**
529 * pch_gbe_mdio_read - The read function for mii
530 * @netdev: Network interface device structure
531 * @addr: Phy ID
532 * @reg: Access location
533 * Returns
534 * 0: Successfully
535 * Negative value: Failed
536 */
537 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
538 {
539 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
540 struct pch_gbe_hw *hw = &adapter->hw;
541
542 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
543 (u16) 0);
544 }
545
546 /**
547 * pch_gbe_mdio_write - The write function for mii
548 * @netdev: Network interface device structure
549 * @addr: Phy ID (not used)
550 * @reg: Access location
551 * @data: Write data
552 */
553 static void pch_gbe_mdio_write(struct net_device *netdev,
554 int addr, int reg, int data)
555 {
556 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
557 struct pch_gbe_hw *hw = &adapter->hw;
558
559 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
560 }
561
562 /**
563 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
564 * @work: Pointer of board private structure
565 */
566 static void pch_gbe_reset_task(struct work_struct *work)
567 {
568 struct pch_gbe_adapter *adapter;
569 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
570
571 rtnl_lock();
572 pch_gbe_reinit_locked(adapter);
573 rtnl_unlock();
574 }
575
576 /**
577 * pch_gbe_reinit_locked- Re-initialization
578 * @adapter: Board private structure
579 */
580 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
581 {
582 pch_gbe_down(adapter);
583 pch_gbe_up(adapter);
584 }
585
586 /**
587 * pch_gbe_reset - Reset GbE
588 * @adapter: Board private structure
589 */
590 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
591 {
592 pch_gbe_mac_reset_hw(&adapter->hw);
593 /* Setup the receive address. */
594 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
595 if (pch_gbe_hal_init_hw(&adapter->hw))
596 pr_err("Hardware Error\n");
597 }
598
599 /**
600 * pch_gbe_free_irq - Free an interrupt
601 * @adapter: Board private structure
602 */
603 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
604 {
605 struct net_device *netdev = adapter->netdev;
606
607 free_irq(adapter->pdev->irq, netdev);
608 if (adapter->have_msi) {
609 pci_disable_msi(adapter->pdev);
610 pr_debug("call pci_disable_msi\n");
611 }
612 }
613
614 /**
615 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
616 * @adapter: Board private structure
617 */
618 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
619 {
620 struct pch_gbe_hw *hw = &adapter->hw;
621
622 atomic_inc(&adapter->irq_sem);
623 iowrite32(0, &hw->reg->INT_EN);
624 ioread32(&hw->reg->INT_ST);
625 synchronize_irq(adapter->pdev->irq);
626
627 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
628 }
629
630 /**
631 * pch_gbe_irq_enable - Enable default interrupt generation settings
632 * @adapter: Board private structure
633 */
634 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
635 {
636 struct pch_gbe_hw *hw = &adapter->hw;
637
638 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
639 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
640 ioread32(&hw->reg->INT_ST);
641 pr_debug("INT_EN reg : 0x%08x\n", ioread32(&hw->reg->INT_EN));
642 }
643
644
645
646 /**
647 * pch_gbe_setup_tctl - configure the Transmit control registers
648 * @adapter: Board private structure
649 */
650 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
651 {
652 struct pch_gbe_hw *hw = &adapter->hw;
653 u32 tx_mode, tcpip;
654
655 tx_mode = PCH_GBE_TM_LONG_PKT |
656 PCH_GBE_TM_ST_AND_FD |
657 PCH_GBE_TM_SHORT_PKT |
658 PCH_GBE_TM_TH_TX_STRT_8 |
659 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
660
661 iowrite32(tx_mode, &hw->reg->TX_MODE);
662
663 tcpip = ioread32(&hw->reg->TCPIP_ACC);
664 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
665 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
666 return;
667 }
668
669 /**
670 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
671 * @adapter: Board private structure
672 */
673 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
674 {
675 struct pch_gbe_hw *hw = &adapter->hw;
676 u32 tdba, tdlen, dctrl;
677
678 pr_debug("dma addr = 0x%08llx size = 0x%08x\n",
679 (unsigned long long)adapter->tx_ring->dma,
680 adapter->tx_ring->size);
681
682 /* Setup the HW Tx Head and Tail descriptor pointers */
683 tdba = adapter->tx_ring->dma;
684 tdlen = adapter->tx_ring->size - 0x10;
685 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
686 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
687 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
688
689 /* Enables Transmission DMA */
690 dctrl = ioread32(&hw->reg->DMA_CTRL);
691 dctrl |= PCH_GBE_TX_DMA_EN;
692 iowrite32(dctrl, &hw->reg->DMA_CTRL);
693 }
694
695 /**
696 * pch_gbe_setup_rctl - Configure the receive control registers
697 * @adapter: Board private structure
698 */
699 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
700 {
701 struct pch_gbe_hw *hw = &adapter->hw;
702 u32 rx_mode, tcpip;
703
704 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
705 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
706
707 iowrite32(rx_mode, &hw->reg->RX_MODE);
708
709 tcpip = ioread32(&hw->reg->TCPIP_ACC);
710
711 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
712 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
713 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
714 return;
715 }
716
717 /**
718 * pch_gbe_configure_rx - Configure Receive Unit after Reset
719 * @adapter: Board private structure
720 */
721 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
722 {
723 struct pch_gbe_hw *hw = &adapter->hw;
724 u32 rdba, rdlen, rctl, rxdma;
725
726 pr_debug("dma adr = 0x%08llx size = 0x%08x\n",
727 (unsigned long long)adapter->rx_ring->dma,
728 adapter->rx_ring->size);
729
730 pch_gbe_mac_force_mac_fc(hw);
731
732 /* Disables Receive MAC */
733 rctl = ioread32(&hw->reg->MAC_RX_EN);
734 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
735
736 /* Disables Receive DMA */
737 rxdma = ioread32(&hw->reg->DMA_CTRL);
738 rxdma &= ~PCH_GBE_RX_DMA_EN;
739 iowrite32(rxdma, &hw->reg->DMA_CTRL);
740
741 pr_debug("MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
742 ioread32(&hw->reg->MAC_RX_EN),
743 ioread32(&hw->reg->DMA_CTRL));
744
745 /* Setup the HW Rx Head and Tail Descriptor Pointers and
746 * the Base and Length of the Rx Descriptor Ring */
747 rdba = adapter->rx_ring->dma;
748 rdlen = adapter->rx_ring->size - 0x10;
749 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
750 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
751 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
752 }
753
754 /**
755 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
756 * @adapter: Board private structure
757 * @buffer_info: Buffer information structure
758 */
759 static void pch_gbe_unmap_and_free_tx_resource(
760 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
761 {
762 if (buffer_info->mapped) {
763 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
764 buffer_info->length, DMA_TO_DEVICE);
765 buffer_info->mapped = false;
766 }
767 if (buffer_info->skb) {
768 dev_kfree_skb_any(buffer_info->skb);
769 buffer_info->skb = NULL;
770 }
771 }
772
773 /**
774 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
775 * @adapter: Board private structure
776 * @buffer_info: Buffer information structure
777 */
778 static void pch_gbe_unmap_and_free_rx_resource(
779 struct pch_gbe_adapter *adapter,
780 struct pch_gbe_buffer *buffer_info)
781 {
782 if (buffer_info->mapped) {
783 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
784 buffer_info->length, DMA_FROM_DEVICE);
785 buffer_info->mapped = false;
786 }
787 if (buffer_info->skb) {
788 dev_kfree_skb_any(buffer_info->skb);
789 buffer_info->skb = NULL;
790 }
791 }
792
793 /**
794 * pch_gbe_clean_tx_ring - Free Tx Buffers
795 * @adapter: Board private structure
796 * @tx_ring: Ring to be cleaned
797 */
798 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
799 struct pch_gbe_tx_ring *tx_ring)
800 {
801 struct pch_gbe_hw *hw = &adapter->hw;
802 struct pch_gbe_buffer *buffer_info;
803 unsigned long size;
804 unsigned int i;
805
806 /* Free all the Tx ring sk_buffs */
807 for (i = 0; i < tx_ring->count; i++) {
808 buffer_info = &tx_ring->buffer_info[i];
809 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
810 }
811 pr_debug("call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
812
813 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
814 memset(tx_ring->buffer_info, 0, size);
815
816 /* Zero out the descriptor ring */
817 memset(tx_ring->desc, 0, tx_ring->size);
818 tx_ring->next_to_use = 0;
819 tx_ring->next_to_clean = 0;
820 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
821 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
822 }
823
824 /**
825 * pch_gbe_clean_rx_ring - Free Rx Buffers
826 * @adapter: Board private structure
827 * @rx_ring: Ring to free buffers from
828 */
829 static void
830 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
831 struct pch_gbe_rx_ring *rx_ring)
832 {
833 struct pch_gbe_hw *hw = &adapter->hw;
834 struct pch_gbe_buffer *buffer_info;
835 unsigned long size;
836 unsigned int i;
837
838 /* Free all the Rx ring sk_buffs */
839 for (i = 0; i < rx_ring->count; i++) {
840 buffer_info = &rx_ring->buffer_info[i];
841 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
842 }
843 pr_debug("call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
844 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
845 memset(rx_ring->buffer_info, 0, size);
846
847 /* Zero out the descriptor ring */
848 memset(rx_ring->desc, 0, rx_ring->size);
849 rx_ring->next_to_clean = 0;
850 rx_ring->next_to_use = 0;
851 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
852 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
853 }
854
855 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
856 u16 duplex)
857 {
858 struct pch_gbe_hw *hw = &adapter->hw;
859 unsigned long rgmii = 0;
860
861 /* Set the RGMII control. */
862 #ifdef PCH_GBE_MAC_IFOP_RGMII
863 switch (speed) {
864 case SPEED_10:
865 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
866 PCH_GBE_MAC_RGMII_CTRL_SETTING);
867 break;
868 case SPEED_100:
869 rgmii = (PCH_GBE_RGMII_RATE_25M |
870 PCH_GBE_MAC_RGMII_CTRL_SETTING);
871 break;
872 case SPEED_1000:
873 rgmii = (PCH_GBE_RGMII_RATE_125M |
874 PCH_GBE_MAC_RGMII_CTRL_SETTING);
875 break;
876 }
877 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
878 #else /* GMII */
879 rgmii = 0;
880 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
881 #endif
882 }
883 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
884 u16 duplex)
885 {
886 struct net_device *netdev = adapter->netdev;
887 struct pch_gbe_hw *hw = &adapter->hw;
888 unsigned long mode = 0;
889
890 /* Set the communication mode */
891 switch (speed) {
892 case SPEED_10:
893 mode = PCH_GBE_MODE_MII_ETHER;
894 netdev->tx_queue_len = 10;
895 break;
896 case SPEED_100:
897 mode = PCH_GBE_MODE_MII_ETHER;
898 netdev->tx_queue_len = 100;
899 break;
900 case SPEED_1000:
901 mode = PCH_GBE_MODE_GMII_ETHER;
902 break;
903 }
904 if (duplex == DUPLEX_FULL)
905 mode |= PCH_GBE_MODE_FULL_DUPLEX;
906 else
907 mode |= PCH_GBE_MODE_HALF_DUPLEX;
908 iowrite32(mode, &hw->reg->MODE);
909 }
910
911 /**
912 * pch_gbe_watchdog - Watchdog process
913 * @data: Board private structure
914 */
915 static void pch_gbe_watchdog(unsigned long data)
916 {
917 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
918 struct net_device *netdev = adapter->netdev;
919 struct pch_gbe_hw *hw = &adapter->hw;
920
921 pr_debug("right now = %ld\n", jiffies);
922
923 pch_gbe_update_stats(adapter);
924 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
925 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
926 netdev->tx_queue_len = adapter->tx_queue_len;
927 /* mii library handles link maintenance tasks */
928 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
929 pr_err("ethtool get setting Error\n");
930 mod_timer(&adapter->watchdog_timer,
931 round_jiffies(jiffies +
932 PCH_GBE_WATCHDOG_PERIOD));
933 return;
934 }
935 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
936 hw->mac.link_duplex = cmd.duplex;
937 /* Set the RGMII control. */
938 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
939 hw->mac.link_duplex);
940 /* Set the communication mode */
941 pch_gbe_set_mode(adapter, hw->mac.link_speed,
942 hw->mac.link_duplex);
943 netdev_dbg(netdev,
944 "Link is Up %d Mbps %s-Duplex\n",
945 hw->mac.link_speed,
946 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
947 netif_carrier_on(netdev);
948 netif_wake_queue(netdev);
949 } else if ((!mii_link_ok(&adapter->mii)) &&
950 (netif_carrier_ok(netdev))) {
951 netdev_dbg(netdev, "NIC Link is Down\n");
952 hw->mac.link_speed = SPEED_10;
953 hw->mac.link_duplex = DUPLEX_HALF;
954 netif_carrier_off(netdev);
955 netif_stop_queue(netdev);
956 }
957 mod_timer(&adapter->watchdog_timer,
958 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
959 }
960
961 /**
962 * pch_gbe_tx_queue - Carry out queuing of the transmission data
963 * @adapter: Board private structure
964 * @tx_ring: Tx descriptor ring structure
965 * @skb: Sockt buffer structure
966 */
967 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
968 struct pch_gbe_tx_ring *tx_ring,
969 struct sk_buff *skb)
970 {
971 struct pch_gbe_hw *hw = &adapter->hw;
972 struct pch_gbe_tx_desc *tx_desc;
973 struct pch_gbe_buffer *buffer_info;
974 struct sk_buff *tmp_skb;
975 unsigned int frame_ctrl;
976 unsigned int ring_num;
977 unsigned long flags;
978
979 /*-- Set frame control --*/
980 frame_ctrl = 0;
981 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
982 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
983 if (skb->ip_summed == CHECKSUM_NONE)
984 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
985
986 /* Performs checksum processing */
987 /*
988 * It is because the hardware accelerator does not support a checksum,
989 * when the received data size is less than 64 bytes.
990 */
991 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
992 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
993 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
994 if (skb->protocol == htons(ETH_P_IP)) {
995 struct iphdr *iph = ip_hdr(skb);
996 unsigned int offset;
997 iph->check = 0;
998 iph->check = ip_fast_csum((u8 *) iph, iph->ihl);
999 offset = skb_transport_offset(skb);
1000 if (iph->protocol == IPPROTO_TCP) {
1001 skb->csum = 0;
1002 tcp_hdr(skb)->check = 0;
1003 skb->csum = skb_checksum(skb, offset,
1004 skb->len - offset, 0);
1005 tcp_hdr(skb)->check =
1006 csum_tcpudp_magic(iph->saddr,
1007 iph->daddr,
1008 skb->len - offset,
1009 IPPROTO_TCP,
1010 skb->csum);
1011 } else if (iph->protocol == IPPROTO_UDP) {
1012 skb->csum = 0;
1013 udp_hdr(skb)->check = 0;
1014 skb->csum =
1015 skb_checksum(skb, offset,
1016 skb->len - offset, 0);
1017 udp_hdr(skb)->check =
1018 csum_tcpudp_magic(iph->saddr,
1019 iph->daddr,
1020 skb->len - offset,
1021 IPPROTO_UDP,
1022 skb->csum);
1023 }
1024 }
1025 }
1026 spin_lock_irqsave(&tx_ring->tx_lock, flags);
1027 ring_num = tx_ring->next_to_use;
1028 if (unlikely((ring_num + 1) == tx_ring->count))
1029 tx_ring->next_to_use = 0;
1030 else
1031 tx_ring->next_to_use = ring_num + 1;
1032
1033 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1034 buffer_info = &tx_ring->buffer_info[ring_num];
1035 tmp_skb = buffer_info->skb;
1036
1037 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1038 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1039 tmp_skb->data[ETH_HLEN] = 0x00;
1040 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1041 tmp_skb->len = skb->len;
1042 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1043 (skb->len - ETH_HLEN));
1044 /*-- Set Buffer information --*/
1045 buffer_info->length = tmp_skb->len;
1046 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1047 buffer_info->length,
1048 DMA_TO_DEVICE);
1049 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1050 pr_err("TX DMA map failed\n");
1051 buffer_info->dma = 0;
1052 buffer_info->time_stamp = 0;
1053 tx_ring->next_to_use = ring_num;
1054 return;
1055 }
1056 buffer_info->mapped = true;
1057 buffer_info->time_stamp = jiffies;
1058
1059 /*-- Set Tx descriptor --*/
1060 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1061 tx_desc->buffer_addr = (buffer_info->dma);
1062 tx_desc->length = (tmp_skb->len);
1063 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1064 tx_desc->tx_frame_ctrl = (frame_ctrl);
1065 tx_desc->gbec_status = (DSC_INIT16);
1066
1067 if (unlikely(++ring_num == tx_ring->count))
1068 ring_num = 0;
1069
1070 /* Update software pointer of TX descriptor */
1071 iowrite32(tx_ring->dma +
1072 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1073 &hw->reg->TX_DSC_SW_P);
1074 dev_kfree_skb_any(skb);
1075 }
1076
1077 /**
1078 * pch_gbe_update_stats - Update the board statistics counters
1079 * @adapter: Board private structure
1080 */
1081 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1082 {
1083 struct net_device *netdev = adapter->netdev;
1084 struct pci_dev *pdev = adapter->pdev;
1085 struct pch_gbe_hw_stats *stats = &adapter->stats;
1086 unsigned long flags;
1087
1088 /*
1089 * Prevent stats update while adapter is being reset, or if the pci
1090 * connection is down.
1091 */
1092 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1093 return;
1094
1095 spin_lock_irqsave(&adapter->stats_lock, flags);
1096
1097 /* Update device status "adapter->stats" */
1098 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1099 stats->tx_errors = stats->tx_length_errors +
1100 stats->tx_aborted_errors +
1101 stats->tx_carrier_errors + stats->tx_timeout_count;
1102
1103 /* Update network device status "adapter->net_stats" */
1104 netdev->stats.rx_packets = stats->rx_packets;
1105 netdev->stats.rx_bytes = stats->rx_bytes;
1106 netdev->stats.rx_dropped = stats->rx_dropped;
1107 netdev->stats.tx_packets = stats->tx_packets;
1108 netdev->stats.tx_bytes = stats->tx_bytes;
1109 netdev->stats.tx_dropped = stats->tx_dropped;
1110 /* Fill out the OS statistics structure */
1111 netdev->stats.multicast = stats->multicast;
1112 netdev->stats.collisions = stats->collisions;
1113 /* Rx Errors */
1114 netdev->stats.rx_errors = stats->rx_errors;
1115 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1116 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1117 /* Tx Errors */
1118 netdev->stats.tx_errors = stats->tx_errors;
1119 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1120 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1121
1122 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1123 }
1124
1125 static void pch_gbe_stop_receive(struct pch_gbe_adapter *adapter)
1126 {
1127 struct pch_gbe_hw *hw = &adapter->hw;
1128 u32 rxdma;
1129 u16 value;
1130 int ret;
1131
1132 /* Disable Receive DMA */
1133 rxdma = ioread32(&hw->reg->DMA_CTRL);
1134 rxdma &= ~PCH_GBE_RX_DMA_EN;
1135 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1136 /* Wait Rx DMA BUS is IDLE */
1137 ret = pch_gbe_wait_clr_bit_irq(&hw->reg->RX_DMA_ST, PCH_GBE_IDLE_CHECK);
1138 if (ret) {
1139 /* Disable Bus master */
1140 pci_read_config_word(adapter->pdev, PCI_COMMAND, &value);
1141 value &= ~PCI_COMMAND_MASTER;
1142 pci_write_config_word(adapter->pdev, PCI_COMMAND, value);
1143 /* Stop Receive */
1144 pch_gbe_mac_reset_rx(hw);
1145 /* Enable Bus master */
1146 value |= PCI_COMMAND_MASTER;
1147 pci_write_config_word(adapter->pdev, PCI_COMMAND, value);
1148 } else {
1149 /* Stop Receive */
1150 pch_gbe_mac_reset_rx(hw);
1151 }
1152 }
1153
1154 static void pch_gbe_start_receive(struct pch_gbe_hw *hw)
1155 {
1156 u32 rxdma;
1157
1158 /* Enables Receive DMA */
1159 rxdma = ioread32(&hw->reg->DMA_CTRL);
1160 rxdma |= PCH_GBE_RX_DMA_EN;
1161 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1162 /* Enables Receive */
1163 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
1164 return;
1165 }
1166
1167 /**
1168 * pch_gbe_intr - Interrupt Handler
1169 * @irq: Interrupt number
1170 * @data: Pointer to a network interface device structure
1171 * Returns
1172 * - IRQ_HANDLED: Our interrupt
1173 * - IRQ_NONE: Not our interrupt
1174 */
1175 static irqreturn_t pch_gbe_intr(int irq, void *data)
1176 {
1177 struct net_device *netdev = data;
1178 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1179 struct pch_gbe_hw *hw = &adapter->hw;
1180 u32 int_st;
1181 u32 int_en;
1182
1183 /* Check request status */
1184 int_st = ioread32(&hw->reg->INT_ST);
1185 int_st = int_st & ioread32(&hw->reg->INT_EN);
1186 /* When request status is no interruption factor */
1187 if (unlikely(!int_st))
1188 return IRQ_NONE; /* Not our interrupt. End processing. */
1189 pr_debug("%s occur int_st = 0x%08x\n", __func__, int_st);
1190 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1191 adapter->stats.intr_rx_frame_err_count++;
1192 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1193 if (!adapter->rx_stop_flag) {
1194 adapter->stats.intr_rx_fifo_err_count++;
1195 pr_debug("Rx fifo over run\n");
1196 adapter->rx_stop_flag = true;
1197 int_en = ioread32(&hw->reg->INT_EN);
1198 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1199 &hw->reg->INT_EN);
1200 pch_gbe_stop_receive(adapter);
1201 int_st |= ioread32(&hw->reg->INT_ST);
1202 int_st = int_st & ioread32(&hw->reg->INT_EN);
1203 }
1204 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1205 adapter->stats.intr_rx_dma_err_count++;
1206 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1207 adapter->stats.intr_tx_fifo_err_count++;
1208 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1209 adapter->stats.intr_tx_dma_err_count++;
1210 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1211 adapter->stats.intr_tcpip_err_count++;
1212 /* When Rx descriptor is empty */
1213 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1214 adapter->stats.intr_rx_dsc_empty_count++;
1215 pr_debug("Rx descriptor is empty\n");
1216 int_en = ioread32(&hw->reg->INT_EN);
1217 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1218 if (hw->mac.tx_fc_enable) {
1219 /* Set Pause packet */
1220 pch_gbe_mac_set_pause_packet(hw);
1221 }
1222 }
1223
1224 /* When request status is Receive interruption */
1225 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1226 (adapter->rx_stop_flag == true)) {
1227 if (likely(napi_schedule_prep(&adapter->napi))) {
1228 /* Enable only Rx Descriptor empty */
1229 atomic_inc(&adapter->irq_sem);
1230 int_en = ioread32(&hw->reg->INT_EN);
1231 int_en &=
1232 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1233 iowrite32(int_en, &hw->reg->INT_EN);
1234 /* Start polling for NAPI */
1235 __napi_schedule(&adapter->napi);
1236 }
1237 }
1238 pr_debug("return = 0x%08x INT_EN reg = 0x%08x\n",
1239 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1240 return IRQ_HANDLED;
1241 }
1242
1243 /**
1244 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1245 * @adapter: Board private structure
1246 * @rx_ring: Rx descriptor ring
1247 * @cleaned_count: Cleaned count
1248 */
1249 static void
1250 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1251 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1252 {
1253 struct net_device *netdev = adapter->netdev;
1254 struct pci_dev *pdev = adapter->pdev;
1255 struct pch_gbe_hw *hw = &adapter->hw;
1256 struct pch_gbe_rx_desc *rx_desc;
1257 struct pch_gbe_buffer *buffer_info;
1258 struct sk_buff *skb;
1259 unsigned int i;
1260 unsigned int bufsz;
1261
1262 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1263 i = rx_ring->next_to_use;
1264
1265 while ((cleaned_count--)) {
1266 buffer_info = &rx_ring->buffer_info[i];
1267 skb = netdev_alloc_skb(netdev, bufsz);
1268 if (unlikely(!skb)) {
1269 /* Better luck next round */
1270 adapter->stats.rx_alloc_buff_failed++;
1271 break;
1272 }
1273 /* align */
1274 skb_reserve(skb, NET_IP_ALIGN);
1275 buffer_info->skb = skb;
1276
1277 buffer_info->dma = dma_map_single(&pdev->dev,
1278 buffer_info->rx_buffer,
1279 buffer_info->length,
1280 DMA_FROM_DEVICE);
1281 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1282 dev_kfree_skb(skb);
1283 buffer_info->skb = NULL;
1284 buffer_info->dma = 0;
1285 adapter->stats.rx_alloc_buff_failed++;
1286 break; /* while !buffer_info->skb */
1287 }
1288 buffer_info->mapped = true;
1289 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1290 rx_desc->buffer_addr = (buffer_info->dma);
1291 rx_desc->gbec_status = DSC_INIT16;
1292
1293 pr_debug("i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1294 i, (unsigned long long)buffer_info->dma,
1295 buffer_info->length);
1296
1297 if (unlikely(++i == rx_ring->count))
1298 i = 0;
1299 }
1300 if (likely(rx_ring->next_to_use != i)) {
1301 rx_ring->next_to_use = i;
1302 if (unlikely(i-- == 0))
1303 i = (rx_ring->count - 1);
1304 iowrite32(rx_ring->dma +
1305 (int)sizeof(struct pch_gbe_rx_desc) * i,
1306 &hw->reg->RX_DSC_SW_P);
1307 }
1308 return;
1309 }
1310
1311 static int
1312 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1313 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1314 {
1315 struct pci_dev *pdev = adapter->pdev;
1316 struct pch_gbe_buffer *buffer_info;
1317 unsigned int i;
1318 unsigned int bufsz;
1319 unsigned int size;
1320
1321 bufsz = adapter->rx_buffer_len;
1322
1323 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1324 rx_ring->rx_buff_pool = dma_alloc_coherent(&pdev->dev, size,
1325 &rx_ring->rx_buff_pool_logic,
1326 GFP_KERNEL);
1327 if (!rx_ring->rx_buff_pool) {
1328 pr_err("Unable to allocate memory for the receive poll buffer\n");
1329 return -ENOMEM;
1330 }
1331 memset(rx_ring->rx_buff_pool, 0, size);
1332 rx_ring->rx_buff_pool_size = size;
1333 for (i = 0; i < rx_ring->count; i++) {
1334 buffer_info = &rx_ring->buffer_info[i];
1335 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1336 buffer_info->length = bufsz;
1337 }
1338 return 0;
1339 }
1340
1341 /**
1342 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1343 * @adapter: Board private structure
1344 * @tx_ring: Tx descriptor ring
1345 */
1346 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1347 struct pch_gbe_tx_ring *tx_ring)
1348 {
1349 struct pch_gbe_buffer *buffer_info;
1350 struct sk_buff *skb;
1351 unsigned int i;
1352 unsigned int bufsz;
1353 struct pch_gbe_tx_desc *tx_desc;
1354
1355 bufsz =
1356 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1357
1358 for (i = 0; i < tx_ring->count; i++) {
1359 buffer_info = &tx_ring->buffer_info[i];
1360 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1361 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1362 buffer_info->skb = skb;
1363 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1364 tx_desc->gbec_status = (DSC_INIT16);
1365 }
1366 return;
1367 }
1368
1369 /**
1370 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1371 * @adapter: Board private structure
1372 * @tx_ring: Tx descriptor ring
1373 * Returns
1374 * true: Cleaned the descriptor
1375 * false: Not cleaned the descriptor
1376 */
1377 static bool
1378 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1379 struct pch_gbe_tx_ring *tx_ring)
1380 {
1381 struct pch_gbe_tx_desc *tx_desc;
1382 struct pch_gbe_buffer *buffer_info;
1383 struct sk_buff *skb;
1384 unsigned int i;
1385 unsigned int cleaned_count = 0;
1386 bool cleaned = true;
1387
1388 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1389
1390 i = tx_ring->next_to_clean;
1391 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1392 pr_debug("gbec_status:0x%04x dma_status:0x%04x\n",
1393 tx_desc->gbec_status, tx_desc->dma_status);
1394
1395 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1396 pr_debug("gbec_status:0x%04x\n", tx_desc->gbec_status);
1397 buffer_info = &tx_ring->buffer_info[i];
1398 skb = buffer_info->skb;
1399
1400 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1401 adapter->stats.tx_aborted_errors++;
1402 pr_err("Transfer Abort Error\n");
1403 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1404 ) {
1405 adapter->stats.tx_carrier_errors++;
1406 pr_err("Transfer Carrier Sense Error\n");
1407 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1408 ) {
1409 adapter->stats.tx_aborted_errors++;
1410 pr_err("Transfer Collision Abort Error\n");
1411 } else if ((tx_desc->gbec_status &
1412 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1413 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1414 adapter->stats.collisions++;
1415 adapter->stats.tx_packets++;
1416 adapter->stats.tx_bytes += skb->len;
1417 pr_debug("Transfer Collision\n");
1418 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1419 ) {
1420 adapter->stats.tx_packets++;
1421 adapter->stats.tx_bytes += skb->len;
1422 }
1423 if (buffer_info->mapped) {
1424 pr_debug("unmap buffer_info->dma : %d\n", i);
1425 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1426 buffer_info->length, DMA_TO_DEVICE);
1427 buffer_info->mapped = false;
1428 }
1429 if (buffer_info->skb) {
1430 pr_debug("trim buffer_info->skb : %d\n", i);
1431 skb_trim(buffer_info->skb, 0);
1432 }
1433 tx_desc->gbec_status = DSC_INIT16;
1434 if (unlikely(++i == tx_ring->count))
1435 i = 0;
1436 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1437
1438 /* weight of a sort for tx, to avoid endless transmit cleanup */
1439 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1440 cleaned = false;
1441 break;
1442 }
1443 }
1444 pr_debug("called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1445 cleaned_count);
1446 /* Recover from running out of Tx resources in xmit_frame */
1447 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) {
1448 netif_wake_queue(adapter->netdev);
1449 adapter->stats.tx_restart_count++;
1450 pr_debug("Tx wake queue\n");
1451 }
1452 spin_lock(&adapter->tx_queue_lock);
1453 tx_ring->next_to_clean = i;
1454 spin_unlock(&adapter->tx_queue_lock);
1455 pr_debug("next_to_clean : %d\n", tx_ring->next_to_clean);
1456 return cleaned;
1457 }
1458
1459 /**
1460 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1461 * @adapter: Board private structure
1462 * @rx_ring: Rx descriptor ring
1463 * @work_done: Completed count
1464 * @work_to_do: Request count
1465 * Returns
1466 * true: Cleaned the descriptor
1467 * false: Not cleaned the descriptor
1468 */
1469 static bool
1470 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1471 struct pch_gbe_rx_ring *rx_ring,
1472 int *work_done, int work_to_do)
1473 {
1474 struct net_device *netdev = adapter->netdev;
1475 struct pci_dev *pdev = adapter->pdev;
1476 struct pch_gbe_buffer *buffer_info;
1477 struct pch_gbe_rx_desc *rx_desc;
1478 u32 length;
1479 unsigned int i;
1480 unsigned int cleaned_count = 0;
1481 bool cleaned = false;
1482 struct sk_buff *skb;
1483 u8 dma_status;
1484 u16 gbec_status;
1485 u32 tcp_ip_status;
1486
1487 i = rx_ring->next_to_clean;
1488
1489 while (*work_done < work_to_do) {
1490 /* Check Rx descriptor status */
1491 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1492 if (rx_desc->gbec_status == DSC_INIT16)
1493 break;
1494 cleaned = true;
1495 cleaned_count++;
1496
1497 dma_status = rx_desc->dma_status;
1498 gbec_status = rx_desc->gbec_status;
1499 tcp_ip_status = rx_desc->tcp_ip_status;
1500 rx_desc->gbec_status = DSC_INIT16;
1501 buffer_info = &rx_ring->buffer_info[i];
1502 skb = buffer_info->skb;
1503 buffer_info->skb = NULL;
1504
1505 /* unmap dma */
1506 dma_unmap_single(&pdev->dev, buffer_info->dma,
1507 buffer_info->length, DMA_FROM_DEVICE);
1508 buffer_info->mapped = false;
1509
1510 pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x "
1511 "TCP:0x%08x] BufInf = 0x%p\n",
1512 i, dma_status, gbec_status, tcp_ip_status,
1513 buffer_info);
1514 /* Error check */
1515 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1516 adapter->stats.rx_frame_errors++;
1517 pr_err("Receive Not Octal Error\n");
1518 } else if (unlikely(gbec_status &
1519 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1520 adapter->stats.rx_frame_errors++;
1521 pr_err("Receive Nibble Error\n");
1522 } else if (unlikely(gbec_status &
1523 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1524 adapter->stats.rx_crc_errors++;
1525 pr_err("Receive CRC Error\n");
1526 } else {
1527 /* get receive length */
1528 /* length convert[-3], length includes FCS length */
1529 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1530 if (rx_desc->rx_words_eob & 0x02)
1531 length = length - 4;
1532 /*
1533 * buffer_info->rx_buffer: [Header:14][payload]
1534 * skb->data: [Reserve:2][Header:14][payload]
1535 */
1536 memcpy(skb->data, buffer_info->rx_buffer, length);
1537
1538 /* update status of driver */
1539 adapter->stats.rx_bytes += length;
1540 adapter->stats.rx_packets++;
1541 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1542 adapter->stats.multicast++;
1543 /* Write meta date of skb */
1544 skb_put(skb, length);
1545 skb->protocol = eth_type_trans(skb, netdev);
1546 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1547 skb->ip_summed = CHECKSUM_NONE;
1548 else
1549 skb->ip_summed = CHECKSUM_UNNECESSARY;
1550
1551 napi_gro_receive(&adapter->napi, skb);
1552 (*work_done)++;
1553 pr_debug("Receive skb->ip_summed: %d length: %d\n",
1554 skb->ip_summed, length);
1555 }
1556 /* return some buffers to hardware, one at a time is too slow */
1557 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1558 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1559 cleaned_count);
1560 cleaned_count = 0;
1561 }
1562 if (++i == rx_ring->count)
1563 i = 0;
1564 }
1565 rx_ring->next_to_clean = i;
1566 if (cleaned_count)
1567 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1568 return cleaned;
1569 }
1570
1571 /**
1572 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1573 * @adapter: Board private structure
1574 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1575 * Returns
1576 * 0: Successfully
1577 * Negative value: Failed
1578 */
1579 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1580 struct pch_gbe_tx_ring *tx_ring)
1581 {
1582 struct pci_dev *pdev = adapter->pdev;
1583 struct pch_gbe_tx_desc *tx_desc;
1584 int size;
1585 int desNo;
1586
1587 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1588 tx_ring->buffer_info = vzalloc(size);
1589 if (!tx_ring->buffer_info) {
1590 pr_err("Unable to allocate memory for the buffer information\n");
1591 return -ENOMEM;
1592 }
1593
1594 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1595
1596 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1597 &tx_ring->dma, GFP_KERNEL);
1598 if (!tx_ring->desc) {
1599 vfree(tx_ring->buffer_info);
1600 pr_err("Unable to allocate memory for the transmit descriptor ring\n");
1601 return -ENOMEM;
1602 }
1603 memset(tx_ring->desc, 0, tx_ring->size);
1604
1605 tx_ring->next_to_use = 0;
1606 tx_ring->next_to_clean = 0;
1607 spin_lock_init(&tx_ring->tx_lock);
1608
1609 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1610 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1611 tx_desc->gbec_status = DSC_INIT16;
1612 }
1613 pr_debug("tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx\n"
1614 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1615 tx_ring->desc, (unsigned long long)tx_ring->dma,
1616 tx_ring->next_to_clean, tx_ring->next_to_use);
1617 return 0;
1618 }
1619
1620 /**
1621 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1622 * @adapter: Board private structure
1623 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1624 * Returns
1625 * 0: Successfully
1626 * Negative value: Failed
1627 */
1628 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1629 struct pch_gbe_rx_ring *rx_ring)
1630 {
1631 struct pci_dev *pdev = adapter->pdev;
1632 struct pch_gbe_rx_desc *rx_desc;
1633 int size;
1634 int desNo;
1635
1636 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1637 rx_ring->buffer_info = vzalloc(size);
1638 if (!rx_ring->buffer_info) {
1639 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1640 return -ENOMEM;
1641 }
1642 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1643 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1644 &rx_ring->dma, GFP_KERNEL);
1645
1646 if (!rx_ring->desc) {
1647 pr_err("Unable to allocate memory for the receive descriptor ring\n");
1648 vfree(rx_ring->buffer_info);
1649 return -ENOMEM;
1650 }
1651 memset(rx_ring->desc, 0, rx_ring->size);
1652 rx_ring->next_to_clean = 0;
1653 rx_ring->next_to_use = 0;
1654 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1655 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1656 rx_desc->gbec_status = DSC_INIT16;
1657 }
1658 pr_debug("rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx "
1659 "next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1660 rx_ring->desc, (unsigned long long)rx_ring->dma,
1661 rx_ring->next_to_clean, rx_ring->next_to_use);
1662 return 0;
1663 }
1664
1665 /**
1666 * pch_gbe_free_tx_resources - Free Tx Resources
1667 * @adapter: Board private structure
1668 * @tx_ring: Tx descriptor ring for a specific queue
1669 */
1670 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1671 struct pch_gbe_tx_ring *tx_ring)
1672 {
1673 struct pci_dev *pdev = adapter->pdev;
1674
1675 pch_gbe_clean_tx_ring(adapter, tx_ring);
1676 vfree(tx_ring->buffer_info);
1677 tx_ring->buffer_info = NULL;
1678 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1679 tx_ring->desc = NULL;
1680 }
1681
1682 /**
1683 * pch_gbe_free_rx_resources - Free Rx Resources
1684 * @adapter: Board private structure
1685 * @rx_ring: Ring to clean the resources from
1686 */
1687 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1688 struct pch_gbe_rx_ring *rx_ring)
1689 {
1690 struct pci_dev *pdev = adapter->pdev;
1691
1692 pch_gbe_clean_rx_ring(adapter, rx_ring);
1693 vfree(rx_ring->buffer_info);
1694 rx_ring->buffer_info = NULL;
1695 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1696 rx_ring->desc = NULL;
1697 }
1698
1699 /**
1700 * pch_gbe_request_irq - Allocate an interrupt line
1701 * @adapter: Board private structure
1702 * Returns
1703 * 0: Successfully
1704 * Negative value: Failed
1705 */
1706 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1707 {
1708 struct net_device *netdev = adapter->netdev;
1709 int err;
1710 int flags;
1711
1712 flags = IRQF_SHARED;
1713 adapter->have_msi = false;
1714 err = pci_enable_msi(adapter->pdev);
1715 pr_debug("call pci_enable_msi\n");
1716 if (err) {
1717 pr_debug("call pci_enable_msi - Error: %d\n", err);
1718 } else {
1719 flags = 0;
1720 adapter->have_msi = true;
1721 }
1722 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1723 flags, netdev->name, netdev);
1724 if (err)
1725 pr_err("Unable to allocate interrupt Error: %d\n", err);
1726 pr_debug("adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1727 adapter->have_msi, flags, err);
1728 return err;
1729 }
1730
1731
1732 static void pch_gbe_set_multi(struct net_device *netdev);
1733 /**
1734 * pch_gbe_up - Up GbE network device
1735 * @adapter: Board private structure
1736 * Returns
1737 * 0: Successfully
1738 * Negative value: Failed
1739 */
1740 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1741 {
1742 struct net_device *netdev = adapter->netdev;
1743 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1744 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1745 int err;
1746
1747 /* hardware has been reset, we need to reload some things */
1748 pch_gbe_set_multi(netdev);
1749
1750 pch_gbe_setup_tctl(adapter);
1751 pch_gbe_configure_tx(adapter);
1752 pch_gbe_setup_rctl(adapter);
1753 pch_gbe_configure_rx(adapter);
1754
1755 err = pch_gbe_request_irq(adapter);
1756 if (err) {
1757 pr_err("Error: can't bring device up\n");
1758 return err;
1759 }
1760 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1761 if (err) {
1762 pr_err("Error: can't bring device up\n");
1763 return err;
1764 }
1765 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1766 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1767 adapter->tx_queue_len = netdev->tx_queue_len;
1768 pch_gbe_start_receive(&adapter->hw);
1769
1770 mod_timer(&adapter->watchdog_timer, jiffies);
1771
1772 napi_enable(&adapter->napi);
1773 pch_gbe_irq_enable(adapter);
1774 netif_start_queue(adapter->netdev);
1775
1776 return 0;
1777 }
1778
1779 /**
1780 * pch_gbe_down - Down GbE network device
1781 * @adapter: Board private structure
1782 */
1783 void pch_gbe_down(struct pch_gbe_adapter *adapter)
1784 {
1785 struct net_device *netdev = adapter->netdev;
1786 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1787
1788 /* signal that we're down so the interrupt handler does not
1789 * reschedule our watchdog timer */
1790 napi_disable(&adapter->napi);
1791 atomic_set(&adapter->irq_sem, 0);
1792
1793 pch_gbe_irq_disable(adapter);
1794 pch_gbe_free_irq(adapter);
1795
1796 del_timer_sync(&adapter->watchdog_timer);
1797
1798 netdev->tx_queue_len = adapter->tx_queue_len;
1799 netif_carrier_off(netdev);
1800 netif_stop_queue(netdev);
1801
1802 pch_gbe_reset(adapter);
1803 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
1804 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
1805
1806 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
1807 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
1808 rx_ring->rx_buff_pool_logic = 0;
1809 rx_ring->rx_buff_pool_size = 0;
1810 rx_ring->rx_buff_pool = NULL;
1811 }
1812
1813 /**
1814 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
1815 * @adapter: Board private structure to initialize
1816 * Returns
1817 * 0: Successfully
1818 * Negative value: Failed
1819 */
1820 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
1821 {
1822 struct pch_gbe_hw *hw = &adapter->hw;
1823 struct net_device *netdev = adapter->netdev;
1824
1825 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
1826 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1827 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1828
1829 /* Initialize the hardware-specific values */
1830 if (pch_gbe_hal_setup_init_funcs(hw)) {
1831 pr_err("Hardware Initialization Failure\n");
1832 return -EIO;
1833 }
1834 if (pch_gbe_alloc_queues(adapter)) {
1835 pr_err("Unable to allocate memory for queues\n");
1836 return -ENOMEM;
1837 }
1838 spin_lock_init(&adapter->hw.miim_lock);
1839 spin_lock_init(&adapter->tx_queue_lock);
1840 spin_lock_init(&adapter->stats_lock);
1841 spin_lock_init(&adapter->ethtool_lock);
1842 atomic_set(&adapter->irq_sem, 0);
1843 pch_gbe_irq_disable(adapter);
1844
1845 pch_gbe_init_stats(adapter);
1846
1847 pr_debug("rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
1848 (u32) adapter->rx_buffer_len,
1849 hw->mac.min_frame_size, hw->mac.max_frame_size);
1850 return 0;
1851 }
1852
1853 /**
1854 * pch_gbe_open - Called when a network interface is made active
1855 * @netdev: Network interface device structure
1856 * Returns
1857 * 0: Successfully
1858 * Negative value: Failed
1859 */
1860 static int pch_gbe_open(struct net_device *netdev)
1861 {
1862 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1863 struct pch_gbe_hw *hw = &adapter->hw;
1864 int err;
1865
1866 /* allocate transmit descriptors */
1867 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
1868 if (err)
1869 goto err_setup_tx;
1870 /* allocate receive descriptors */
1871 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
1872 if (err)
1873 goto err_setup_rx;
1874 pch_gbe_hal_power_up_phy(hw);
1875 err = pch_gbe_up(adapter);
1876 if (err)
1877 goto err_up;
1878 pr_debug("Success End\n");
1879 return 0;
1880
1881 err_up:
1882 if (!adapter->wake_up_evt)
1883 pch_gbe_hal_power_down_phy(hw);
1884 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1885 err_setup_rx:
1886 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1887 err_setup_tx:
1888 pch_gbe_reset(adapter);
1889 pr_err("Error End\n");
1890 return err;
1891 }
1892
1893 /**
1894 * pch_gbe_stop - Disables a network interface
1895 * @netdev: Network interface device structure
1896 * Returns
1897 * 0: Successfully
1898 */
1899 static int pch_gbe_stop(struct net_device *netdev)
1900 {
1901 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1902 struct pch_gbe_hw *hw = &adapter->hw;
1903
1904 pch_gbe_down(adapter);
1905 if (!adapter->wake_up_evt)
1906 pch_gbe_hal_power_down_phy(hw);
1907 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
1908 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
1909 return 0;
1910 }
1911
1912 /**
1913 * pch_gbe_xmit_frame - Packet transmitting start
1914 * @skb: Socket buffer structure
1915 * @netdev: Network interface device structure
1916 * Returns
1917 * - NETDEV_TX_OK: Normal end
1918 * - NETDEV_TX_BUSY: Error end
1919 */
1920 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1921 {
1922 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1923 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1924 unsigned long flags;
1925
1926 if (unlikely(skb->len > (adapter->hw.mac.max_frame_size - 4))) {
1927 pr_err("Transfer length Error: skb len: %d > max: %d\n",
1928 skb->len, adapter->hw.mac.max_frame_size);
1929 dev_kfree_skb_any(skb);
1930 adapter->stats.tx_length_errors++;
1931 return NETDEV_TX_OK;
1932 }
1933 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
1934 /* Collision - tell upper layer to requeue */
1935 return NETDEV_TX_LOCKED;
1936 }
1937 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
1938 netif_stop_queue(netdev);
1939 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1940 pr_debug("Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
1941 tx_ring->next_to_use, tx_ring->next_to_clean);
1942 return NETDEV_TX_BUSY;
1943 }
1944 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1945
1946 /* CRC,ITAG no support */
1947 pch_gbe_tx_queue(adapter, tx_ring, skb);
1948 return NETDEV_TX_OK;
1949 }
1950
1951 /**
1952 * pch_gbe_get_stats - Get System Network Statistics
1953 * @netdev: Network interface device structure
1954 * Returns: The current stats
1955 */
1956 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
1957 {
1958 /* only return the current stats */
1959 return &netdev->stats;
1960 }
1961
1962 /**
1963 * pch_gbe_set_multi - Multicast and Promiscuous mode set
1964 * @netdev: Network interface device structure
1965 */
1966 static void pch_gbe_set_multi(struct net_device *netdev)
1967 {
1968 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1969 struct pch_gbe_hw *hw = &adapter->hw;
1970 struct netdev_hw_addr *ha;
1971 u8 *mta_list;
1972 u32 rctl;
1973 int i;
1974 int mc_count;
1975
1976 pr_debug("netdev->flags : 0x%08x\n", netdev->flags);
1977
1978 /* Check for Promiscuous and All Multicast modes */
1979 rctl = ioread32(&hw->reg->RX_MODE);
1980 mc_count = netdev_mc_count(netdev);
1981 if ((netdev->flags & IFF_PROMISC)) {
1982 rctl &= ~PCH_GBE_ADD_FIL_EN;
1983 rctl &= ~PCH_GBE_MLT_FIL_EN;
1984 } else if ((netdev->flags & IFF_ALLMULTI)) {
1985 /* all the multicasting receive permissions */
1986 rctl |= PCH_GBE_ADD_FIL_EN;
1987 rctl &= ~PCH_GBE_MLT_FIL_EN;
1988 } else {
1989 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
1990 /* all the multicasting receive permissions */
1991 rctl |= PCH_GBE_ADD_FIL_EN;
1992 rctl &= ~PCH_GBE_MLT_FIL_EN;
1993 } else {
1994 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
1995 }
1996 }
1997 iowrite32(rctl, &hw->reg->RX_MODE);
1998
1999 if (mc_count >= PCH_GBE_MAR_ENTRIES)
2000 return;
2001 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2002 if (!mta_list)
2003 return;
2004
2005 /* The shared function expects a packed array of only addresses. */
2006 i = 0;
2007 netdev_for_each_mc_addr(ha, netdev) {
2008 if (i == mc_count)
2009 break;
2010 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2011 }
2012 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2013 PCH_GBE_MAR_ENTRIES);
2014 kfree(mta_list);
2015
2016 pr_debug("RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2017 ioread32(&hw->reg->RX_MODE), mc_count);
2018 }
2019
2020 /**
2021 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2022 * @netdev: Network interface device structure
2023 * @addr: Pointer to an address structure
2024 * Returns
2025 * 0: Successfully
2026 * -EADDRNOTAVAIL: Failed
2027 */
2028 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2029 {
2030 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2031 struct sockaddr *skaddr = addr;
2032 int ret_val;
2033
2034 if (!is_valid_ether_addr(skaddr->sa_data)) {
2035 ret_val = -EADDRNOTAVAIL;
2036 } else {
2037 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2038 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2039 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2040 ret_val = 0;
2041 }
2042 pr_debug("ret_val : 0x%08x\n", ret_val);
2043 pr_debug("dev_addr : %pM\n", netdev->dev_addr);
2044 pr_debug("mac_addr : %pM\n", adapter->hw.mac.addr);
2045 pr_debug("MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2046 ioread32(&adapter->hw.reg->mac_adr[0].high),
2047 ioread32(&adapter->hw.reg->mac_adr[0].low));
2048 return ret_val;
2049 }
2050
2051 /**
2052 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2053 * @netdev: Network interface device structure
2054 * @new_mtu: New value for maximum frame size
2055 * Returns
2056 * 0: Successfully
2057 * -EINVAL: Failed
2058 */
2059 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2060 {
2061 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2062 int max_frame;
2063 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2064 int err;
2065
2066 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2067 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2068 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2069 pr_err("Invalid MTU setting\n");
2070 return -EINVAL;
2071 }
2072 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2073 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2074 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2075 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2076 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2077 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2078 else
2079 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2080
2081 if (netif_running(netdev)) {
2082 pch_gbe_down(adapter);
2083 err = pch_gbe_up(adapter);
2084 if (err) {
2085 adapter->rx_buffer_len = old_rx_buffer_len;
2086 pch_gbe_up(adapter);
2087 return -ENOMEM;
2088 } else {
2089 netdev->mtu = new_mtu;
2090 adapter->hw.mac.max_frame_size = max_frame;
2091 }
2092 } else {
2093 pch_gbe_reset(adapter);
2094 netdev->mtu = new_mtu;
2095 adapter->hw.mac.max_frame_size = max_frame;
2096 }
2097
2098 pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2099 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2100 adapter->hw.mac.max_frame_size);
2101 return 0;
2102 }
2103
2104 /**
2105 * pch_gbe_set_features - Reset device after features changed
2106 * @netdev: Network interface device structure
2107 * @features: New features
2108 * Returns
2109 * 0: HW state updated successfully
2110 */
2111 static int pch_gbe_set_features(struct net_device *netdev, u32 features)
2112 {
2113 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2114 u32 changed = features ^ netdev->features;
2115
2116 if (!(changed & NETIF_F_RXCSUM))
2117 return 0;
2118
2119 if (netif_running(netdev))
2120 pch_gbe_reinit_locked(adapter);
2121 else
2122 pch_gbe_reset(adapter);
2123
2124 return 0;
2125 }
2126
2127 /**
2128 * pch_gbe_ioctl - Controls register through a MII interface
2129 * @netdev: Network interface device structure
2130 * @ifr: Pointer to ifr structure
2131 * @cmd: Control command
2132 * Returns
2133 * 0: Successfully
2134 * Negative value: Failed
2135 */
2136 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2137 {
2138 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2139
2140 pr_debug("cmd : 0x%04x\n", cmd);
2141
2142 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2143 }
2144
2145 /**
2146 * pch_gbe_tx_timeout - Respond to a Tx Hang
2147 * @netdev: Network interface device structure
2148 */
2149 static void pch_gbe_tx_timeout(struct net_device *netdev)
2150 {
2151 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2152
2153 /* Do the reset outside of interrupt context */
2154 adapter->stats.tx_timeout_count++;
2155 schedule_work(&adapter->reset_task);
2156 }
2157
2158 /**
2159 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2160 * @napi: Pointer of polling device struct
2161 * @budget: The maximum number of a packet
2162 * Returns
2163 * false: Exit the polling mode
2164 * true: Continue the polling mode
2165 */
2166 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2167 {
2168 struct pch_gbe_adapter *adapter =
2169 container_of(napi, struct pch_gbe_adapter, napi);
2170 int work_done = 0;
2171 bool poll_end_flag = false;
2172 bool cleaned = false;
2173 u32 int_en;
2174
2175 pr_debug("budget : %d\n", budget);
2176
2177 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2178 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2179
2180 if (!cleaned)
2181 work_done = budget;
2182 /* If no Tx and not enough Rx work done,
2183 * exit the polling mode
2184 */
2185 if (work_done < budget)
2186 poll_end_flag = true;
2187
2188 if (poll_end_flag) {
2189 napi_complete(napi);
2190 if (adapter->rx_stop_flag) {
2191 adapter->rx_stop_flag = false;
2192 pch_gbe_start_receive(&adapter->hw);
2193 }
2194 pch_gbe_irq_enable(adapter);
2195 } else
2196 if (adapter->rx_stop_flag) {
2197 adapter->rx_stop_flag = false;
2198 pch_gbe_start_receive(&adapter->hw);
2199 int_en = ioread32(&adapter->hw.reg->INT_EN);
2200 iowrite32((int_en | PCH_GBE_INT_RX_FIFO_ERR),
2201 &adapter->hw.reg->INT_EN);
2202 }
2203
2204 pr_debug("poll_end_flag : %d work_done : %d budget : %d\n",
2205 poll_end_flag, work_done, budget);
2206
2207 return work_done;
2208 }
2209
2210 #ifdef CONFIG_NET_POLL_CONTROLLER
2211 /**
2212 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2213 * @netdev: Network interface device structure
2214 */
2215 static void pch_gbe_netpoll(struct net_device *netdev)
2216 {
2217 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2218
2219 disable_irq(adapter->pdev->irq);
2220 pch_gbe_intr(adapter->pdev->irq, netdev);
2221 enable_irq(adapter->pdev->irq);
2222 }
2223 #endif
2224
2225 static const struct net_device_ops pch_gbe_netdev_ops = {
2226 .ndo_open = pch_gbe_open,
2227 .ndo_stop = pch_gbe_stop,
2228 .ndo_start_xmit = pch_gbe_xmit_frame,
2229 .ndo_get_stats = pch_gbe_get_stats,
2230 .ndo_set_mac_address = pch_gbe_set_mac,
2231 .ndo_tx_timeout = pch_gbe_tx_timeout,
2232 .ndo_change_mtu = pch_gbe_change_mtu,
2233 .ndo_set_features = pch_gbe_set_features,
2234 .ndo_do_ioctl = pch_gbe_ioctl,
2235 .ndo_set_rx_mode = pch_gbe_set_multi,
2236 #ifdef CONFIG_NET_POLL_CONTROLLER
2237 .ndo_poll_controller = pch_gbe_netpoll,
2238 #endif
2239 };
2240
2241 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2242 pci_channel_state_t state)
2243 {
2244 struct net_device *netdev = pci_get_drvdata(pdev);
2245 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2246
2247 netif_device_detach(netdev);
2248 if (netif_running(netdev))
2249 pch_gbe_down(adapter);
2250 pci_disable_device(pdev);
2251 /* Request a slot slot reset. */
2252 return PCI_ERS_RESULT_NEED_RESET;
2253 }
2254
2255 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2256 {
2257 struct net_device *netdev = pci_get_drvdata(pdev);
2258 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2259 struct pch_gbe_hw *hw = &adapter->hw;
2260
2261 if (pci_enable_device(pdev)) {
2262 pr_err("Cannot re-enable PCI device after reset\n");
2263 return PCI_ERS_RESULT_DISCONNECT;
2264 }
2265 pci_set_master(pdev);
2266 pci_enable_wake(pdev, PCI_D0, 0);
2267 pch_gbe_hal_power_up_phy(hw);
2268 pch_gbe_reset(adapter);
2269 /* Clear wake up status */
2270 pch_gbe_mac_set_wol_event(hw, 0);
2271
2272 return PCI_ERS_RESULT_RECOVERED;
2273 }
2274
2275 static void pch_gbe_io_resume(struct pci_dev *pdev)
2276 {
2277 struct net_device *netdev = pci_get_drvdata(pdev);
2278 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2279
2280 if (netif_running(netdev)) {
2281 if (pch_gbe_up(adapter)) {
2282 pr_debug("can't bring device back up after reset\n");
2283 return;
2284 }
2285 }
2286 netif_device_attach(netdev);
2287 }
2288
2289 static int __pch_gbe_suspend(struct pci_dev *pdev)
2290 {
2291 struct net_device *netdev = pci_get_drvdata(pdev);
2292 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2293 struct pch_gbe_hw *hw = &adapter->hw;
2294 u32 wufc = adapter->wake_up_evt;
2295 int retval = 0;
2296
2297 netif_device_detach(netdev);
2298 if (netif_running(netdev))
2299 pch_gbe_down(adapter);
2300 if (wufc) {
2301 pch_gbe_set_multi(netdev);
2302 pch_gbe_setup_rctl(adapter);
2303 pch_gbe_configure_rx(adapter);
2304 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2305 hw->mac.link_duplex);
2306 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2307 hw->mac.link_duplex);
2308 pch_gbe_mac_set_wol_event(hw, wufc);
2309 pci_disable_device(pdev);
2310 } else {
2311 pch_gbe_hal_power_down_phy(hw);
2312 pch_gbe_mac_set_wol_event(hw, wufc);
2313 pci_disable_device(pdev);
2314 }
2315 return retval;
2316 }
2317
2318 #ifdef CONFIG_PM
2319 static int pch_gbe_suspend(struct device *device)
2320 {
2321 struct pci_dev *pdev = to_pci_dev(device);
2322
2323 return __pch_gbe_suspend(pdev);
2324 }
2325
2326 static int pch_gbe_resume(struct device *device)
2327 {
2328 struct pci_dev *pdev = to_pci_dev(device);
2329 struct net_device *netdev = pci_get_drvdata(pdev);
2330 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2331 struct pch_gbe_hw *hw = &adapter->hw;
2332 u32 err;
2333
2334 err = pci_enable_device(pdev);
2335 if (err) {
2336 pr_err("Cannot enable PCI device from suspend\n");
2337 return err;
2338 }
2339 pci_set_master(pdev);
2340 pch_gbe_hal_power_up_phy(hw);
2341 pch_gbe_reset(adapter);
2342 /* Clear wake on lan control and status */
2343 pch_gbe_mac_set_wol_event(hw, 0);
2344
2345 if (netif_running(netdev))
2346 pch_gbe_up(adapter);
2347 netif_device_attach(netdev);
2348
2349 return 0;
2350 }
2351 #endif /* CONFIG_PM */
2352
2353 static void pch_gbe_shutdown(struct pci_dev *pdev)
2354 {
2355 __pch_gbe_suspend(pdev);
2356 if (system_state == SYSTEM_POWER_OFF) {
2357 pci_wake_from_d3(pdev, true);
2358 pci_set_power_state(pdev, PCI_D3hot);
2359 }
2360 }
2361
2362 static void pch_gbe_remove(struct pci_dev *pdev)
2363 {
2364 struct net_device *netdev = pci_get_drvdata(pdev);
2365 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2366
2367 cancel_work_sync(&adapter->reset_task);
2368 unregister_netdev(netdev);
2369
2370 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2371
2372 kfree(adapter->tx_ring);
2373 kfree(adapter->rx_ring);
2374
2375 iounmap(adapter->hw.reg);
2376 pci_release_regions(pdev);
2377 free_netdev(netdev);
2378 pci_disable_device(pdev);
2379 }
2380
2381 static int pch_gbe_probe(struct pci_dev *pdev,
2382 const struct pci_device_id *pci_id)
2383 {
2384 struct net_device *netdev;
2385 struct pch_gbe_adapter *adapter;
2386 int ret;
2387
2388 ret = pci_enable_device(pdev);
2389 if (ret)
2390 return ret;
2391
2392 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2393 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2394 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2395 if (ret) {
2396 ret = pci_set_consistent_dma_mask(pdev,
2397 DMA_BIT_MASK(32));
2398 if (ret) {
2399 dev_err(&pdev->dev, "ERR: No usable DMA "
2400 "configuration, aborting\n");
2401 goto err_disable_device;
2402 }
2403 }
2404 }
2405
2406 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2407 if (ret) {
2408 dev_err(&pdev->dev,
2409 "ERR: Can't reserve PCI I/O and memory resources\n");
2410 goto err_disable_device;
2411 }
2412 pci_set_master(pdev);
2413
2414 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2415 if (!netdev) {
2416 ret = -ENOMEM;
2417 dev_err(&pdev->dev,
2418 "ERR: Can't allocate and set up an Ethernet device\n");
2419 goto err_release_pci;
2420 }
2421 SET_NETDEV_DEV(netdev, &pdev->dev);
2422
2423 pci_set_drvdata(pdev, netdev);
2424 adapter = netdev_priv(netdev);
2425 adapter->netdev = netdev;
2426 adapter->pdev = pdev;
2427 adapter->hw.back = adapter;
2428 adapter->hw.reg = pci_iomap(pdev, PCH_GBE_PCI_BAR, 0);
2429 if (!adapter->hw.reg) {
2430 ret = -EIO;
2431 dev_err(&pdev->dev, "Can't ioremap\n");
2432 goto err_free_netdev;
2433 }
2434
2435 netdev->netdev_ops = &pch_gbe_netdev_ops;
2436 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2437 netif_napi_add(netdev, &adapter->napi,
2438 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2439 netdev->hw_features = NETIF_F_RXCSUM |
2440 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2441 netdev->features = netdev->hw_features;
2442 pch_gbe_set_ethtool_ops(netdev);
2443
2444 pch_gbe_mac_load_mac_addr(&adapter->hw);
2445 pch_gbe_mac_reset_hw(&adapter->hw);
2446
2447 /* setup the private structure */
2448 ret = pch_gbe_sw_init(adapter);
2449 if (ret)
2450 goto err_iounmap;
2451
2452 /* Initialize PHY */
2453 ret = pch_gbe_init_phy(adapter);
2454 if (ret) {
2455 dev_err(&pdev->dev, "PHY initialize error\n");
2456 goto err_free_adapter;
2457 }
2458 pch_gbe_hal_get_bus_info(&adapter->hw);
2459
2460 /* Read the MAC address. and store to the private data */
2461 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2462 if (ret) {
2463 dev_err(&pdev->dev, "MAC address Read Error\n");
2464 goto err_free_adapter;
2465 }
2466
2467 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2468 if (!is_valid_ether_addr(netdev->dev_addr)) {
2469 dev_err(&pdev->dev, "Invalid MAC Address\n");
2470 ret = -EIO;
2471 goto err_free_adapter;
2472 }
2473 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2474 (unsigned long)adapter);
2475
2476 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2477
2478 pch_gbe_check_options(adapter);
2479
2480 /* initialize the wol settings based on the eeprom settings */
2481 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2482 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2483
2484 /* reset the hardware with the new settings */
2485 pch_gbe_reset(adapter);
2486
2487 ret = register_netdev(netdev);
2488 if (ret)
2489 goto err_free_adapter;
2490 /* tell the stack to leave us alone until pch_gbe_open() is called */
2491 netif_carrier_off(netdev);
2492 netif_stop_queue(netdev);
2493
2494 dev_dbg(&pdev->dev, "OKIsemi(R) PCH Network Connection\n");
2495
2496 device_set_wakeup_enable(&pdev->dev, 1);
2497 return 0;
2498
2499 err_free_adapter:
2500 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2501 kfree(adapter->tx_ring);
2502 kfree(adapter->rx_ring);
2503 err_iounmap:
2504 iounmap(adapter->hw.reg);
2505 err_free_netdev:
2506 free_netdev(netdev);
2507 err_release_pci:
2508 pci_release_regions(pdev);
2509 err_disable_device:
2510 pci_disable_device(pdev);
2511 return ret;
2512 }
2513
2514 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2515 {.vendor = PCI_VENDOR_ID_INTEL,
2516 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2517 .subvendor = PCI_ANY_ID,
2518 .subdevice = PCI_ANY_ID,
2519 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2520 .class_mask = (0xFFFF00)
2521 },
2522 {.vendor = PCI_VENDOR_ID_ROHM,
2523 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2524 .subvendor = PCI_ANY_ID,
2525 .subdevice = PCI_ANY_ID,
2526 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2527 .class_mask = (0xFFFF00)
2528 },
2529 {.vendor = PCI_VENDOR_ID_ROHM,
2530 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2531 .subvendor = PCI_ANY_ID,
2532 .subdevice = PCI_ANY_ID,
2533 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2534 .class_mask = (0xFFFF00)
2535 },
2536 /* required last entry */
2537 {0}
2538 };
2539
2540 #ifdef CONFIG_PM
2541 static const struct dev_pm_ops pch_gbe_pm_ops = {
2542 .suspend = pch_gbe_suspend,
2543 .resume = pch_gbe_resume,
2544 .freeze = pch_gbe_suspend,
2545 .thaw = pch_gbe_resume,
2546 .poweroff = pch_gbe_suspend,
2547 .restore = pch_gbe_resume,
2548 };
2549 #endif
2550
2551 static struct pci_error_handlers pch_gbe_err_handler = {
2552 .error_detected = pch_gbe_io_error_detected,
2553 .slot_reset = pch_gbe_io_slot_reset,
2554 .resume = pch_gbe_io_resume
2555 };
2556
2557 static struct pci_driver pch_gbe_driver = {
2558 .name = KBUILD_MODNAME,
2559 .id_table = pch_gbe_pcidev_id,
2560 .probe = pch_gbe_probe,
2561 .remove = pch_gbe_remove,
2562 #ifdef CONFIG_PM
2563 .driver.pm = &pch_gbe_pm_ops,
2564 #endif
2565 .shutdown = pch_gbe_shutdown,
2566 .err_handler = &pch_gbe_err_handler
2567 };
2568
2569
2570 static int __init pch_gbe_init_module(void)
2571 {
2572 int ret;
2573
2574 ret = pci_register_driver(&pch_gbe_driver);
2575 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2576 if (copybreak == 0) {
2577 pr_info("copybreak disabled\n");
2578 } else {
2579 pr_info("copybreak enabled for packets <= %u bytes\n",
2580 copybreak);
2581 }
2582 }
2583 return ret;
2584 }
2585
2586 static void __exit pch_gbe_exit_module(void)
2587 {
2588 pci_unregister_driver(&pch_gbe_driver);
2589 }
2590
2591 module_init(pch_gbe_init_module);
2592 module_exit(pch_gbe_exit_module);
2593
2594 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2595 MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>");
2596 MODULE_LICENSE("GPL");
2597 MODULE_VERSION(DRV_VERSION);
2598 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2599
2600 module_param(copybreak, uint, 0644);
2601 MODULE_PARM_DESC(copybreak,
2602 "Maximum size of packet that is copied to a new buffer on receive");
2603
2604 /* pch_gbe_main.c */
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