drivers/net/ethernet/stmicro/stmmac/common.h

   1 /*******************************************************************************
   2   STMMAC Common Header File
   3
   4   Copyright (C) 2007-2009  STMicroelectronics Ltd
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  23 *******************************************************************************/
  24
  25 #include <linux/netdevice.h>
  26 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  27 #define STMMAC_VLAN_TAG_USED
  28 #include <linux/if_vlan.h>
  29 #endif
  30
  31 #include "descs.h"
  32 #include "mmc.h"
  33
  34 #undef CHIP_DEBUG_PRINT
  35 /* Turn-on extra printk debug for MAC core, dma and descriptors */
  36 /* #define CHIP_DEBUG_PRINT */
  37
  38 #ifdef CHIP_DEBUG_PRINT
  39 #define CHIP_DBG(fmt, args...)  printk(fmt, ## args)
  40 #else
  41 #define CHIP_DBG(fmt, args...)  do { } while (0)
  42 #endif
  43
  44 #undef FRAME_FILTER_DEBUG
  45 /* #define FRAME_FILTER_DEBUG */
  46
  47 struct stmmac_extra_stats {
  48         /* Transmit errors */
  49         unsigned long tx_underflow ____cacheline_aligned;
  50         unsigned long tx_carrier;
  51         unsigned long tx_losscarrier;
  52         unsigned long tx_heartbeat;
  53         unsigned long tx_deferred;
  54         unsigned long tx_vlan;
  55         unsigned long tx_jabber;
  56         unsigned long tx_frame_flushed;
  57         unsigned long tx_payload_error;
  58         unsigned long tx_ip_header_error;
  59         /* Receive errors */
  60         unsigned long rx_desc;
  61         unsigned long rx_partial;
  62         unsigned long rx_runt;
  63         unsigned long rx_toolong;
  64         unsigned long rx_collision;
  65         unsigned long rx_crc;
  66         unsigned long rx_length;
  67         unsigned long rx_mii;
  68         unsigned long rx_multicast;
  69         unsigned long rx_gmac_overflow;
  70         unsigned long rx_watchdog;
  71         unsigned long da_rx_filter_fail;
  72         unsigned long sa_rx_filter_fail;
  73         unsigned long rx_missed_cntr;
  74         unsigned long rx_overflow_cntr;
  75         unsigned long rx_vlan;
  76         /* Tx/Rx IRQ errors */
  77         unsigned long tx_undeflow_irq;
  78         unsigned long tx_process_stopped_irq;
  79         unsigned long tx_jabber_irq;
  80         unsigned long rx_overflow_irq;
  81         unsigned long rx_buf_unav_irq;
  82         unsigned long rx_process_stopped_irq;
  83         unsigned long rx_watchdog_irq;
  84         unsigned long tx_early_irq;
  85         unsigned long fatal_bus_error_irq;
  86         /* Extra info */
  87         unsigned long threshold;
  88         unsigned long tx_pkt_n;
  89         unsigned long rx_pkt_n;
  90         unsigned long poll_n;
  91         unsigned long sched_timer_n;
  92         unsigned long normal_irq_n;
  93 };
  94
  95 #define HASH_TABLE_SIZE 64
  96 #define PAUSE_TIME 0x200
  97
  98 /* Flow Control defines */
  99 #define FLOW_OFF        0
 100 #define FLOW_RX         1
 101 #define FLOW_TX         2
 102 #define FLOW_AUTO       (FLOW_TX | FLOW_RX)
 103
 104 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
 105
 106 /* DAM HW feature register fields */
 107 #define DMA_HW_FEAT_MIISEL      0x00000001 /* 10/100 Mbps Support */
 108 #define DMA_HW_FEAT_GMIISEL     0x00000002 /* 1000 Mbps Support */
 109 #define DMA_HW_FEAT_HDSEL       0x00000004 /* Half-Duplex Support */
 110 #define DMA_HW_FEAT_EXTHASHEN   0x00000008 /* Expanded DA Hash Filter */
 111 #define DMA_HW_FEAT_HASHSEL     0x00000010 /* HASH Filter */
 112 #define DMA_HW_FEAT_ADDMACADRSEL        0x00000020 /* Multiple MAC Addr Reg */
 113 #define DMA_HW_FEAT_PCSSEL      0x00000040 /* PCS registers */
 114 #define DMA_HW_FEAT_L3L4FLTREN  0x00000080 /* Layer 3 & Layer 4 Feature */
 115 #define DMA_HW_FEAT_SMASEL      0x00000100 /* SMA(MDIO) Interface */
 116 #define DMA_HW_FEAT_RWKSEL      0x00000200 /* PMT Remote Wakeup */
 117 #define DMA_HW_FEAT_MGKSEL      0x00000400 /* PMT Magic Packet */
 118 #define DMA_HW_FEAT_MMCSEL      0x00000800 /* RMON Module */
 119 #define DMA_HW_FEAT_TSVER1SEL   0x00001000 /* Only IEEE 1588-2002 Timestamp */
 120 #define DMA_HW_FEAT_TSVER2SEL   0x00002000 /* IEEE 1588-2008 Adv Timestamp */
 121 #define DMA_HW_FEAT_EEESEL      0x00004000 /* Energy Efficient Ethernet */
 122 #define DMA_HW_FEAT_AVSEL       0x00008000 /* AV Feature */
 123 #define DMA_HW_FEAT_TXCOESEL    0x00010000 /* Checksum Offload in Tx */
 124 #define DMA_HW_FEAT_RXTYP1COE   0x00020000 /* IP csum Offload(Type 1) in Rx */
 125 #define DMA_HW_FEAT_RXTYP2COE   0x00040000 /* IP csum Offload(Type 2) in Rx */
 126 #define DMA_HW_FEAT_RXFIFOSIZE  0x00080000 /* Rx FIFO > 2048 Bytes */
 127 #define DMA_HW_FEAT_RXCHCNT     0x00300000 /* No. of additional Rx Channels */
 128 #define DMA_HW_FEAT_TXCHCNT     0x00c00000 /* No. of additional Tx Channels */
 129 #define DMA_HW_FEAT_ENHDESSEL   0x01000000 /* Alternate (Enhanced Descriptor) */
 130 #define DMA_HW_FEAT_INTTSEN     0x02000000 /* Timestamping with Internal
 131                                               System Time */
 132 #define DMA_HW_FEAT_FLEXIPPSEN  0x04000000 /* Flexible PPS Output */
 133 #define DMA_HW_FEAT_SAVLANINS   0x08000000 /* Source Addr or VLAN Insertion */
 134 #define DMA_HW_FEAT_ACTPHYIF    0x70000000 /* Active/selected PHY interface */
 135
 136 enum rx_frame_status { /* IPC status */
 137         good_frame = 0,
 138         discard_frame = 1,
 139         csum_none = 2,
 140         llc_snap = 4,
 141 };
 142
 143 enum tx_dma_irq_status {
 144         tx_hard_error = 1,
 145         tx_hard_error_bump_tc = 2,
 146         handle_tx_rx = 3,
 147 };
 148
 149 /* DMA HW capabilities */
 150 struct dma_features {
 151         unsigned int mbps_10_100;
 152         unsigned int mbps_1000;
 153         unsigned int half_duplex;
 154         unsigned int hash_filter;
 155         unsigned int multi_addr;
 156         unsigned int pcs;
 157         unsigned int sma_mdio;
 158         unsigned int pmt_remote_wake_up;
 159         unsigned int pmt_magic_frame;
 160         unsigned int rmon;
 161         /* IEEE 1588-2002*/
 162         unsigned int time_stamp;
 163         /* IEEE 1588-2008*/
 164         unsigned int atime_stamp;
 165         /* 802.3az - Energy-Efficient Ethernet (EEE) */
 166         unsigned int eee;
 167         unsigned int av;
 168         /* TX and RX csum */
 169         unsigned int tx_coe;
 170         unsigned int rx_coe_type1;
 171         unsigned int rx_coe_type2;
 172         unsigned int rxfifo_over_2048;
 173         /* TX and RX number of channels */
 174         unsigned int number_rx_channel;
 175         unsigned int number_tx_channel;
 176         /* Alternate (enhanced) DESC mode*/
 177         unsigned int enh_desc;
 178 };
 179
 180 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
 181 #define BUF_SIZE_16KiB 16384
 182 #define BUF_SIZE_8KiB 8192
 183 #define BUF_SIZE_4KiB 4096
 184 #define BUF_SIZE_2KiB 2048
 185
 186 /* Power Down and WOL */
 187 #define PMT_NOT_SUPPORTED 0
 188 #define PMT_SUPPORTED 1
 189
 190 /* Common MAC defines */
 191 #define MAC_CTRL_REG            0x00000000      /* MAC Control */
 192 #define MAC_ENABLE_TX           0x00000008      /* Transmitter Enable */
 193 #define MAC_RNABLE_RX           0x00000004      /* Receiver Enable */
 194
 195 struct stmmac_desc_ops {
 196         /* DMA RX descriptor ring initialization */
 197         void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
 198                               int disable_rx_ic);
 199         /* DMA TX descriptor ring initialization */
 200         void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
 201
 202         /* Invoked by the xmit function to prepare the tx descriptor */
 203         void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
 204                                  int csum_flag);
 205         /* Set/get the owner of the descriptor */
 206         void (*set_tx_owner) (struct dma_desc *p);
 207         int (*get_tx_owner) (struct dma_desc *p);
 208         /* Invoked by the xmit function to close the tx descriptor */
 209         void (*close_tx_desc) (struct dma_desc *p);
 210         /* Clean the tx descriptor as soon as the tx irq is received */
 211         void (*release_tx_desc) (struct dma_desc *p);
 212         /* Clear interrupt on tx frame completion. When this bit is
 213          * set an interrupt happens as soon as the frame is transmitted */
 214         void (*clear_tx_ic) (struct dma_desc *p);
 215         /* Last tx segment reports the transmit status */
 216         int (*get_tx_ls) (struct dma_desc *p);
 217         /* Return the transmit status looking at the TDES1 */
 218         int (*tx_status) (void *data, struct stmmac_extra_stats *x,
 219                           struct dma_desc *p, void __iomem *ioaddr);
 220         /* Get the buffer size from the descriptor */
 221         int (*get_tx_len) (struct dma_desc *p);
 222         /* Handle extra events on specific interrupts hw dependent */
 223         int (*get_rx_owner) (struct dma_desc *p);
 224         void (*set_rx_owner) (struct dma_desc *p);
 225         /* Get the receive frame size */
 226         int (*get_rx_frame_len) (struct dma_desc *p);
 227         /* Return the reception status looking at the RDES1 */
 228         int (*rx_status) (void *data, struct stmmac_extra_stats *x,
 229                           struct dma_desc *p);
 230 };
 231
 232 struct stmmac_dma_ops {
 233         /* DMA core initialization */
 234         int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
 235         /* Dump DMA registers */
 236         void (*dump_regs) (void __iomem *ioaddr);
 237         /* Set tx/rx threshold in the csr6 register
 238          * An invalid value enables the store-and-forward mode */
 239         void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
 240         /* To track extra statistic (if supported) */
 241         void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
 242                                    void __iomem *ioaddr);
 243         void (*enable_dma_transmission) (void __iomem *ioaddr);
 244         void (*enable_dma_irq) (void __iomem *ioaddr);
 245         void (*disable_dma_irq) (void __iomem *ioaddr);
 246         void (*start_tx) (void __iomem *ioaddr);
 247         void (*stop_tx) (void __iomem *ioaddr);
 248         void (*start_rx) (void __iomem *ioaddr);
 249         void (*stop_rx) (void __iomem *ioaddr);
 250         int (*dma_interrupt) (void __iomem *ioaddr,
 251                               struct stmmac_extra_stats *x);
 252         /* If supported then get the optional core features */
 253         unsigned int (*get_hw_feature) (void __iomem *ioaddr);
 254 };
 255
 256 struct stmmac_ops {
 257         /* MAC core initialization */
 258         void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
 259         /* Support checksum offload engine */
 260         int  (*rx_coe) (void __iomem *ioaddr);
 261         /* Dump MAC registers */
 262         void (*dump_regs) (void __iomem *ioaddr);
 263         /* Handle extra events on specific interrupts hw dependent */
 264         void (*host_irq_status) (void __iomem *ioaddr);
 265         /* Multicast filter setting */
 266         void (*set_filter) (struct net_device *dev);
 267         /* Flow control setting */
 268         void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
 269                            unsigned int fc, unsigned int pause_time);
 270         /* Set power management mode (e.g. magic frame) */
 271         void (*pmt) (void __iomem *ioaddr, unsigned long mode);
 272         /* Set/Get Unicast MAC addresses */
 273         void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
 274                                unsigned int reg_n);
 275         void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
 276                                unsigned int reg_n);
 277 };
 278
 279 struct mac_link {
 280         int port;
 281         int duplex;
 282         int speed;
 283 };
 284
 285 struct mii_regs {
 286         unsigned int addr;      /* MII Address */
 287         unsigned int data;      /* MII Data */
 288 };
 289
 290 struct stmmac_ring_mode_ops {
 291         unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
 292         unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
 293         void (*refill_desc3) (int bfsize, struct dma_desc *p);
 294         void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p);
 295         void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr,
 296                                 unsigned int size);
 297         void (*clean_desc3) (struct dma_desc *p);
 298         int (*set_16kib_bfsize) (int mtu);
 299 };
 300
 301 struct mac_device_info {
 302         const struct stmmac_ops         *mac;
 303         const struct stmmac_desc_ops    *desc;
 304         const struct stmmac_dma_ops     *dma;
 305         const struct stmmac_ring_mode_ops       *ring;
 306         struct mii_regs mii;    /* MII register Addresses */
 307         struct mac_link link;
 308         unsigned int synopsys_uid;
 309 };
 310
 311 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
 312 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
 313
 314 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 315                                 unsigned int high, unsigned int low);
 316 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 317                                 unsigned int high, unsigned int low);
 318 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
 319 extern const struct stmmac_ring_mode_ops ring_mode_ops;