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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / net / wireless / rtl818x / rtl8180 / dev.c
blob0082015ff664e9e5af45298dd804f46cf028d4a4
1
2 /*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/etherdevice.h>
24 #include <linux/eeprom_93cx6.h>
25 #include <net/mac80211.h>
26
27 #include "rtl8180.h"
28 #include "rtl8225.h"
29 #include "sa2400.h"
30 #include "max2820.h"
31 #include "grf5101.h"
32
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36 MODULE_LICENSE("GPL");
37
38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
39 /* rtl8185 */
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
43
44 /* rtl8180 */
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
49 { }
50 };
51
52 MODULE_DEVICE_TABLE(pci, rtl8180_table);
53
54 static const struct ieee80211_rate rtl818x_rates[] = {
55 { .bitrate = 10, .hw_value = 0, },
56 { .bitrate = 20, .hw_value = 1, },
57 { .bitrate = 55, .hw_value = 2, },
58 { .bitrate = 110, .hw_value = 3, },
59 { .bitrate = 60, .hw_value = 4, },
60 { .bitrate = 90, .hw_value = 5, },
61 { .bitrate = 120, .hw_value = 6, },
62 { .bitrate = 180, .hw_value = 7, },
63 { .bitrate = 240, .hw_value = 8, },
64 { .bitrate = 360, .hw_value = 9, },
65 { .bitrate = 480, .hw_value = 10, },
66 { .bitrate = 540, .hw_value = 11, },
67 };
68
69 static const struct ieee80211_channel rtl818x_channels[] = {
70 { .center_freq = 2412 },
71 { .center_freq = 2417 },
72 { .center_freq = 2422 },
73 { .center_freq = 2427 },
74 { .center_freq = 2432 },
75 { .center_freq = 2437 },
76 { .center_freq = 2442 },
77 { .center_freq = 2447 },
78 { .center_freq = 2452 },
79 { .center_freq = 2457 },
80 { .center_freq = 2462 },
81 { .center_freq = 2467 },
82 { .center_freq = 2472 },
83 { .center_freq = 2484 },
84 };
85
86
87 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
88 {
89 struct rtl8180_priv *priv = dev->priv;
90 int i = 10;
91 u32 buf;
92
93 buf = (data << 8) | addr;
94
95 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
96 while (i--) {
97 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
98 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
99 return;
100 }
101 }
102
103 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
104 {
105 struct rtl8180_priv *priv = dev->priv;
106 unsigned int count = 32;
107 u8 signal, agc, sq;
108
109 while (count--) {
110 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
111 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
112 u32 flags = le32_to_cpu(entry->flags);
113
114 if (flags & RTL818X_RX_DESC_FLAG_OWN)
115 return;
116
117 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
118 RTL818X_RX_DESC_FLAG_FOF |
119 RTL818X_RX_DESC_FLAG_RX_ERR)))
120 goto done;
121 else {
122 u32 flags2 = le32_to_cpu(entry->flags2);
123 struct ieee80211_rx_status rx_status = {0};
124 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
125
126 if (unlikely(!new_skb))
127 goto done;
128
129 pci_unmap_single(priv->pdev,
130 *((dma_addr_t *)skb->cb),
131 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
132 skb_put(skb, flags & 0xFFF);
133
134 rx_status.antenna = (flags2 >> 15) & 1;
135 rx_status.rate_idx = (flags >> 20) & 0xF;
136 agc = (flags2 >> 17) & 0x7F;
137 if (priv->r8185) {
138 if (rx_status.rate_idx > 3)
139 signal = 90 - clamp_t(u8, agc, 25, 90);
140 else
141 signal = 95 - clamp_t(u8, agc, 30, 95);
142 } else {
143 sq = flags2 & 0xff;
144 signal = priv->rf->calc_rssi(agc, sq);
145 }
146 rx_status.signal = signal;
147 rx_status.freq = dev->conf.channel->center_freq;
148 rx_status.band = dev->conf.channel->band;
149 rx_status.mactime = le64_to_cpu(entry->tsft);
150 rx_status.flag |= RX_FLAG_MACTIME_MPDU;
151 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
152 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
153
154 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
155 ieee80211_rx_irqsafe(dev, skb);
156
157 skb = new_skb;
158 priv->rx_buf[priv->rx_idx] = skb;
159 *((dma_addr_t *) skb->cb) =
160 pci_map_single(priv->pdev, skb_tail_pointer(skb),
161 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
162 }
163
164 done:
165 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
166 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
167 MAX_RX_SIZE);
168 if (priv->rx_idx == 31)
169 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
170 priv->rx_idx = (priv->rx_idx + 1) % 32;
171 }
172 }
173
174 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
175 {
176 struct rtl8180_priv *priv = dev->priv;
177 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
178
179 while (skb_queue_len(&ring->queue)) {
180 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
181 struct sk_buff *skb;
182 struct ieee80211_tx_info *info;
183 u32 flags = le32_to_cpu(entry->flags);
184
185 if (flags & RTL818X_TX_DESC_FLAG_OWN)
186 return;
187
188 ring->idx = (ring->idx + 1) % ring->entries;
189 skb = __skb_dequeue(&ring->queue);
190 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
191 skb->len, PCI_DMA_TODEVICE);
192
193 info = IEEE80211_SKB_CB(skb);
194 ieee80211_tx_info_clear_status(info);
195
196 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
197 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
198 info->flags |= IEEE80211_TX_STAT_ACK;
199
200 info->status.rates[0].count = (flags & 0xFF) + 1;
201 info->status.rates[1].idx = -1;
202
203 ieee80211_tx_status_irqsafe(dev, skb);
204 if (ring->entries - skb_queue_len(&ring->queue) == 2)
205 ieee80211_wake_queue(dev, prio);
206 }
207 }
208
209 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
210 {
211 struct ieee80211_hw *dev = dev_id;
212 struct rtl8180_priv *priv = dev->priv;
213 u16 reg;
214
215 spin_lock(&priv->lock);
216 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
217 if (unlikely(reg == 0xFFFF)) {
218 spin_unlock(&priv->lock);
219 return IRQ_HANDLED;
220 }
221
222 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
223
224 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
225 rtl8180_handle_tx(dev, 3);
226
227 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
228 rtl8180_handle_tx(dev, 2);
229
230 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
231 rtl8180_handle_tx(dev, 1);
232
233 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
234 rtl8180_handle_tx(dev, 0);
235
236 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
237 rtl8180_handle_rx(dev);
238
239 spin_unlock(&priv->lock);
240
241 return IRQ_HANDLED;
242 }
243
244 static void rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
245 {
246 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
247 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
248 struct rtl8180_priv *priv = dev->priv;
249 struct rtl8180_tx_ring *ring;
250 struct rtl8180_tx_desc *entry;
251 unsigned long flags;
252 unsigned int idx, prio;
253 dma_addr_t mapping;
254 u32 tx_flags;
255 u8 rc_flags;
256 u16 plcp_len = 0;
257 __le16 rts_duration = 0;
258
259 prio = skb_get_queue_mapping(skb);
260 ring = &priv->tx_ring[prio];
261
262 mapping = pci_map_single(priv->pdev, skb->data,
263 skb->len, PCI_DMA_TODEVICE);
264
265 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
266 RTL818X_TX_DESC_FLAG_LS |
267 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
268 skb->len;
269
270 if (priv->r8185)
271 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
272 RTL818X_TX_DESC_FLAG_NO_ENC;
273
274 rc_flags = info->control.rates[0].flags;
275 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
276 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
277 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
278 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
279 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
280 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
281 }
282
283 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
284 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
285 info);
286
287 if (!priv->r8185) {
288 unsigned int remainder;
289
290 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
291 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
292 remainder = (16 * (skb->len + 4)) %
293 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
294 if (remainder <= 6)
295 plcp_len |= 1 << 15;
296 }
297
298 spin_lock_irqsave(&priv->lock, flags);
299
300 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
301 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
302 priv->seqno += 0x10;
303 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
304 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
305 }
306
307 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
308 entry = &ring->desc[idx];
309
310 entry->rts_duration = rts_duration;
311 entry->plcp_len = cpu_to_le16(plcp_len);
312 entry->tx_buf = cpu_to_le32(mapping);
313 entry->frame_len = cpu_to_le32(skb->len);
314 entry->flags2 = info->control.rates[1].idx >= 0 ?
315 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
316 entry->retry_limit = info->control.rates[0].count;
317 entry->flags = cpu_to_le32(tx_flags);
318 __skb_queue_tail(&ring->queue, skb);
319 if (ring->entries - skb_queue_len(&ring->queue) < 2)
320 ieee80211_stop_queue(dev, prio);
321
322 spin_unlock_irqrestore(&priv->lock, flags);
323
324 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
325 }
326
327 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
328 {
329 u8 reg;
330
331 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
332 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
333 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
334 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
335 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
336 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
337 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
338 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
339 }
340
341 static int rtl8180_init_hw(struct ieee80211_hw *dev)
342 {
343 struct rtl8180_priv *priv = dev->priv;
344 u16 reg;
345
346 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
347 rtl818x_ioread8(priv, &priv->map->CMD);
348 msleep(10);
349
350 /* reset */
351 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
352 rtl818x_ioread8(priv, &priv->map->CMD);
353
354 reg = rtl818x_ioread8(priv, &priv->map->CMD);
355 reg &= (1 << 1);
356 reg |= RTL818X_CMD_RESET;
357 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
358 rtl818x_ioread8(priv, &priv->map->CMD);
359 msleep(200);
360
361 /* check success of reset */
362 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
363 wiphy_err(dev->wiphy, "reset timeout!\n");
364 return -ETIMEDOUT;
365 }
366
367 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
368 rtl818x_ioread8(priv, &priv->map->CMD);
369 msleep(200);
370
371 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
372 /* For cardbus */
373 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
374 reg |= 1 << 1;
375 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
376 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
377 reg |= (1 << 15) | (1 << 14) | (1 << 4);
378 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
379 }
380
381 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
382
383 if (!priv->r8185)
384 rtl8180_set_anaparam(priv, priv->anaparam);
385
386 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
387 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
388 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
389 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
390 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
391
392 /* TODO: necessary? specs indicate not */
393 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
394 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
395 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
396 if (priv->r8185) {
397 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
398 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
399 }
400 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
401
402 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
403
404 /* TODO: turn off hw wep on rtl8180 */
405
406 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
407
408 if (priv->r8185) {
409 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
410 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
411 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
412
413 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
414
415 /* TODO: set ClkRun enable? necessary? */
416 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
417 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
418 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
419 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
420 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
421 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
422 } else {
423 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
424 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
425
426 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
427 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
428 }
429
430 priv->rf->init(dev);
431 if (priv->r8185)
432 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
433 return 0;
434 }
435
436 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
437 {
438 struct rtl8180_priv *priv = dev->priv;
439 struct rtl8180_rx_desc *entry;
440 int i;
441
442 priv->rx_ring = pci_alloc_consistent(priv->pdev,
443 sizeof(*priv->rx_ring) * 32,
444 &priv->rx_ring_dma);
445
446 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
447 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
448 return -ENOMEM;
449 }
450
451 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
452 priv->rx_idx = 0;
453
454 for (i = 0; i < 32; i++) {
455 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
456 dma_addr_t *mapping;
457 entry = &priv->rx_ring[i];
458 if (!skb)
459 return 0;
460
461 priv->rx_buf[i] = skb;
462 mapping = (dma_addr_t *)skb->cb;
463 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
464 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
465 entry->rx_buf = cpu_to_le32(*mapping);
466 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
467 MAX_RX_SIZE);
468 }
469 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
470 return 0;
471 }
472
473 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
474 {
475 struct rtl8180_priv *priv = dev->priv;
476 int i;
477
478 for (i = 0; i < 32; i++) {
479 struct sk_buff *skb = priv->rx_buf[i];
480 if (!skb)
481 continue;
482
483 pci_unmap_single(priv->pdev,
484 *((dma_addr_t *)skb->cb),
485 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
486 kfree_skb(skb);
487 }
488
489 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
490 priv->rx_ring, priv->rx_ring_dma);
491 priv->rx_ring = NULL;
492 }
493
494 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
495 unsigned int prio, unsigned int entries)
496 {
497 struct rtl8180_priv *priv = dev->priv;
498 struct rtl8180_tx_desc *ring;
499 dma_addr_t dma;
500 int i;
501
502 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
503 if (!ring || (unsigned long)ring & 0xFF) {
504 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
505 prio);
506 return -ENOMEM;
507 }
508
509 memset(ring, 0, sizeof(*ring)*entries);
510 priv->tx_ring[prio].desc = ring;
511 priv->tx_ring[prio].dma = dma;
512 priv->tx_ring[prio].idx = 0;
513 priv->tx_ring[prio].entries = entries;
514 skb_queue_head_init(&priv->tx_ring[prio].queue);
515
516 for (i = 0; i < entries; i++)
517 ring[i].next_tx_desc =
518 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
519
520 return 0;
521 }
522
523 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
524 {
525 struct rtl8180_priv *priv = dev->priv;
526 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
527
528 while (skb_queue_len(&ring->queue)) {
529 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
530 struct sk_buff *skb = __skb_dequeue(&ring->queue);
531
532 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
533 skb->len, PCI_DMA_TODEVICE);
534 kfree_skb(skb);
535 ring->idx = (ring->idx + 1) % ring->entries;
536 }
537
538 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
539 ring->desc, ring->dma);
540 ring->desc = NULL;
541 }
542
543 static int rtl8180_start(struct ieee80211_hw *dev)
544 {
545 struct rtl8180_priv *priv = dev->priv;
546 int ret, i;
547 u32 reg;
548
549 ret = rtl8180_init_rx_ring(dev);
550 if (ret)
551 return ret;
552
553 for (i = 0; i < 4; i++)
554 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
555 goto err_free_rings;
556
557 ret = rtl8180_init_hw(dev);
558 if (ret)
559 goto err_free_rings;
560
561 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
562 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
563 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
564 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
565 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
566
567 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
568 IRQF_SHARED, KBUILD_MODNAME, dev);
569 if (ret) {
570 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
571 goto err_free_rings;
572 }
573
574 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
575
576 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
577 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
578
579 reg = RTL818X_RX_CONF_ONLYERLPKT |
580 RTL818X_RX_CONF_RX_AUTORESETPHY |
581 RTL818X_RX_CONF_MGMT |
582 RTL818X_RX_CONF_DATA |
583 (7 << 8 /* MAX RX DMA */) |
584 RTL818X_RX_CONF_BROADCAST |
585 RTL818X_RX_CONF_NICMAC;
586
587 if (priv->r8185)
588 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
589 else {
590 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
591 ? RTL818X_RX_CONF_CSDM1 : 0;
592 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
593 ? RTL818X_RX_CONF_CSDM2 : 0;
594 }
595
596 priv->rx_conf = reg;
597 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
598
599 if (priv->r8185) {
600 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
601 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
602 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
603 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
604
605 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
606 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
607 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
608 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
609 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
610
611 /* disable early TX */
612 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
613 }
614
615 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
616 reg |= (6 << 21 /* MAX TX DMA */) |
617 RTL818X_TX_CONF_NO_ICV;
618
619 if (priv->r8185)
620 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
621 else
622 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
623
624 /* different meaning, same value on both rtl8185 and rtl8180 */
625 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
626
627 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
628
629 reg = rtl818x_ioread8(priv, &priv->map->CMD);
630 reg |= RTL818X_CMD_RX_ENABLE;
631 reg |= RTL818X_CMD_TX_ENABLE;
632 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
633
634 return 0;
635
636 err_free_rings:
637 rtl8180_free_rx_ring(dev);
638 for (i = 0; i < 4; i++)
639 if (priv->tx_ring[i].desc)
640 rtl8180_free_tx_ring(dev, i);
641
642 return ret;
643 }
644
645 static void rtl8180_stop(struct ieee80211_hw *dev)
646 {
647 struct rtl8180_priv *priv = dev->priv;
648 u8 reg;
649 int i;
650
651 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
652
653 reg = rtl818x_ioread8(priv, &priv->map->CMD);
654 reg &= ~RTL818X_CMD_TX_ENABLE;
655 reg &= ~RTL818X_CMD_RX_ENABLE;
656 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
657
658 priv->rf->stop(dev);
659
660 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
661 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
662 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
663 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
664
665 free_irq(priv->pdev->irq, dev);
666
667 rtl8180_free_rx_ring(dev);
668 for (i = 0; i < 4; i++)
669 rtl8180_free_tx_ring(dev, i);
670 }
671
672 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
673 struct ieee80211_vif *vif)
674 {
675 struct rtl8180_priv *priv = dev->priv;
676
677 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
678 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
679 }
680
681 static void rtl8180_beacon_work(struct work_struct *work)
682 {
683 struct rtl8180_vif *vif_priv =
684 container_of(work, struct rtl8180_vif, beacon_work.work);
685 struct ieee80211_vif *vif =
686 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
687 struct ieee80211_hw *dev = vif_priv->dev;
688 struct ieee80211_mgmt *mgmt;
689 struct sk_buff *skb;
690
691 /* don't overflow the tx ring */
692 if (ieee80211_queue_stopped(dev, 0))
693 goto resched;
694
695 /* grab a fresh beacon */
696 skb = ieee80211_beacon_get(dev, vif);
697 if (!skb)
698 goto resched;
699
700 /*
701 * update beacon timestamp w/ TSF value
702 * TODO: make hardware update beacon timestamp
703 */
704 mgmt = (struct ieee80211_mgmt *)skb->data;
705 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
706
707 /* TODO: use actual beacon queue */
708 skb_set_queue_mapping(skb, 0);
709
710 rtl8180_tx(dev, skb);
711
712 resched:
713 /*
714 * schedule next beacon
715 * TODO: use hardware support for beacon timing
716 */
717 schedule_delayed_work(&vif_priv->beacon_work,
718 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
719 }
720
721 static int rtl8180_add_interface(struct ieee80211_hw *dev,
722 struct ieee80211_vif *vif)
723 {
724 struct rtl8180_priv *priv = dev->priv;
725 struct rtl8180_vif *vif_priv;
726
727 /*
728 * We only support one active interface at a time.
729 */
730 if (priv->vif)
731 return -EBUSY;
732
733 switch (vif->type) {
734 case NL80211_IFTYPE_STATION:
735 case NL80211_IFTYPE_ADHOC:
736 break;
737 default:
738 return -EOPNOTSUPP;
739 }
740
741 priv->vif = vif;
742
743 /* Initialize driver private area */
744 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
745 vif_priv->dev = dev;
746 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
747 vif_priv->enable_beacon = false;
748
749 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
750 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
751 le32_to_cpu(*(__le32 *)vif->addr));
752 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
753 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
754 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
755
756 return 0;
757 }
758
759 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
760 struct ieee80211_vif *vif)
761 {
762 struct rtl8180_priv *priv = dev->priv;
763 priv->vif = NULL;
764 }
765
766 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
767 {
768 struct rtl8180_priv *priv = dev->priv;
769 struct ieee80211_conf *conf = &dev->conf;
770
771 priv->rf->set_chan(dev, conf);
772
773 return 0;
774 }
775
776 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
777 struct ieee80211_vif *vif,
778 struct ieee80211_bss_conf *info,
779 u32 changed)
780 {
781 struct rtl8180_priv *priv = dev->priv;
782 struct rtl8180_vif *vif_priv;
783 int i;
784 u8 reg;
785
786 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
787
788 if (changed & BSS_CHANGED_BSSID) {
789 for (i = 0; i < ETH_ALEN; i++)
790 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
791 info->bssid[i]);
792
793 if (is_valid_ether_addr(info->bssid)) {
794 if (vif->type == NL80211_IFTYPE_ADHOC)
795 reg = RTL818X_MSR_ADHOC;
796 else
797 reg = RTL818X_MSR_INFRA;
798 } else
799 reg = RTL818X_MSR_NO_LINK;
800 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
801 }
802
803 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
804 priv->rf->conf_erp(dev, info);
805
806 if (changed & BSS_CHANGED_BEACON_ENABLED)
807 vif_priv->enable_beacon = info->enable_beacon;
808
809 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
810 cancel_delayed_work_sync(&vif_priv->beacon_work);
811 if (vif_priv->enable_beacon)
812 schedule_work(&vif_priv->beacon_work.work);
813 }
814 }
815
816 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
817 struct netdev_hw_addr_list *mc_list)
818 {
819 return netdev_hw_addr_list_count(mc_list);
820 }
821
822 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
823 unsigned int changed_flags,
824 unsigned int *total_flags,
825 u64 multicast)
826 {
827 struct rtl8180_priv *priv = dev->priv;
828
829 if (changed_flags & FIF_FCSFAIL)
830 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
831 if (changed_flags & FIF_CONTROL)
832 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
833 if (changed_flags & FIF_OTHER_BSS)
834 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
835 if (*total_flags & FIF_ALLMULTI || multicast > 0)
836 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
837 else
838 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
839
840 *total_flags = 0;
841
842 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
843 *total_flags |= FIF_FCSFAIL;
844 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
845 *total_flags |= FIF_CONTROL;
846 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
847 *total_flags |= FIF_OTHER_BSS;
848 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
849 *total_flags |= FIF_ALLMULTI;
850
851 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
852 }
853
854 static const struct ieee80211_ops rtl8180_ops = {
855 .tx = rtl8180_tx,
856 .start = rtl8180_start,
857 .stop = rtl8180_stop,
858 .add_interface = rtl8180_add_interface,
859 .remove_interface = rtl8180_remove_interface,
860 .config = rtl8180_config,
861 .bss_info_changed = rtl8180_bss_info_changed,
862 .prepare_multicast = rtl8180_prepare_multicast,
863 .configure_filter = rtl8180_configure_filter,
864 .get_tsf = rtl8180_get_tsf,
865 };
866
867 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
868 {
869 struct ieee80211_hw *dev = eeprom->data;
870 struct rtl8180_priv *priv = dev->priv;
871 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
872
873 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
874 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
875 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
876 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
877 }
878
879 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
880 {
881 struct ieee80211_hw *dev = eeprom->data;
882 struct rtl8180_priv *priv = dev->priv;
883 u8 reg = 2 << 6;
884
885 if (eeprom->reg_data_in)
886 reg |= RTL818X_EEPROM_CMD_WRITE;
887 if (eeprom->reg_data_out)
888 reg |= RTL818X_EEPROM_CMD_READ;
889 if (eeprom->reg_data_clock)
890 reg |= RTL818X_EEPROM_CMD_CK;
891 if (eeprom->reg_chip_select)
892 reg |= RTL818X_EEPROM_CMD_CS;
893
894 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
895 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
896 udelay(10);
897 }
898
899 static int __devinit rtl8180_probe(struct pci_dev *pdev,
900 const struct pci_device_id *id)
901 {
902 struct ieee80211_hw *dev;
903 struct rtl8180_priv *priv;
904 unsigned long mem_addr, mem_len;
905 unsigned int io_addr, io_len;
906 int err, i;
907 struct eeprom_93cx6 eeprom;
908 const char *chip_name, *rf_name = NULL;
909 u32 reg;
910 u16 eeprom_val;
911 u8 mac_addr[ETH_ALEN];
912
913 err = pci_enable_device(pdev);
914 if (err) {
915 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
916 pci_name(pdev));
917 return err;
918 }
919
920 err = pci_request_regions(pdev, KBUILD_MODNAME);
921 if (err) {
922 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
923 pci_name(pdev));
924 return err;
925 }
926
927 io_addr = pci_resource_start(pdev, 0);
928 io_len = pci_resource_len(pdev, 0);
929 mem_addr = pci_resource_start(pdev, 1);
930 mem_len = pci_resource_len(pdev, 1);
931
932 if (mem_len < sizeof(struct rtl818x_csr) ||
933 io_len < sizeof(struct rtl818x_csr)) {
934 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
935 pci_name(pdev));
936 err = -ENOMEM;
937 goto err_free_reg;
938 }
939
940 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
941 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
942 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
943 pci_name(pdev));
944 goto err_free_reg;
945 }
946
947 pci_set_master(pdev);
948
949 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
950 if (!dev) {
951 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
952 pci_name(pdev));
953 err = -ENOMEM;
954 goto err_free_reg;
955 }
956
957 priv = dev->priv;
958 priv->pdev = pdev;
959
960 dev->max_rates = 2;
961 SET_IEEE80211_DEV(dev, &pdev->dev);
962 pci_set_drvdata(pdev, dev);
963
964 priv->map = pci_iomap(pdev, 1, mem_len);
965 if (!priv->map)
966 priv->map = pci_iomap(pdev, 0, io_len);
967
968 if (!priv->map) {
969 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
970 pci_name(pdev));
971 goto err_free_dev;
972 }
973
974 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
975 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
976
977 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
978 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
979
980 priv->band.band = IEEE80211_BAND_2GHZ;
981 priv->band.channels = priv->channels;
982 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
983 priv->band.bitrates = priv->rates;
984 priv->band.n_bitrates = 4;
985 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
986
987 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
988 IEEE80211_HW_RX_INCLUDES_FCS |
989 IEEE80211_HW_SIGNAL_UNSPEC;
990 dev->vif_data_size = sizeof(struct rtl8180_vif);
991 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
992 BIT(NL80211_IFTYPE_ADHOC);
993 dev->queues = 1;
994 dev->max_signal = 65;
995
996 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
997 reg &= RTL818X_TX_CONF_HWVER_MASK;
998 switch (reg) {
999 case RTL818X_TX_CONF_R8180_ABCD:
1000 chip_name = "RTL8180";
1001 break;
1002 case RTL818X_TX_CONF_R8180_F:
1003 chip_name = "RTL8180vF";
1004 break;
1005 case RTL818X_TX_CONF_R8185_ABC:
1006 chip_name = "RTL8185";
1007 break;
1008 case RTL818X_TX_CONF_R8185_D:
1009 chip_name = "RTL8185vD";
1010 break;
1011 default:
1012 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1013 pci_name(pdev), reg >> 25);
1014 goto err_iounmap;
1015 }
1016
1017 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1018 if (priv->r8185) {
1019 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1020 pci_try_set_mwi(pdev);
1021 }
1022
1023 eeprom.data = dev;
1024 eeprom.register_read = rtl8180_eeprom_register_read;
1025 eeprom.register_write = rtl8180_eeprom_register_write;
1026 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1027 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1028 else
1029 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1030
1031 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1032 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1033 udelay(10);
1034
1035 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1036 eeprom_val &= 0xFF;
1037 switch (eeprom_val) {
1038 case 1: rf_name = "Intersil";
1039 break;
1040 case 2: rf_name = "RFMD";
1041 break;
1042 case 3: priv->rf = &sa2400_rf_ops;
1043 break;
1044 case 4: priv->rf = &max2820_rf_ops;
1045 break;
1046 case 5: priv->rf = &grf5101_rf_ops;
1047 break;
1048 case 9: priv->rf = rtl8180_detect_rf(dev);
1049 break;
1050 case 10:
1051 rf_name = "RTL8255";
1052 break;
1053 default:
1054 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1055 pci_name(pdev), eeprom_val);
1056 goto err_iounmap;
1057 }
1058
1059 if (!priv->rf) {
1060 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1061 pci_name(pdev), rf_name);
1062 goto err_iounmap;
1063 }
1064
1065 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1066 priv->csthreshold = eeprom_val >> 8;
1067 if (!priv->r8185) {
1068 __le32 anaparam;
1069 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1070 priv->anaparam = le32_to_cpu(anaparam);
1071 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1072 }
1073
1074 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1075 if (!is_valid_ether_addr(mac_addr)) {
1076 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1077 " randomly generated MAC addr\n", pci_name(pdev));
1078 random_ether_addr(mac_addr);
1079 }
1080 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1081
1082 /* CCK TX power */
1083 for (i = 0; i < 14; i += 2) {
1084 u16 txpwr;
1085 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
1086 priv->channels[i].hw_value = txpwr & 0xFF;
1087 priv->channels[i + 1].hw_value = txpwr >> 8;
1088 }
1089
1090 /* OFDM TX power */
1091 if (priv->r8185) {
1092 for (i = 0; i < 14; i += 2) {
1093 u16 txpwr;
1094 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1095 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1096 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1097 }
1098 }
1099
1100 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1101
1102 spin_lock_init(&priv->lock);
1103
1104 err = ieee80211_register_hw(dev);
1105 if (err) {
1106 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1107 pci_name(pdev));
1108 goto err_iounmap;
1109 }
1110
1111 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1112 mac_addr, chip_name, priv->rf->name);
1113
1114 return 0;
1115
1116 err_iounmap:
1117 iounmap(priv->map);
1118
1119 err_free_dev:
1120 pci_set_drvdata(pdev, NULL);
1121 ieee80211_free_hw(dev);
1122
1123 err_free_reg:
1124 pci_release_regions(pdev);
1125 pci_disable_device(pdev);
1126 return err;
1127 }
1128
1129 static void __devexit rtl8180_remove(struct pci_dev *pdev)
1130 {
1131 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1132 struct rtl8180_priv *priv;
1133
1134 if (!dev)
1135 return;
1136
1137 ieee80211_unregister_hw(dev);
1138
1139 priv = dev->priv;
1140
1141 pci_iounmap(pdev, priv->map);
1142 pci_release_regions(pdev);
1143 pci_disable_device(pdev);
1144 ieee80211_free_hw(dev);
1145 }
1146
1147 #ifdef CONFIG_PM
1148 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1149 {
1150 pci_save_state(pdev);
1151 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1152 return 0;
1153 }
1154
1155 static int rtl8180_resume(struct pci_dev *pdev)
1156 {
1157 pci_set_power_state(pdev, PCI_D0);
1158 pci_restore_state(pdev);
1159 return 0;
1160 }
1161
1162 #endif /* CONFIG_PM */
1163
1164 static struct pci_driver rtl8180_driver = {
1165 .name = KBUILD_MODNAME,
1166 .id_table = rtl8180_table,
1167 .probe = rtl8180_probe,
1168 .remove = __devexit_p(rtl8180_remove),
1169 #ifdef CONFIG_PM
1170 .suspend = rtl8180_suspend,
1171 .resume = rtl8180_resume,
1172 #endif /* CONFIG_PM */
1173 };
1174
1175 static int __init rtl8180_init(void)
1176 {
1177 return pci_register_driver(&rtl8180_driver);
1178 }
1179
1180 static void __exit rtl8180_exit(void)
1181 {
1182 pci_unregister_driver(&rtl8180_driver);
1183 }
1184
1185 module_init(rtl8180_init);
1186 module_exit(rtl8180_exit);
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