drivers/net/wireless/wl12xx/boot.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/slab.h>
  25 #include <linux/wl12xx.h>
  26
  27 #include "acx.h"
  28 #include "reg.h"
  29 #include "boot.h"
  30 #include "io.h"
  31 #include "event.h"
  32 #include "rx.h"
  33
  34 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
  35         [PART_DOWN] = {
  36                 .mem = {
  37                         .start = 0x00000000,
  38                         .size  = 0x000177c0
  39                 },
  40                 .reg = {
  41                         .start = REGISTERS_BASE,
  42                         .size  = 0x00008800
  43                 },
  44                 .mem2 = {
  45                         .start = 0x00000000,
  46                         .size  = 0x00000000
  47                 },
  48                 .mem3 = {
  49                         .start = 0x00000000,
  50                         .size  = 0x00000000
  51                 },
  52         },
  53
  54         [PART_WORK] = {
  55                 .mem = {
  56                         .start = 0x00040000,
  57                         .size  = 0x00014fc0
  58                 },
  59                 .reg = {
  60                         .start = REGISTERS_BASE,
  61                         .size  = 0x0000a000
  62                 },
  63                 .mem2 = {
  64                         .start = 0x003004f8,
  65                         .size  = 0x00000004
  66                 },
  67                 .mem3 = {
  68                         .start = 0x00040404,
  69                         .size  = 0x00000000
  70                 },
  71         },
  72
  73         [PART_DRPW] = {
  74                 .mem = {
  75                         .start = 0x00040000,
  76                         .size  = 0x00014fc0
  77                 },
  78                 .reg = {
  79                         .start = DRPW_BASE,
  80                         .size  = 0x00006000
  81                 },
  82                 .mem2 = {
  83                         .start = 0x00000000,
  84                         .size  = 0x00000000
  85                 },
  86                 .mem3 = {
  87                         .start = 0x00000000,
  88                         .size  = 0x00000000
  89                 }
  90         }
  91 };
  92
  93 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
  94 {
  95         u32 cpu_ctrl;
  96
  97         /* 10.5.0 run the firmware (I) */
  98         cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
  99
 100         /* 10.5.1 run the firmware (II) */
 101         cpu_ctrl |= flag;
 102         wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
 103 }
 104
 105 static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271 *wl)
 106 {
 107         unsigned int quirks = 0;
 108         unsigned int *fw_ver = wl->chip.fw_ver;
 109
 110         /* Only new station firmwares support routing fw logs to the host */
 111         if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
 112             (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
 113                 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED;
 114
 115         /* This feature is not yet supported for AP mode */
 116         if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
 117                 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED;
 118
 119         return quirks;
 120 }
 121
 122 static void wl1271_parse_fw_ver(struct wl1271 *wl)
 123 {
 124         int ret;
 125
 126         ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
 127                      &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
 128                      &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
 129                      &wl->chip.fw_ver[4]);
 130
 131         if (ret != 5) {
 132                 wl1271_warning("fw version incorrect value");
 133                 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
 134                 return;
 135         }
 136
 137         /* Check if any quirks are needed with older fw versions */
 138         wl->quirks |= wl12xx_get_fw_ver_quirks(wl);
 139 }
 140
 141 static void wl1271_boot_fw_version(struct wl1271 *wl)
 142 {
 143         struct wl1271_static_data static_data;
 144
 145         wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
 146                     false);
 147
 148         strncpy(wl->chip.fw_ver_str, static_data.fw_version,
 149                 sizeof(wl->chip.fw_ver_str));
 150
 151         /* make sure the string is NULL-terminated */
 152         wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
 153
 154         wl1271_parse_fw_ver(wl);
 155 }
 156
 157 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
 158                                              size_t fw_data_len, u32 dest)
 159 {
 160         struct wl1271_partition_set partition;
 161         int addr, chunk_num, partition_limit;
 162         u8 *p, *chunk;
 163
 164         /* whal_FwCtrl_LoadFwImageSm() */
 165
 166         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
 167
 168         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
 169                      fw_data_len, CHUNK_SIZE);
 170
 171         if ((fw_data_len % 4) != 0) {
 172                 wl1271_error("firmware length not multiple of four");
 173                 return -EIO;
 174         }
 175
 176         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
 177         if (!chunk) {
 178                 wl1271_error("allocation for firmware upload chunk failed");
 179                 return -ENOMEM;
 180         }
 181
 182         memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
 183         partition.mem.start = dest;
 184         wl1271_set_partition(wl, &partition);
 185
 186         /* 10.1 set partition limit and chunk num */
 187         chunk_num = 0;
 188         partition_limit = part_table[PART_DOWN].mem.size;
 189
 190         while (chunk_num < fw_data_len / CHUNK_SIZE) {
 191                 /* 10.2 update partition, if needed */
 192                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
 193                 if (addr > partition_limit) {
 194                         addr = dest + chunk_num * CHUNK_SIZE;
 195                         partition_limit = chunk_num * CHUNK_SIZE +
 196                                 part_table[PART_DOWN].mem.size;
 197                         partition.mem.start = addr;
 198                         wl1271_set_partition(wl, &partition);
 199                 }
 200
 201                 /* 10.3 upload the chunk */
 202                 addr = dest + chunk_num * CHUNK_SIZE;
 203                 p = buf + chunk_num * CHUNK_SIZE;
 204                 memcpy(chunk, p, CHUNK_SIZE);
 205                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 206                              p, addr);
 207                 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
 208
 209                 chunk_num++;
 210         }
 211
 212         /* 10.4 upload the last chunk */
 213         addr = dest + chunk_num * CHUNK_SIZE;
 214         p = buf + chunk_num * CHUNK_SIZE;
 215         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
 216         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
 217                      fw_data_len % CHUNK_SIZE, p, addr);
 218         wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
 219
 220         kfree(chunk);
 221         return 0;
 222 }
 223
 224 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
 225 {
 226         u32 chunks, addr, len;
 227         int ret = 0;
 228         u8 *fw;
 229
 230         fw = wl->fw;
 231         chunks = be32_to_cpup((__be32 *) fw);
 232         fw += sizeof(u32);
 233
 234         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
 235
 236         while (chunks--) {
 237                 addr = be32_to_cpup((__be32 *) fw);
 238                 fw += sizeof(u32);
 239                 len = be32_to_cpup((__be32 *) fw);
 240                 fw += sizeof(u32);
 241
 242                 if (len > 300000) {
 243                         wl1271_info("firmware chunk too long: %u", len);
 244                         return -EINVAL;
 245                 }
 246                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
 247                              chunks, addr, len);
 248                 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
 249                 if (ret != 0)
 250                         break;
 251                 fw += len;
 252         }
 253
 254         return ret;
 255 }
 256
 257 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
 258 {
 259         size_t nvs_len, burst_len;
 260         int i;
 261         u32 dest_addr, val;
 262         u8 *nvs_ptr, *nvs_aligned;
 263
 264         if (wl->nvs == NULL)
 265                 return -ENODEV;
 266
 267         if (wl->chip.id == CHIP_ID_1283_PG20) {
 268                 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;
 269
 270                 if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
 271                         if (nvs->general_params.dual_mode_select)
 272                                 wl->enable_11a = true;
 273                 } else {
 274                         wl1271_error("nvs size is not as expected: %zu != %zu",
 275                                      wl->nvs_len,
 276                                      sizeof(struct wl128x_nvs_file));
 277                         kfree(wl->nvs);
 278                         wl->nvs = NULL;
 279                         wl->nvs_len = 0;
 280                         return -EILSEQ;
 281                 }
 282
 283                 /* only the first part of the NVS needs to be uploaded */
 284                 nvs_len = sizeof(nvs->nvs);
 285                 nvs_ptr = (u8 *)nvs->nvs;
 286
 287         } else {
 288                 struct wl1271_nvs_file *nvs =
 289                         (struct wl1271_nvs_file *)wl->nvs;
 290                 /*
 291                  * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
 292                  * band configurations) can be removed when those NVS files stop
 293                  * floating around.
 294                  */
 295                 if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
 296                     wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
 297                         if (nvs->general_params.dual_mode_select)
 298                                 wl->enable_11a = true;
 299                 }
 300
 301                 if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
 302                     (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
 303                      wl->enable_11a)) {
 304                         wl1271_error("nvs size is not as expected: %zu != %zu",
 305                                 wl->nvs_len, sizeof(struct wl1271_nvs_file));
 306                         kfree(wl->nvs);
 307                         wl->nvs = NULL;
 308                         wl->nvs_len = 0;
 309                         return -EILSEQ;
 310                 }
 311
 312                 /* only the first part of the NVS needs to be uploaded */
 313                 nvs_len = sizeof(nvs->nvs);
 314                 nvs_ptr = (u8 *) nvs->nvs;
 315         }
 316
 317         /* update current MAC address to NVS */
 318         nvs_ptr[11] = wl->mac_addr[0];
 319         nvs_ptr[10] = wl->mac_addr[1];
 320         nvs_ptr[6] = wl->mac_addr[2];
 321         nvs_ptr[5] = wl->mac_addr[3];
 322         nvs_ptr[4] = wl->mac_addr[4];
 323         nvs_ptr[3] = wl->mac_addr[5];
 324
 325         /*
 326          * Layout before the actual NVS tables:
 327          * 1 byte : burst length.
 328          * 2 bytes: destination address.
 329          * n bytes: data to burst copy.
 330          *
 331          * This is ended by a 0 length, then the NVS tables.
 332          */
 333
 334         /* FIXME: Do we need to check here whether the LSB is 1? */
 335         while (nvs_ptr[0]) {
 336                 burst_len = nvs_ptr[0];
 337                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 338
 339                 /*
 340                  * Due to our new wl1271_translate_reg_addr function,
 341                  * we need to add the REGISTER_BASE to the destination
 342                  */
 343                 dest_addr += REGISTERS_BASE;
 344
 345                 /* We move our pointer to the data */
 346                 nvs_ptr += 3;
 347
 348                 for (i = 0; i < burst_len; i++) {
 349                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 350                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 351
 352                         wl1271_debug(DEBUG_BOOT,
 353                                      "nvs burst write 0x%x: 0x%x",
 354                                      dest_addr, val);
 355                         wl1271_write32(wl, dest_addr, val);
 356
 357                         nvs_ptr += 4;
 358                         dest_addr += 4;
 359                 }
 360         }
 361
 362         /*
 363          * We've reached the first zero length, the first NVS table
 364          * is located at an aligned offset which is at least 7 bytes further.
 365          * NOTE: The wl->nvs->nvs element must be first, in order to
 366          * simplify the casting, we assume it is at the beginning of
 367          * the wl->nvs structure.
 368          */
 369         nvs_ptr = (u8 *)wl->nvs +
 370                         ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);
 371         nvs_len -= nvs_ptr - (u8 *)wl->nvs;
 372
 373         /* Now we must set the partition correctly */
 374         wl1271_set_partition(wl, &part_table[PART_WORK]);
 375
 376         /* Copy the NVS tables to a new block to ensure alignment */
 377         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
 378         if (!nvs_aligned)
 379                 return -ENOMEM;
 380
 381         /* And finally we upload the NVS tables */
 382         wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
 383
 384         kfree(nvs_aligned);
 385         return 0;
 386 }
 387
 388 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
 389 {
 390         wl1271_enable_interrupts(wl);
 391         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 392                        WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 393         wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
 394 }
 395
 396 static int wl1271_boot_soft_reset(struct wl1271 *wl)
 397 {
 398         unsigned long timeout;
 399         u32 boot_data;
 400
 401         /* perform soft reset */
 402         wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
 403
 404         /* SOFT_RESET is self clearing */
 405         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
 406         while (1) {
 407                 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
 408                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
 409                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
 410                         break;
 411
 412                 if (time_after(jiffies, timeout)) {
 413                         /* 1.2 check pWhalBus->uSelfClearTime if the
 414                          * timeout was reached */
 415                         wl1271_error("soft reset timeout");
 416                         return -1;
 417                 }
 418
 419                 udelay(SOFT_RESET_STALL_TIME);
 420         }
 421
 422         /* disable Rx/Tx */
 423         wl1271_write32(wl, ENABLE, 0x0);
 424
 425         /* disable auto calibration on start*/
 426         wl1271_write32(wl, SPARE_A2, 0xffff);
 427
 428         return 0;
 429 }
 430
 431 static int wl1271_boot_run_firmware(struct wl1271 *wl)
 432 {
 433         int loop, ret;
 434         u32 chip_id, intr;
 435
 436         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 437
 438         chip_id = wl1271_read32(wl, CHIP_ID_B);
 439
 440         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 441
 442         if (chip_id != wl->chip.id) {
 443                 wl1271_error("chip id doesn't match after firmware boot");
 444                 return -EIO;
 445         }
 446
 447         /* wait for init to complete */
 448         loop = 0;
 449         while (loop++ < INIT_LOOP) {
 450                 udelay(INIT_LOOP_DELAY);
 451                 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 452
 453                 if (intr == 0xffffffff) {
 454                         wl1271_error("error reading hardware complete "
 455                                      "init indication");
 456                         return -EIO;
 457                 }
 458                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
 459                 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
 460                         wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
 461                                        WL1271_ACX_INTR_INIT_COMPLETE);
 462                         break;
 463                 }
 464         }
 465
 466         if (loop > INIT_LOOP) {
 467                 wl1271_error("timeout waiting for the hardware to "
 468                              "complete initialization");
 469                 return -EIO;
 470         }
 471
 472         /* get hardware config command mail box */
 473         wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
 474
 475         /* get hardware config event mail box */
 476         wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
 477
 478         /* set the working partition to its "running" mode offset */
 479         wl1271_set_partition(wl, &part_table[PART_WORK]);
 480
 481         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 482                      wl->cmd_box_addr, wl->event_box_addr);
 483
 484         wl1271_boot_fw_version(wl);
 485
 486         /*
 487          * in case of full asynchronous mode the firmware event must be
 488          * ready to receive event from the command mailbox
 489          */
 490
 491         /* unmask required mbox events  */
 492         wl->event_mask = BSS_LOSE_EVENT_ID |
 493                 SCAN_COMPLETE_EVENT_ID |
 494                 PS_REPORT_EVENT_ID |
 495                 DISCONNECT_EVENT_COMPLETE_ID |
 496                 RSSI_SNR_TRIGGER_0_EVENT_ID |
 497                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
 498                 SOFT_GEMINI_SENSE_EVENT_ID |
 499                 PERIODIC_SCAN_REPORT_EVENT_ID |
 500                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
 501                 DUMMY_PACKET_EVENT_ID |
 502                 PEER_REMOVE_COMPLETE_EVENT_ID |
 503                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
 504                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
 505                 INACTIVE_STA_EVENT_ID |
 506                 MAX_TX_RETRY_EVENT_ID |
 507                 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
 508
 509         ret = wl1271_event_unmask(wl);
 510         if (ret < 0) {
 511                 wl1271_error("EVENT mask setting failed");
 512                 return ret;
 513         }
 514
 515         wl1271_event_mbox_config(wl);
 516
 517         /* firmware startup completed */
 518         return 0;
 519 }
 520
 521 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
 522 {
 523         u32 polarity;
 524
 525         polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
 526
 527         /* We use HIGH polarity, so unset the LOW bit */
 528         polarity &= ~POLARITY_LOW;
 529         wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
 530
 531         return 0;
 532 }
 533
 534 static void wl1271_boot_hw_version(struct wl1271 *wl)
 535 {
 536         u32 fuse;
 537
 538         if (wl->chip.id == CHIP_ID_1283_PG20)
 539                 fuse = wl1271_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1);
 540         else
 541                 fuse = wl1271_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1);
 542         fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
 543
 544         wl->hw_pg_ver = (s8)fuse;
 545 }
 546
 547 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 548 {
 549         u16 spare_reg;
 550
 551         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 552         spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG);
 553         if (spare_reg == 0xFFFF)
 554                 return -EFAULT;
 555         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 556         wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 557
 558         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 559         wl1271_top_reg_write(wl, SYS_CLK_CFG_REG,
 560                              WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 561
 562         /* Delay execution for 15msec, to let the HW settle */
 563         mdelay(15);
 564
 565         return 0;
 566 }
 567
 568 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 569 {
 570         u16 tcxo_detection;
 571
 572         tcxo_detection = wl1271_top_reg_read(wl, TCXO_CLK_DETECT_REG);
 573         if (tcxo_detection & TCXO_DET_FAILED)
 574                 return false;
 575
 576         return true;
 577 }
 578
 579 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 580 {
 581         u16 fref_detection;
 582
 583         fref_detection = wl1271_top_reg_read(wl, FREF_CLK_DETECT_REG);
 584         if (fref_detection & FREF_CLK_DETECT_FAIL)
 585                 return false;
 586
 587         return true;
 588 }
 589
 590 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 591 {
 592         wl1271_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 593         wl1271_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 594         wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, MCS_PLL_CONFIG_REG_VAL);
 595
 596         return 0;
 597 }
 598
 599 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 600 {
 601         u16 spare_reg;
 602         u16 pll_config;
 603         u8 input_freq;
 604
 605         /* Mask bits [3:1] in the sys_clk_cfg register */
 606         spare_reg = wl1271_top_reg_read(wl, WL_SPARE_REG);
 607         if (spare_reg == 0xFFFF)
 608                 return -EFAULT;
 609         spare_reg |= BIT(2);
 610         wl1271_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 611
 612         /* Handle special cases of the TCXO clock */
 613         if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 614             wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 615                 return wl128x_manually_configure_mcs_pll(wl);
 616
 617         /* Set the input frequency according to the selected clock source */
 618         input_freq = (clk & 1) + 1;
 619
 620         pll_config = wl1271_top_reg_read(wl, MCS_PLL_CONFIG_REG);
 621         if (pll_config == 0xFFFF)
 622                 return -EFAULT;
 623         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 624         pll_config |= MCS_PLL_ENABLE_HP;
 625         wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 626
 627         return 0;
 628 }
 629
 630 /*
 631  * WL128x has two clocks input - TCXO and FREF.
 632  * TCXO is the main clock of the device, while FREF is used to sync
 633  * between the GPS and the cellular modem.
 634  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 635  * as the WLAN/BT main clock.
 636  */
 637 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 638 {
 639         u16 sys_clk_cfg;
 640
 641         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 642         if (wl->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 643             wl->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 644                 if (!wl128x_switch_tcxo_to_fref(wl))
 645                         return -EINVAL;
 646                 goto fref_clk;
 647         }
 648
 649         /* Query the HW, to determine which clock source we should use */
 650         sys_clk_cfg = wl1271_top_reg_read(wl, SYS_CLK_CFG_REG);
 651         if (sys_clk_cfg == 0xFFFF)
 652                 return -EINVAL;
 653         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 654                 goto fref_clk;
 655
 656         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 657         if (wl->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 658             wl->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 659                 if (!wl128x_switch_tcxo_to_fref(wl))
 660                         return -EINVAL;
 661                 goto fref_clk;
 662         }
 663
 664         /* TCXO clock is selected */
 665         if (!wl128x_is_tcxo_valid(wl))
 666                 return -EINVAL;
 667         *selected_clock = wl->tcxo_clock;
 668         goto config_mcs_pll;
 669
 670 fref_clk:
 671         /* FREF clock is selected */
 672         if (!wl128x_is_fref_valid(wl))
 673                 return -EINVAL;
 674         *selected_clock = wl->ref_clock;
 675
 676 config_mcs_pll:
 677         return wl128x_configure_mcs_pll(wl, *selected_clock);
 678 }
 679
 680 static int wl127x_boot_clk(struct wl1271 *wl)
 681 {
 682         u32 pause;
 683         u32 clk;
 684
 685         if (((wl->hw_pg_ver & PG_MAJOR_VER_MASK) >> PG_MAJOR_VER_OFFSET) < 3)
 686                 wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION;
 687
 688         if (wl->ref_clock == CONF_REF_CLK_19_2_E ||
 689             wl->ref_clock == CONF_REF_CLK_38_4_E ||
 690             wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 691                 /* ref clk: 19.2/38.4/38.4-XTAL */
 692                 clk = 0x3;
 693         else if (wl->ref_clock == CONF_REF_CLK_26_E ||
 694                  wl->ref_clock == CONF_REF_CLK_52_E)
 695                 /* ref clk: 26/52 */
 696                 clk = 0x5;
 697         else
 698                 return -EINVAL;
 699
 700         if (wl->ref_clock != CONF_REF_CLK_19_2_E) {
 701                 u16 val;
 702                 /* Set clock type (open drain) */
 703                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
 704                 val &= FREF_CLK_TYPE_BITS;
 705                 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 706
 707                 /* Set clock pull mode (no pull) */
 708                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
 709                 val |= NO_PULL;
 710                 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
 711         } else {
 712                 u16 val;
 713                 /* Set clock polarity */
 714                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
 715                 val &= FREF_CLK_POLARITY_BITS;
 716                 val |= CLK_REQ_OUTN_SEL;
 717                 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
 718         }
 719
 720         wl1271_write32(wl, PLL_PARAMETERS, clk);
 721
 722         pause = wl1271_read32(wl, PLL_PARAMETERS);
 723
 724         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
 725
 726         pause &= ~(WU_COUNTER_PAUSE_VAL);
 727         pause |= WU_COUNTER_PAUSE_VAL;
 728         wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
 729
 730         return 0;
 731 }
 732
 733 /* uploads NVS and firmware */
 734 int wl1271_load_firmware(struct wl1271 *wl)
 735 {
 736         int ret = 0;
 737         u32 tmp, clk;
 738         int selected_clock = -1;
 739
 740         wl1271_boot_hw_version(wl);
 741
 742         if (wl->chip.id == CHIP_ID_1283_PG20) {
 743                 ret = wl128x_boot_clk(wl, &selected_clock);
 744                 if (ret < 0)
 745                         goto out;
 746         } else {
 747                 ret = wl127x_boot_clk(wl);
 748                 if (ret < 0)
 749                         goto out;
 750         }
 751
 752         /* Continue the ELP wake up sequence */
 753         wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 754         udelay(500);
 755
 756         wl1271_set_partition(wl, &part_table[PART_DRPW]);
 757
 758         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
 759            to be used by DRPw FW. The RTRIM value will be added by the FW
 760            before taking DRPw out of reset */
 761
 762         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
 763         clk = wl1271_read32(wl, DRPW_SCRATCH_START);
 764
 765         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 766
 767         if (wl->chip.id == CHIP_ID_1283_PG20) {
 768                 clk |= ((selected_clock & 0x3) << 1) << 4;
 769         } else {
 770                 clk |= (wl->ref_clock << 1) << 4;
 771         }
 772
 773         wl1271_write32(wl, DRPW_SCRATCH_START, clk);
 774
 775         wl1271_set_partition(wl, &part_table[PART_WORK]);
 776
 777         /* Disable interrupts */
 778         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 779
 780         ret = wl1271_boot_soft_reset(wl);
 781         if (ret < 0)
 782                 goto out;
 783
 784         /* 2. start processing NVS file */
 785         ret = wl1271_boot_upload_nvs(wl);
 786         if (ret < 0)
 787                 goto out;
 788
 789         /* write firmware's last address (ie. it's length) to
 790          * ACX_EEPROMLESS_IND_REG */
 791         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
 792
 793         wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
 794
 795         tmp = wl1271_read32(wl, CHIP_ID_B);
 796
 797         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 798
 799         /* 6. read the EEPROM parameters */
 800         tmp = wl1271_read32(wl, SCR_PAD2);
 801
 802         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
 803          * to upload_fw) */
 804
 805         if (wl->chip.id == CHIP_ID_1283_PG20)
 806                 wl1271_top_reg_write(wl, SDIO_IO_DS, wl->conf.hci_io_ds);
 807
 808         ret = wl1271_boot_upload_firmware(wl);
 809         if (ret < 0)
 810                 goto out;
 811
 812 out:
 813         return ret;
 814 }
 815 EXPORT_SYMBOL_GPL(wl1271_load_firmware);
 816
 817 int wl1271_boot(struct wl1271 *wl)
 818 {
 819         int ret;
 820
 821         /* upload NVS and firmware */
 822         ret = wl1271_load_firmware(wl);
 823         if (ret)
 824                 return ret;
 825
 826         /* 10.5 start firmware */
 827         ret = wl1271_boot_run_firmware(wl);
 828         if (ret < 0)
 829                 goto out;
 830
 831         ret = wl1271_boot_write_irq_polarity(wl);
 832         if (ret < 0)
 833                 goto out;
 834
 835         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 836                        WL1271_ACX_ALL_EVENTS_VECTOR);
 837
 838         /* Enable firmware interrupts now */
 839         wl1271_boot_enable_interrupts(wl);
 840
 841         wl1271_event_mbox_config(wl);
 842
 843 out:
 844         return ret;
 845 }