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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / staging / cx25821 / cx25821-video-upstream.c
blobc0b80068f468b9d62e9d967f92dc96b261491791
1 /*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25 #include "cx25821-video.h"
26 #include "cx25821-video-upstream.h"
27
28 #include <linux/fs.h>
29 #include <linux/errno.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/syscalls.h>
34 #include <linux/file.h>
35 #include <linux/fcntl.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
40 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
41 MODULE_LICENSE("GPL");
42
43 static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC |
44 FLD_VID_SRC_OPC_ERR;
45
46 int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
47 struct sram_channel *ch,
48 unsigned int bpl, u32 risc)
49 {
50 unsigned int i, lines;
51 u32 cdt;
52
53 if (ch->cmds_start == 0) {
54 cx_write(ch->ptr1_reg, 0);
55 cx_write(ch->ptr2_reg, 0);
56 cx_write(ch->cnt2_reg, 0);
57 cx_write(ch->cnt1_reg, 0);
58 return 0;
59 }
60
61 bpl = (bpl + 7) & ~7; /* alignment */
62 cdt = ch->cdt;
63 lines = ch->fifo_size / bpl;
64
65 if (lines > 4)
66 lines = 4;
67
68 BUG_ON(lines < 2);
69
70 /* write CDT */
71 for (i = 0; i < lines; i++) {
72 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
73 cx_write(cdt + 16 * i + 4, 0);
74 cx_write(cdt + 16 * i + 8, 0);
75 cx_write(cdt + 16 * i + 12, 0);
76 }
77
78 /* write CMDS */
79 cx_write(ch->cmds_start + 0, risc);
80
81 cx_write(ch->cmds_start + 4, 0);
82 cx_write(ch->cmds_start + 8, cdt);
83 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
84 cx_write(ch->cmds_start + 16, ch->ctrl_start);
85
86 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
87
88 for (i = 24; i < 80; i += 4)
89 cx_write(ch->cmds_start + i, 0);
90
91 /* fill registers */
92 cx_write(ch->ptr1_reg, ch->fifo_start);
93 cx_write(ch->ptr2_reg, cdt);
94 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
95 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
96
97 return 0;
98 }
99
100 static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
101 __le32 *rp, unsigned int offset,
102 unsigned int bpl, u32 sync_line,
103 unsigned int lines, int fifo_enable,
104 int field_type)
105 {
106 unsigned int line, i;
107 int dist_betwn_starts = bpl * 2;
108
109 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
110
111 if (USE_RISC_NOOP_VIDEO) {
112 for (i = 0; i < NUM_NO_OPS; i++)
113 *(rp++) = cpu_to_le32(RISC_NOOP);
114 }
115
116 /* scan lines */
117 for (line = 0; line < lines; line++) {
118 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
119 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
120 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
121
122 if ((lines <= NTSC_FIELD_HEIGHT)
123 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
124 offset += dist_betwn_starts;
125 }
126 }
127
128 return rp;
129 }
130
131 static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
132 dma_addr_t databuf_phys_addr,
133 unsigned int offset, u32 sync_line,
134 unsigned int bpl, unsigned int lines,
135 int fifo_enable, int field_type)
136 {
137 unsigned int line, i;
138 struct sram_channel *sram_ch =
139 dev->channels[dev->_channel_upstream_select].sram_channels;
140 int dist_betwn_starts = bpl * 2;
141
142 /* sync instruction */
143 if (sync_line != NO_SYNC_LINE)
144 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
145
146 if (USE_RISC_NOOP_VIDEO) {
147 for (i = 0; i < NUM_NO_OPS; i++)
148 *(rp++) = cpu_to_le32(RISC_NOOP);
149 }
150
151 /* scan lines */
152 for (line = 0; line < lines; line++) {
153 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
154 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
155 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
156
157 if ((lines <= NTSC_FIELD_HEIGHT)
158 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC))
159 /* to skip the other field line */
160 offset += dist_betwn_starts;
161
162 /* check if we need to enable the FIFO after the first 4 lines
163 * For the upstream video channel, the risc engine will enable
164 * the FIFO. */
165 if (fifo_enable && line == 3) {
166 *(rp++) = RISC_WRITECR;
167 *(rp++) = sram_ch->dma_ctl;
168 *(rp++) = FLD_VID_FIFO_EN;
169 *(rp++) = 0x00000001;
170 }
171 }
172
173 return rp;
174 }
175
176 int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
177 struct pci_dev *pci,
178 unsigned int top_offset,
179 unsigned int bpl, unsigned int lines)
180 {
181 __le32 *rp;
182 int fifo_enable = 0;
183 /* get line count for single field */
184 int singlefield_lines = lines >> 1;
185 int odd_num_lines = singlefield_lines;
186 int frame = 0;
187 int frame_size = 0;
188 int databuf_offset = 0;
189 int risc_program_size = 0;
190 int risc_flag = RISC_CNT_RESET;
191 unsigned int bottom_offset = bpl;
192 dma_addr_t risc_phys_jump_addr;
193
194 if (dev->_isNTSC) {
195 odd_num_lines = singlefield_lines + 1;
196 risc_program_size = FRAME1_VID_PROG_SIZE;
197 frame_size =
198 (bpl ==
199 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
200 FRAME_SIZE_NTSC_Y422;
201 } else {
202 risc_program_size = PAL_VID_PROG_SIZE;
203 frame_size =
204 (bpl ==
205 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
206 }
207
208 /* Virtual address of Risc buffer program */
209 rp = dev->_dma_virt_addr;
210
211 for (frame = 0; frame < NUM_FRAMES; frame++) {
212 databuf_offset = frame_size * frame;
213
214 if (UNSET != top_offset) {
215 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
216 rp = cx25821_risc_field_upstream(dev, rp,
217 dev->
218 _data_buf_phys_addr +
219 databuf_offset,
220 top_offset, 0, bpl,
221 odd_num_lines,
222 fifo_enable,
223 ODD_FIELD);
224 }
225
226 fifo_enable = FIFO_DISABLE;
227
228 /* Even Field */
229 rp = cx25821_risc_field_upstream(dev, rp,
230 dev->_data_buf_phys_addr +
231 databuf_offset, bottom_offset,
232 0x200, bpl, singlefield_lines,
233 fifo_enable, EVEN_FIELD);
234
235 if (frame == 0) {
236 risc_flag = RISC_CNT_RESET;
237 risc_phys_jump_addr =
238 dev->_dma_phys_start_addr + risc_program_size;
239 } else {
240 risc_phys_jump_addr = dev->_dma_phys_start_addr;
241 risc_flag = RISC_CNT_INC;
242 }
243
244 /* Loop to 2ndFrameRISC or to Start of Risc
245 * program & generate IRQ
246 */
247 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
248 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
249 *(rp++) = cpu_to_le32(0);
250 }
251
252 return 0;
253 }
254
255 void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
256 {
257 struct sram_channel *sram_ch =
258 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_I].sram_channels;
259 u32 tmp = 0;
260
261 if (!dev->_is_running) {
262 pr_info("No video file is currently running so return!\n");
263 return;
264 }
265 /* Disable RISC interrupts */
266 tmp = cx_read(sram_ch->int_msk);
267 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
268
269 /* Turn OFF risc and fifo enable */
270 tmp = cx_read(sram_ch->dma_ctl);
271 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
272
273 /* Clear data buffer memory */
274 if (dev->_data_buf_virt_addr)
275 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
276
277 dev->_is_running = 0;
278 dev->_is_first_frame = 0;
279 dev->_frame_count = 0;
280 dev->_file_status = END_OF_FILE;
281
282 kfree(dev->_irq_queues);
283 dev->_irq_queues = NULL;
284
285 kfree(dev->_filename);
286
287 tmp = cx_read(VID_CH_MODE_SEL);
288 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
289 }
290
291 void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
292 {
293 if (dev->_is_running)
294 cx25821_stop_upstream_video_ch1(dev);
295
296 if (dev->_dma_virt_addr) {
297 pci_free_consistent(dev->pci, dev->_risc_size,
298 dev->_dma_virt_addr, dev->_dma_phys_addr);
299 dev->_dma_virt_addr = NULL;
300 }
301
302 if (dev->_data_buf_virt_addr) {
303 pci_free_consistent(dev->pci, dev->_data_buf_size,
304 dev->_data_buf_virt_addr,
305 dev->_data_buf_phys_addr);
306 dev->_data_buf_virt_addr = NULL;
307 }
308 }
309
310 int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
311 {
312 struct file *myfile;
313 int frame_index_temp = dev->_frame_index;
314 int i = 0;
315 int line_size =
316 (dev->_pixel_format ==
317 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
318 int frame_size = 0;
319 int frame_offset = 0;
320 ssize_t vfs_read_retval = 0;
321 char mybuf[line_size];
322 loff_t file_offset;
323 loff_t pos;
324 mm_segment_t old_fs;
325
326 if (dev->_file_status == END_OF_FILE)
327 return 0;
328
329 if (dev->_isNTSC) {
330 frame_size =
331 (line_size ==
332 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
333 FRAME_SIZE_NTSC_Y422;
334 } else {
335 frame_size =
336 (line_size ==
337 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
338 }
339
340 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
341 file_offset = dev->_frame_count * frame_size;
342
343 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
344
345 if (IS_ERR(myfile)) {
346 const int open_errno = -PTR_ERR(myfile);
347 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
348 __func__, dev->_filename, open_errno);
349 return PTR_ERR(myfile);
350 } else {
351 if (!(myfile->f_op)) {
352 pr_err("%s(): File has no file operations registered!\n",
353 __func__);
354 filp_close(myfile, NULL);
355 return -EIO;
356 }
357
358 if (!myfile->f_op->read) {
359 pr_err("%s(): File has no READ operations registered!\n",
360 __func__);
361 filp_close(myfile, NULL);
362 return -EIO;
363 }
364
365 pos = myfile->f_pos;
366 old_fs = get_fs();
367 set_fs(KERNEL_DS);
368
369 for (i = 0; i < dev->_lines_count; i++) {
370 pos = file_offset;
371
372 vfs_read_retval =
373 vfs_read(myfile, mybuf, line_size, &pos);
374
375 if (vfs_read_retval > 0 && vfs_read_retval == line_size
376 && dev->_data_buf_virt_addr != NULL) {
377 memcpy((void *)(dev->_data_buf_virt_addr +
378 frame_offset / 4), mybuf,
379 vfs_read_retval);
380 }
381
382 file_offset += vfs_read_retval;
383 frame_offset += vfs_read_retval;
384
385 if (vfs_read_retval < line_size) {
386 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
387 __func__);
388 break;
389 }
390 }
391
392 if (i > 0)
393 dev->_frame_count++;
394
395 dev->_file_status =
396 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
397
398 set_fs(old_fs);
399 filp_close(myfile, NULL);
400 }
401
402 return 0;
403 }
404
405 static void cx25821_vidups_handler(struct work_struct *work)
406 {
407 struct cx25821_dev *dev =
408 container_of(work, struct cx25821_dev, _irq_work_entry);
409
410 if (!dev) {
411 pr_err("ERROR %s(): since container_of(work_struct) FAILED!\n",
412 __func__);
413 return;
414 }
415
416 cx25821_get_frame(dev,
417 dev->channels[dev->_channel_upstream_select].
418 sram_channels);
419 }
420
421 int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
422 {
423 struct file *myfile;
424 int i = 0, j = 0;
425 int line_size =
426 (dev->_pixel_format ==
427 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
428 ssize_t vfs_read_retval = 0;
429 char mybuf[line_size];
430 loff_t pos;
431 loff_t offset = (unsigned long)0;
432 mm_segment_t old_fs;
433
434 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
435
436 if (IS_ERR(myfile)) {
437 const int open_errno = -PTR_ERR(myfile);
438 pr_err("%s(): ERROR opening file(%s) with errno = %d!\n",
439 __func__, dev->_filename, open_errno);
440 return PTR_ERR(myfile);
441 } else {
442 if (!(myfile->f_op)) {
443 pr_err("%s(): File has no file operations registered!\n",
444 __func__);
445 filp_close(myfile, NULL);
446 return -EIO;
447 }
448
449 if (!myfile->f_op->read) {
450 pr_err("%s(): File has no READ operations registered! Returning\n",
451 __func__);
452 filp_close(myfile, NULL);
453 return -EIO;
454 }
455
456 pos = myfile->f_pos;
457 old_fs = get_fs();
458 set_fs(KERNEL_DS);
459
460 for (j = 0; j < NUM_FRAMES; j++) {
461 for (i = 0; i < dev->_lines_count; i++) {
462 pos = offset;
463
464 vfs_read_retval =
465 vfs_read(myfile, mybuf, line_size, &pos);
466
467 if (vfs_read_retval > 0
468 && vfs_read_retval == line_size
469 && dev->_data_buf_virt_addr != NULL) {
470 memcpy((void *)(dev->
471 _data_buf_virt_addr +
472 offset / 4), mybuf,
473 vfs_read_retval);
474 }
475
476 offset += vfs_read_retval;
477
478 if (vfs_read_retval < line_size) {
479 pr_info("Done: exit %s() since no more bytes to read from Video file\n",
480 __func__);
481 break;
482 }
483 }
484
485 if (i > 0)
486 dev->_frame_count++;
487
488 if (vfs_read_retval < line_size)
489 break;
490 }
491
492 dev->_file_status =
493 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
494
495 set_fs(old_fs);
496 myfile->f_pos = 0;
497 filp_close(myfile, NULL);
498 }
499
500 return 0;
501 }
502
503 int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
504 struct sram_channel *sram_ch, int bpl)
505 {
506 int ret = 0;
507 dma_addr_t dma_addr;
508 dma_addr_t data_dma_addr;
509
510 if (dev->_dma_virt_addr != NULL) {
511 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
512 dev->_dma_virt_addr, dev->_dma_phys_addr);
513 }
514
515 dev->_dma_virt_addr =
516 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
517 &dma_addr);
518 dev->_dma_virt_start_addr = dev->_dma_virt_addr;
519 dev->_dma_phys_start_addr = dma_addr;
520 dev->_dma_phys_addr = dma_addr;
521 dev->_risc_size = dev->upstream_riscbuf_size;
522
523 if (!dev->_dma_virt_addr) {
524 pr_err("FAILED to allocate memory for Risc buffer! Returning\n");
525 return -ENOMEM;
526 }
527
528 /* Clear memory at address */
529 memset(dev->_dma_virt_addr, 0, dev->_risc_size);
530
531 if (dev->_data_buf_virt_addr != NULL) {
532 pci_free_consistent(dev->pci, dev->upstream_databuf_size,
533 dev->_data_buf_virt_addr,
534 dev->_data_buf_phys_addr);
535 }
536 /* For Video Data buffer allocation */
537 dev->_data_buf_virt_addr =
538 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
539 &data_dma_addr);
540 dev->_data_buf_phys_addr = data_dma_addr;
541 dev->_data_buf_size = dev->upstream_databuf_size;
542
543 if (!dev->_data_buf_virt_addr) {
544 pr_err("FAILED to allocate memory for data buffer! Returning\n");
545 return -ENOMEM;
546 }
547
548 /* Clear memory at address */
549 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
550
551 ret = cx25821_openfile(dev, sram_ch);
552 if (ret < 0)
553 return ret;
554
555 /* Create RISC programs */
556 ret =
557 cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
558 dev->_lines_count);
559 if (ret < 0) {
560 pr_info("Failed creating Video Upstream Risc programs!\n");
561 goto error;
562 }
563
564 return 0;
565
566 error:
567 return ret;
568 }
569
570 int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
571 u32 status)
572 {
573 u32 int_msk_tmp;
574 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
575 int singlefield_lines = NTSC_FIELD_HEIGHT;
576 int line_size_in_bytes = Y422_LINE_SZ;
577 int odd_risc_prog_size = 0;
578 dma_addr_t risc_phys_jump_addr;
579 __le32 *rp;
580
581 if (status & FLD_VID_SRC_RISC1) {
582 /* We should only process one program per call */
583 u32 prog_cnt = cx_read(channel->gpcnt);
584
585 /* Since we've identified our IRQ, clear our bits from the
586 * interrupt mask and interrupt status registers */
587 int_msk_tmp = cx_read(channel->int_msk);
588 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
589 cx_write(channel->int_stat, _intr_msk);
590
591 spin_lock(&dev->slock);
592
593 dev->_frame_index = prog_cnt;
594
595 queue_work(dev->_irq_queues, &dev->_irq_work_entry);
596
597 if (dev->_is_first_frame) {
598 dev->_is_first_frame = 0;
599
600 if (dev->_isNTSC) {
601 singlefield_lines += 1;
602 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
603 } else {
604 singlefield_lines = PAL_FIELD_HEIGHT;
605 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
606 }
607
608 if (dev->_dma_virt_start_addr != NULL) {
609 line_size_in_bytes =
610 (dev->_pixel_format ==
611 PIXEL_FRMT_411) ? Y411_LINE_SZ :
612 Y422_LINE_SZ;
613 risc_phys_jump_addr =
614 dev->_dma_phys_start_addr +
615 odd_risc_prog_size;
616
617 rp = cx25821_update_riscprogram(dev,
618 dev->_dma_virt_start_addr, TOP_OFFSET,
619 line_size_in_bytes, 0x0,
620 singlefield_lines, FIFO_DISABLE,
621 ODD_FIELD);
622
623 /* Jump to Even Risc program of 1st Frame */
624 *(rp++) = cpu_to_le32(RISC_JUMP);
625 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
626 *(rp++) = cpu_to_le32(0);
627 }
628 }
629
630 spin_unlock(&dev->slock);
631 } else {
632 if (status & FLD_VID_SRC_UF)
633 pr_err("%s(): Video Received Underflow Error Interrupt!\n",
634 __func__);
635
636 if (status & FLD_VID_SRC_SYNC)
637 pr_err("%s(): Video Received Sync Error Interrupt!\n",
638 __func__);
639
640 if (status & FLD_VID_SRC_OPC_ERR)
641 pr_err("%s(): Video Received OpCode Error Interrupt!\n",
642 __func__);
643 }
644
645 if (dev->_file_status == END_OF_FILE) {
646 pr_err("EOF Channel 1 Framecount = %d\n", dev->_frame_count);
647 return -1;
648 }
649 /* ElSE, set the interrupt mask register, re-enable irq. */
650 int_msk_tmp = cx_read(channel->int_msk);
651 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
652
653 return 0;
654 }
655
656 static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
657 {
658 struct cx25821_dev *dev = dev_id;
659 u32 msk_stat, vid_status;
660 int handled = 0;
661 int channel_num = 0;
662 struct sram_channel *sram_ch;
663
664 if (!dev)
665 return -1;
666
667 channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
668
669 sram_ch = dev->channels[channel_num].sram_channels;
670
671 msk_stat = cx_read(sram_ch->int_mstat);
672 vid_status = cx_read(sram_ch->int_stat);
673
674 /* Only deal with our interrupt */
675 if (vid_status) {
676 handled =
677 cx25821_video_upstream_irq(dev, channel_num, vid_status);
678 }
679
680 if (handled < 0)
681 cx25821_stop_upstream_video_ch1(dev);
682 else
683 handled += handled;
684
685 return IRQ_RETVAL(handled);
686 }
687
688 void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
689 int pix_format)
690 {
691 int width = WIDTH_D1;
692 int height = dev->_lines_count;
693 int num_lines, odd_num_lines;
694 u32 value;
695 int vip_mode = OUTPUT_FRMT_656;
696
697 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
698 value &= 0xFFFFFFEF;
699 value |= dev->_isNTSC ? 0 : 0x10;
700 cx_write(ch->vid_fmt_ctl, value);
701
702 /* set number of active pixels in each line.
703 * Default is 720 pixels in both NTSC and PAL format */
704 cx_write(ch->vid_active_ctl1, width);
705
706 num_lines = (height / 2) & 0x3FF;
707 odd_num_lines = num_lines;
708
709 if (dev->_isNTSC)
710 odd_num_lines += 1;
711
712 value = (num_lines << 16) | odd_num_lines;
713
714 /* set number of active lines in field 0 (top) and field 1 (bottom) */
715 cx_write(ch->vid_active_ctl2, value);
716
717 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
718 }
719
720 int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
721 struct sram_channel *sram_ch)
722 {
723 u32 tmp = 0;
724 int err = 0;
725
726 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
727 * channel A-C
728 */
729 tmp = cx_read(VID_CH_MODE_SEL);
730 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
731
732 /* Set the physical start address of the RISC program in the initial
733 * program counter(IPC) member of the cmds.
734 */
735 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
736 /* Risc IPC High 64 bits 63-32 */
737 cx_write(sram_ch->cmds_start + 4, 0);
738
739 /* reset counter */
740 cx_write(sram_ch->gpcnt_ctl, 3);
741
742 /* Clear our bits from the interrupt status register. */
743 cx_write(sram_ch->int_stat, _intr_msk);
744
745 /* Set the interrupt mask register, enable irq. */
746 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
747 tmp = cx_read(sram_ch->int_msk);
748 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
749
750 err =
751 request_irq(dev->pci->irq, cx25821_upstream_irq,
752 IRQF_SHARED, dev->name, dev);
753 if (err < 0) {
754 pr_err("%s: can't get upstream IRQ %d\n",
755 dev->name, dev->pci->irq);
756 goto fail_irq;
757 }
758
759 /* Start the DMA engine */
760 tmp = cx_read(sram_ch->dma_ctl);
761 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
762
763 dev->_is_running = 1;
764 dev->_is_first_frame = 1;
765
766 return 0;
767
768 fail_irq:
769 cx25821_dev_unregister(dev);
770 return err;
771 }
772
773 int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
774 int pixel_format)
775 {
776 struct sram_channel *sram_ch;
777 u32 tmp;
778 int retval = 0;
779 int err = 0;
780 int data_frame_size = 0;
781 int risc_buffer_size = 0;
782 int str_length = 0;
783
784 if (dev->_is_running) {
785 pr_info("Video Channel is still running so return!\n");
786 return 0;
787 }
788
789 dev->_channel_upstream_select = channel_select;
790 sram_ch = dev->channels[channel_select].sram_channels;
791
792 INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
793 dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
794
795 if (!dev->_irq_queues) {
796 pr_err("create_singlethread_workqueue() for Video FAILED!\n");
797 return -ENOMEM;
798 }
799 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
800 * channel A-C
801 */
802 tmp = cx_read(VID_CH_MODE_SEL);
803 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
804
805 dev->_is_running = 0;
806 dev->_frame_count = 0;
807 dev->_file_status = RESET_STATUS;
808 dev->_lines_count = dev->_isNTSC ? 480 : 576;
809 dev->_pixel_format = pixel_format;
810 dev->_line_size =
811 (dev->_pixel_format ==
812 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
813 data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
814 risc_buffer_size =
815 dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
816
817 if (dev->input_filename) {
818 str_length = strlen(dev->input_filename);
819 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
820
821 if (!dev->_filename)
822 goto error;
823
824 memcpy(dev->_filename, dev->input_filename, str_length + 1);
825 } else {
826 str_length = strlen(dev->_defaultname);
827 dev->_filename = kmalloc(str_length + 1, GFP_KERNEL);
828
829 if (!dev->_filename)
830 goto error;
831
832 memcpy(dev->_filename, dev->_defaultname, str_length + 1);
833 }
834
835 /* Default if filename is empty string */
836 if (strcmp(dev->input_filename, "") == 0) {
837 if (dev->_isNTSC) {
838 dev->_filename =
839 (dev->_pixel_format ==
840 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
841 "/root/vidtest.yuv";
842 } else {
843 dev->_filename =
844 (dev->_pixel_format ==
845 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
846 "/root/pal422.yuv";
847 }
848 }
849
850 dev->_is_running = 0;
851 dev->_frame_count = 0;
852 dev->_file_status = RESET_STATUS;
853 dev->_lines_count = dev->_isNTSC ? 480 : 576;
854 dev->_pixel_format = pixel_format;
855 dev->_line_size =
856 (dev->_pixel_format ==
857 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
858
859 retval =
860 cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
861 0);
862
863 /* setup fifo + format */
864 cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
865
866 dev->upstream_riscbuf_size = risc_buffer_size * 2;
867 dev->upstream_databuf_size = data_frame_size * 2;
868
869 /* Allocating buffers and prepare RISC program */
870 retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
871 if (retval < 0) {
872 pr_err("%s: Failed to set up Video upstream buffers!\n",
873 dev->name);
874 goto error;
875 }
876
877 cx25821_start_video_dma_upstream(dev, sram_ch);
878
879 return 0;
880
881 error:
882 cx25821_dev_unregister(dev);
883
884 return err;
885 }
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