drivers/staging/gma500/psb_drm.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  * Copyright (c) 2008, Tungsten Graphics Inc.  Cedar Park, TX., USA.
   5  * All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  **************************************************************************/
  21
  22 #ifndef _PSB_DRM_H_
  23 #define _PSB_DRM_H_
  24
  25 #define PSB_NUM_PIPE 3
  26
  27 #define PSB_GPU_ACCESS_READ         (1ULL << 32)
  28 #define PSB_GPU_ACCESS_WRITE        (1ULL << 33)
  29 #define PSB_GPU_ACCESS_MASK         (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
  30
  31 #define PSB_BO_FLAG_COMMAND         (1ULL << 52)
  32
  33 /*
  34  * Feedback components:
  35  */
  36
  37 struct drm_psb_sizes_arg {
  38         u32 ta_mem_size;
  39         u32 mmu_size;
  40         u32 pds_size;
  41         u32 rastgeom_size;
  42         u32 tt_size;
  43         u32 vram_size;
  44 };
  45
  46 struct drm_psb_dpst_lut_arg {
  47         uint8_t lut[256];
  48         int output_id;
  49 };
  50
  51 #define PSB_DC_CRTC_SAVE 0x01
  52 #define PSB_DC_CRTC_RESTORE 0x02
  53 #define PSB_DC_OUTPUT_SAVE 0x04
  54 #define PSB_DC_OUTPUT_RESTORE 0x08
  55 #define PSB_DC_CRTC_MASK 0x03
  56 #define PSB_DC_OUTPUT_MASK 0x0C
  57
  58 struct drm_psb_dc_state_arg {
  59         u32 flags;
  60         u32 obj_id;
  61 };
  62
  63 struct drm_psb_mode_operation_arg {
  64         u32 obj_id;
  65         u16 operation;
  66         struct drm_mode_modeinfo mode;
  67         void *data;
  68 };
  69
  70 struct drm_psb_stolen_memory_arg {
  71         u32 base;
  72         u32 size;
  73 };
  74
  75 /*Display Register Bits*/
  76 #define REGRWBITS_PFIT_CONTROLS                 (1 << 0)
  77 #define REGRWBITS_PFIT_AUTOSCALE_RATIOS         (1 << 1)
  78 #define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS  (1 << 2)
  79 #define REGRWBITS_PIPEASRC                      (1 << 3)
  80 #define REGRWBITS_PIPEBSRC                      (1 << 4)
  81 #define REGRWBITS_VTOTAL_A                      (1 << 5)
  82 #define REGRWBITS_VTOTAL_B                      (1 << 6)
  83 #define REGRWBITS_DSPACNTR      (1 << 8)
  84 #define REGRWBITS_DSPBCNTR      (1 << 9)
  85 #define REGRWBITS_DSPCCNTR      (1 << 10)
  86
  87 /*Overlay Register Bits*/
  88 #define OV_REGRWBITS_OVADD                      (1 << 0)
  89 #define OV_REGRWBITS_OGAM_ALL                   (1 << 1)
  90
  91 #define OVC_REGRWBITS_OVADD                  (1 << 2)
  92 #define OVC_REGRWBITS_OGAM_ALL                  (1 << 3)
  93
  94 struct drm_psb_register_rw_arg {
  95         u32 b_force_hw_on;
  96
  97         u32 display_read_mask;
  98         u32 display_write_mask;
  99
 100         struct {
 101                 u32 pfit_controls;
 102                 u32 pfit_autoscale_ratios;
 103                 u32 pfit_programmed_scale_ratios;
 104                 u32 pipeasrc;
 105                 u32 pipebsrc;
 106                 u32 vtotal_a;
 107                 u32 vtotal_b;
 108         } display;
 109
 110         u32 overlay_read_mask;
 111         u32 overlay_write_mask;
 112
 113         struct {
 114                 u32 OVADD;
 115                 u32 OGAMC0;
 116                 u32 OGAMC1;
 117                 u32 OGAMC2;
 118                 u32 OGAMC3;
 119                 u32 OGAMC4;
 120                 u32 OGAMC5;
 121                 u32 IEP_ENABLED;
 122                 u32 IEP_BLE_MINMAX;
 123                 u32 IEP_BSSCC_CONTROL;
 124                 u32 b_wait_vblank;
 125         } overlay;
 126
 127         u32 sprite_enable_mask;
 128         u32 sprite_disable_mask;
 129
 130         struct {
 131                 u32 dspa_control;
 132                 u32 dspa_key_value;
 133                 u32 dspa_key_mask;
 134                 u32 dspc_control;
 135                 u32 dspc_stride;
 136                 u32 dspc_position;
 137                 u32 dspc_linear_offset;
 138                 u32 dspc_size;
 139                 u32 dspc_surface;
 140         } sprite;
 141
 142         u32 subpicture_enable_mask;
 143         u32 subpicture_disable_mask;
 144 };
 145
 146 /* Controlling the kernel modesetting buffers */
 147
 148 #define DRM_PSB_SIZES           0x07
 149 #define DRM_PSB_FUSE_REG        0x08
 150 #define DRM_PSB_DC_STATE        0x0A
 151 #define DRM_PSB_ADB             0x0B
 152 #define DRM_PSB_MODE_OPERATION  0x0C
 153 #define DRM_PSB_STOLEN_MEMORY   0x0D
 154 #define DRM_PSB_REGISTER_RW     0x0E
 155
 156 /*
 157  * NOTE: Add new commands here, but increment
 158  * the values below and increment their
 159  * corresponding defines where they're
 160  * defined elsewhere.
 161  */
 162
 163 #define DRM_PSB_GEM_CREATE      0x10
 164 #define DRM_PSB_2D_OP           0x11
 165 #define DRM_PSB_GEM_MMAP        0x12
 166 #define DRM_PSB_DPST            0x1B
 167 #define DRM_PSB_GAMMA           0x1C
 168 #define DRM_PSB_DPST_BL         0x1D
 169 #define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F
 170
 171 #define PSB_MODE_OPERATION_MODE_VALID   0x01
 172 #define PSB_MODE_OPERATION_SET_DC_BASE  0x02
 173
 174 struct drm_psb_get_pipe_from_crtc_id_arg {
 175         /** ID of CRTC being requested **/
 176         u32 crtc_id;
 177
 178         /** pipe of requested CRTC **/
 179         u32 pipe;
 180 };
 181
 182 /* FIXME: move this into a medfield header once we are sure it isn't needed for an
 183    ioctl  */
 184 struct psb_drm_dpu_rect {
 185         int x, y;
 186         int width, height;
 187 };
 188
 189 struct drm_psb_gem_create {
 190         __u64 size;
 191         __u32 handle;
 192         __u32 flags;
 193 #define PSB_GEM_CREATE_STOLEN           1       /* Stolen memory can be used */
 194 };
 195
 196 #define PSB_2D_OP_BUFLEN                16
 197
 198 struct drm_psb_2d_op {
 199         __u32 src;              /* Handles, only src supported right now */
 200         __u32 dst;
 201         __u32 mask;
 202         __u32 pat;
 203         __u32 size;             /* In dwords of command */
 204         __u32 spare;            /* And bumps array to u64 align */
 205         __u32 cmd[PSB_2D_OP_BUFLEN];
 206 };
 207
 208 struct drm_psb_gem_mmap {
 209         __u32 handle;
 210         __u32 pad;
 211         /**
 212          * Fake offset to use for subsequent mmap call
 213          *
 214          * This is a fixed-size type for 32/64 compatibility.
 215          */
 216         __u64 offset;
 217 };
 218
 219 #endif