drivers/staging/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/kref.h>
  24
  25 #include <drm/drmP.h>
  26 #include "drm_global.h"
  27 #include "gem_glue.h"
  28 #include "psb_drm.h"
  29 #include "psb_reg.h"
  30 #include "psb_intel_drv.h"
  31 #include "gtt.h"
  32 #include "power.h"
  33 #include "mrst.h"
  34 #include "medfield.h"
  35
  36 /* Append new drm mode definition here, align with libdrm definition */
  37 #define DRM_MODE_SCALE_NO_SCALE         2
  38
  39 enum {
  40         CHIP_PSB_8108 = 0,              /* Poulsbo */
  41         CHIP_PSB_8109 = 1,              /* Poulsbo */
  42         CHIP_MRST_4100 = 2,             /* Moorestown/Oaktrail */
  43         CHIP_MFLD_0130 = 3,             /* Medfield */
  44 };
  45
  46 #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
  47 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
  48 #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
  49
  50 /*
  51  * Driver definitions
  52  */
  53
  54 #define DRIVER_NAME "gma500"
  55 #define DRIVER_DESC "DRM driver for the Intel GMA500"
  56
  57 #define PSB_DRM_DRIVER_DATE "2011-06-06"
  58 #define PSB_DRM_DRIVER_MAJOR 1
  59 #define PSB_DRM_DRIVER_MINOR 0
  60 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  61
  62 /*
  63  *      Hardware offsets
  64  */
  65 #define PSB_VDC_OFFSET           0x00000000
  66 #define PSB_VDC_SIZE             0x000080000
  67 #define MRST_MMIO_SIZE           0x0000C0000
  68 #define MDFLD_MMIO_SIZE          0x000100000
  69 #define PSB_SGX_SIZE             0x8000
  70 #define PSB_SGX_OFFSET           0x00040000
  71 #define MRST_SGX_OFFSET          0x00080000
  72 /*
  73  *      PCI resource identifiers
  74  */
  75 #define PSB_MMIO_RESOURCE        0
  76 #define PSB_GATT_RESOURCE        2
  77 #define PSB_GTT_RESOURCE         3
  78 /*
  79  *      PCI configuration
  80  */
  81 #define PSB_GMCH_CTRL            0x52
  82 #define PSB_BSM                  0x5C
  83 #define _PSB_GMCH_ENABLED        0x4
  84 #define PSB_PGETBL_CTL           0x2020
  85 #define _PSB_PGETBL_ENABLED      0x00000001
  86 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  87
  88 /* To get rid of */
  89 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  90 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  91
  92 /*
  93  *      SGX side MMU definitions (these can probably go)
  94  */
  95
  96 /*
  97  *      Flags for external memory type field.
  98  */
  99 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
 100 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
 101 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
 102 /*
 103  *      PTE's and PDE's
 104  */
 105 #define PSB_PDE_MASK              0x003FFFFF
 106 #define PSB_PDE_SHIFT             22
 107 #define PSB_PTE_SHIFT             12
 108 /*
 109  *      Cache control
 110  */
 111 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 112 #define PSB_PTE_WO                0x0002        /* Write only */
 113 #define PSB_PTE_RO                0x0004        /* Read only */
 114 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 115
 116 /*
 117  *      VDC registers and bits
 118  */
 119 #define PSB_MSVDX_CLOCKGATING     0x2064
 120 #define PSB_TOPAZ_CLOCKGATING     0x2068
 121 #define PSB_HWSTAM                0x2098
 122 #define PSB_INSTPM                0x20C0
 123 #define PSB_INT_IDENTITY_R        0x20A4
 124 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 125 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 126 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 127 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 128 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 129 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 130 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 131 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 132 #define _MDFLD_MIPIA_FLAG         (1<<16)
 133 #define _MDFLD_MIPIC_FLAG         (1<<17)
 134 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 135 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 136 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 137
 138 #define _PSB_PIPE_EVENT_FLAG    (_PSB_VSYNC_PIPEA_FLAG | \
 139                                  _PSB_VSYNC_PIPEB_FLAG)
 140
 141 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 142 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
 143                                   _MDFLD_PIPEB_EVENT_FLAG | \
 144                                   _PSB_PIPEA_EVENT_FLAG | \
 145                                   _PSB_VSYNC_PIPEA_FLAG | \
 146                                   _MDFLD_MIPIA_FLAG | \
 147                                   _MDFLD_MIPIC_FLAG)
 148 #define PSB_INT_IDENTITY_R        0x20A4
 149 #define PSB_INT_MASK_R            0x20A8
 150 #define PSB_INT_ENABLE_R          0x20A0
 151
 152 #define _PSB_MMU_ER_MASK      0x0001FF00
 153 #define _PSB_MMU_ER_HOST      (1 << 16)
 154 #define GPIOA                   0x5010
 155 #define GPIOB                   0x5014
 156 #define GPIOC                   0x5018
 157 #define GPIOD                   0x501c
 158 #define GPIOE                   0x5020
 159 #define GPIOF                   0x5024
 160 #define GPIOG                   0x5028
 161 #define GPIOH                   0x502c
 162 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 163 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 164 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 165 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 166 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 167 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 168 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 169 #define GPIO_DATA_DIR_MASK              (1 << 8)
 170 #define GPIO_DATA_DIR_IN                (0 << 9)
 171 #define GPIO_DATA_DIR_OUT               (1 << 9)
 172 #define GPIO_DATA_VAL_MASK              (1 << 10)
 173 #define GPIO_DATA_VAL_OUT               (1 << 11)
 174 #define GPIO_DATA_VAL_IN                (1 << 12)
 175 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 176
 177 #define VCLK_DIVISOR_VGA0   0x6000
 178 #define VCLK_DIVISOR_VGA1   0x6004
 179 #define VCLK_POST_DIV       0x6010
 180
 181 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 182 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 183 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 184 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 185 #define PSB_COMM_USER_IRQ (1024 >> 2)
 186 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 187 #define PSB_COMM_FW (2048 >> 2)
 188
 189 #define PSB_UIRQ_VISTEST               1
 190 #define PSB_UIRQ_OOM_REPLY             2
 191 #define PSB_UIRQ_FIRE_TA_REPLY         3
 192 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 193
 194 #define PSB_2D_SIZE (256*1024*1024)
 195 #define PSB_MAX_RELOC_PAGES 1024
 196
 197 #define PSB_LOW_REG_OFFS 0x0204
 198 #define PSB_HIGH_REG_OFFS 0x0600
 199
 200 #define PSB_NUM_VBLANKS 2
 201
 202
 203 #define PSB_2D_SIZE (256*1024*1024)
 204 #define PSB_MAX_RELOC_PAGES 1024
 205
 206 #define PSB_LOW_REG_OFFS 0x0204
 207 #define PSB_HIGH_REG_OFFS 0x0600
 208
 209 #define PSB_NUM_VBLANKS 2
 210 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 211 #define PSB_LID_DELAY (DRM_HZ / 10)
 212
 213 #define MDFLD_PNW_B0 0x04
 214 #define MDFLD_PNW_C0 0x08
 215
 216 #define MDFLD_DSR_2D_3D_0       (1 << 0)
 217 #define MDFLD_DSR_2D_3D_2       (1 << 1)
 218 #define MDFLD_DSR_CURSOR_0      (1 << 2)
 219 #define MDFLD_DSR_CURSOR_2      (1 << 3)
 220 #define MDFLD_DSR_OVERLAY_0     (1 << 4)
 221 #define MDFLD_DSR_OVERLAY_2     (1 << 5)
 222 #define MDFLD_DSR_MIPI_CONTROL  (1 << 6)
 223 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
 224 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
 225 #define MDFLD_DSR_2D_3D         (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
 226
 227 #define MDFLD_DSR_RR            45
 228 #define MDFLD_DPU_ENABLE        (1 << 31)
 229 #define MDFLD_DSR_FULLSCREEN    (1 << 30)
 230 #define MDFLD_DSR_DELAY         (DRM_HZ / MDFLD_DSR_RR)
 231
 232 #define PSB_PWR_STATE_ON                1
 233 #define PSB_PWR_STATE_OFF               2
 234
 235 #define PSB_PMPOLICY_NOPM               0
 236 #define PSB_PMPOLICY_CLOCKGATING        1
 237 #define PSB_PMPOLICY_POWERDOWN          2
 238
 239 #define PSB_PMSTATE_POWERUP             0
 240 #define PSB_PMSTATE_CLOCKGATED          1
 241 #define PSB_PMSTATE_POWERDOWN           2
 242 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 243 #define PSB_PCIx_MSI_DATA_LOC           0x98
 244
 245 /* Medfield crystal settings */
 246 #define KSEL_CRYSTAL_19 1
 247 #define KSEL_BYPASS_19 5
 248 #define KSEL_BYPASS_25 6
 249 #define KSEL_BYPASS_83_100 7
 250
 251 struct opregion_header;
 252 struct opregion_acpi;
 253 struct opregion_swsci;
 254 struct opregion_asle;
 255
 256 struct psb_intel_opregion {
 257         struct opregion_header *header;
 258         struct opregion_acpi *acpi;
 259         struct opregion_swsci *swsci;
 260         struct opregion_asle *asle;
 261         int enabled;
 262 };
 263
 264 struct psb_ops;
 265
 266 struct drm_psb_private {
 267         struct drm_device *dev;
 268         const struct psb_ops *ops;
 269
 270         struct psb_gtt gtt;
 271
 272         /* GTT Memory manager */
 273         struct psb_gtt_mm *gtt_mm;
 274         struct page *scratch_page;
 275         u32 *gtt_map;
 276         uint32_t stolen_base;
 277         void *vram_addr;
 278         unsigned long vram_stolen_size;
 279         int gtt_initialized;
 280         u16 gmch_ctrl;          /* Saved GTT setup */
 281         u32 pge_ctl;
 282
 283         struct mutex gtt_mutex;
 284         struct resource *gtt_mem;       /* Our PCI resource */
 285
 286         struct psb_mmu_driver *mmu;
 287         struct psb_mmu_pd *pf_pd;
 288
 289         /*
 290          * Register base
 291          */
 292
 293         uint8_t *sgx_reg;
 294         uint8_t *vdc_reg;
 295         uint32_t gatt_free_offset;
 296
 297         /*
 298          * Fencing / irq.
 299          */
 300
 301         uint32_t vdc_irq_mask;
 302         uint32_t pipestat[PSB_NUM_PIPE];
 303
 304         spinlock_t irqmask_lock;
 305
 306         /*
 307          * Power
 308          */
 309
 310         bool suspended;
 311         bool display_power;
 312         int display_count;
 313
 314         /*
 315          * Modesetting
 316          */
 317         struct psb_intel_mode_device mode_dev;
 318
 319         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 320         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 321         uint32_t num_pipe;
 322
 323         /*
 324          * OSPM info (Power management base) (can go ?)
 325          */
 326         uint32_t ospm_base;
 327
 328         /*
 329          * Sizes info
 330          */
 331
 332         struct drm_psb_sizes_arg sizes;
 333
 334         u32 fuse_reg_value;
 335         u32 video_device_fuse;
 336
 337         /* PCI revision ID for B0:D2:F0 */
 338         uint8_t platform_rev_id;
 339
 340         /*
 341          * LVDS info
 342          */
 343         int backlight_duty_cycle;       /* restore backlight to this value */
 344         bool panel_wants_dither;
 345         struct drm_display_mode *panel_fixed_mode;
 346         struct drm_display_mode *lfp_lvds_vbt_mode;
 347         struct drm_display_mode *sdvo_lvds_vbt_mode;
 348
 349         struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
 350         struct psb_intel_i2c_chan *lvds_i2c_bus;
 351
 352         /* Feature bits from the VBIOS */
 353         unsigned int int_tv_support:1;
 354         unsigned int lvds_dither:1;
 355         unsigned int lvds_vbt:1;
 356         unsigned int int_crt_support:1;
 357         unsigned int lvds_use_ssc:1;
 358         int lvds_ssc_freq;
 359         bool is_lvds_on;
 360         bool is_mipi_on;
 361         u32 mipi_ctrl_display;
 362
 363         unsigned int core_freq;
 364         uint32_t iLVDS_enable;
 365
 366         /* Runtime PM state */
 367         int rpm_enabled;
 368
 369         /* MID specific */
 370         struct mrst_vbt vbt_data;
 371         struct mrst_gct_data gct_data;
 372
 373         /* MIPI Panel type etc */
 374         int panel_id;
 375         bool dual_mipi;         /* dual display - DPI & DBI */
 376         bool dpi_panel_on;      /* The DPI panel power is on */
 377         bool dpi_panel_on2;     /* The DPI panel power is on */
 378         bool dbi_panel_on;      /* The DBI panel power is on */
 379         bool dbi_panel_on2;     /* The DBI panel power is on */
 380         u32 dsr_fb_update;      /* DSR FB update counter */
 381
 382         /* Moorestown HDMI state */
 383         struct mrst_hdmi_dev *hdmi_priv;
 384
 385         /* Moorestown pipe config register value cache */
 386         uint32_t pipeconf;
 387         uint32_t pipeconf1;
 388         uint32_t pipeconf2;
 389
 390         /* Moorestown plane control register value cache */
 391         uint32_t dspcntr;
 392         uint32_t dspcntr1;
 393         uint32_t dspcntr2;
 394
 395         /* Moorestown MM backlight cache */
 396         uint8_t saveBKLTCNT;
 397         uint8_t saveBKLTREQ;
 398         uint8_t saveBKLTBRTL;
 399
 400         /*
 401          * Register state
 402          */
 403         uint32_t saveDSPACNTR;
 404         uint32_t saveDSPBCNTR;
 405         uint32_t savePIPEACONF;
 406         uint32_t savePIPEBCONF;
 407         uint32_t savePIPEASRC;
 408         uint32_t savePIPEBSRC;
 409         uint32_t saveFPA0;
 410         uint32_t saveFPA1;
 411         uint32_t saveDPLL_A;
 412         uint32_t saveDPLL_A_MD;
 413         uint32_t saveHTOTAL_A;
 414         uint32_t saveHBLANK_A;
 415         uint32_t saveHSYNC_A;
 416         uint32_t saveVTOTAL_A;
 417         uint32_t saveVBLANK_A;
 418         uint32_t saveVSYNC_A;
 419         uint32_t saveDSPASTRIDE;
 420         uint32_t saveDSPASIZE;
 421         uint32_t saveDSPAPOS;
 422         uint32_t saveDSPABASE;
 423         uint32_t saveDSPASURF;
 424         uint32_t saveDSPASTATUS;
 425         uint32_t saveFPB0;
 426         uint32_t saveFPB1;
 427         uint32_t saveDPLL_B;
 428         uint32_t saveDPLL_B_MD;
 429         uint32_t saveHTOTAL_B;
 430         uint32_t saveHBLANK_B;
 431         uint32_t saveHSYNC_B;
 432         uint32_t saveVTOTAL_B;
 433         uint32_t saveVBLANK_B;
 434         uint32_t saveVSYNC_B;
 435         uint32_t saveDSPBSTRIDE;
 436         uint32_t saveDSPBSIZE;
 437         uint32_t saveDSPBPOS;
 438         uint32_t saveDSPBBASE;
 439         uint32_t saveDSPBSURF;
 440         uint32_t saveDSPBSTATUS;
 441         uint32_t saveVCLK_DIVISOR_VGA0;
 442         uint32_t saveVCLK_DIVISOR_VGA1;
 443         uint32_t saveVCLK_POST_DIV;
 444         uint32_t saveVGACNTRL;
 445         uint32_t saveADPA;
 446         uint32_t saveLVDS;
 447         uint32_t saveDVOA;
 448         uint32_t saveDVOB;
 449         uint32_t saveDVOC;
 450         uint32_t savePP_ON;
 451         uint32_t savePP_OFF;
 452         uint32_t savePP_CONTROL;
 453         uint32_t savePP_CYCLE;
 454         uint32_t savePFIT_CONTROL;
 455         uint32_t savePaletteA[256];
 456         uint32_t savePaletteB[256];
 457         uint32_t saveBLC_PWM_CTL2;
 458         uint32_t saveBLC_PWM_CTL;
 459         uint32_t saveCLOCKGATING;
 460         uint32_t saveDSPARB;
 461         uint32_t saveDSPATILEOFF;
 462         uint32_t saveDSPBTILEOFF;
 463         uint32_t saveDSPAADDR;
 464         uint32_t saveDSPBADDR;
 465         uint32_t savePFIT_AUTO_RATIOS;
 466         uint32_t savePFIT_PGM_RATIOS;
 467         uint32_t savePP_ON_DELAYS;
 468         uint32_t savePP_OFF_DELAYS;
 469         uint32_t savePP_DIVISOR;
 470         uint32_t saveBSM;
 471         uint32_t saveVBT;
 472         uint32_t saveBCLRPAT_A;
 473         uint32_t saveBCLRPAT_B;
 474         uint32_t saveDSPALINOFF;
 475         uint32_t saveDSPBLINOFF;
 476         uint32_t savePERF_MODE;
 477         uint32_t saveDSPFW1;
 478         uint32_t saveDSPFW2;
 479         uint32_t saveDSPFW3;
 480         uint32_t saveDSPFW4;
 481         uint32_t saveDSPFW5;
 482         uint32_t saveDSPFW6;
 483         uint32_t saveCHICKENBIT;
 484         uint32_t saveDSPACURSOR_CTRL;
 485         uint32_t saveDSPBCURSOR_CTRL;
 486         uint32_t saveDSPACURSOR_BASE;
 487         uint32_t saveDSPBCURSOR_BASE;
 488         uint32_t saveDSPACURSOR_POS;
 489         uint32_t saveDSPBCURSOR_POS;
 490         uint32_t save_palette_a[256];
 491         uint32_t save_palette_b[256];
 492         uint32_t saveOV_OVADD;
 493         uint32_t saveOV_OGAMC0;
 494         uint32_t saveOV_OGAMC1;
 495         uint32_t saveOV_OGAMC2;
 496         uint32_t saveOV_OGAMC3;
 497         uint32_t saveOV_OGAMC4;
 498         uint32_t saveOV_OGAMC5;
 499         uint32_t saveOVC_OVADD;
 500         uint32_t saveOVC_OGAMC0;
 501         uint32_t saveOVC_OGAMC1;
 502         uint32_t saveOVC_OGAMC2;
 503         uint32_t saveOVC_OGAMC3;
 504         uint32_t saveOVC_OGAMC4;
 505         uint32_t saveOVC_OGAMC5;
 506
 507         /* MSI reg save */
 508         uint32_t msi_addr;
 509         uint32_t msi_data;
 510
 511         /* Medfield specific register save state */
 512         uint32_t saveHDMIPHYMISCCTL;
 513         uint32_t saveHDMIB_CONTROL;
 514         uint32_t saveDSPCCNTR;
 515         uint32_t savePIPECCONF;
 516         uint32_t savePIPECSRC;
 517         uint32_t saveHTOTAL_C;
 518         uint32_t saveHBLANK_C;
 519         uint32_t saveHSYNC_C;
 520         uint32_t saveVTOTAL_C;
 521         uint32_t saveVBLANK_C;
 522         uint32_t saveVSYNC_C;
 523         uint32_t saveDSPCSTRIDE;
 524         uint32_t saveDSPCSIZE;
 525         uint32_t saveDSPCPOS;
 526         uint32_t saveDSPCSURF;
 527         uint32_t saveDSPCSTATUS;
 528         uint32_t saveDSPCLINOFF;
 529         uint32_t saveDSPCTILEOFF;
 530         uint32_t saveDSPCCURSOR_CTRL;
 531         uint32_t saveDSPCCURSOR_BASE;
 532         uint32_t saveDSPCCURSOR_POS;
 533         uint32_t save_palette_c[256];
 534         uint32_t saveOV_OVADD_C;
 535         uint32_t saveOV_OGAMC0_C;
 536         uint32_t saveOV_OGAMC1_C;
 537         uint32_t saveOV_OGAMC2_C;
 538         uint32_t saveOV_OGAMC3_C;
 539         uint32_t saveOV_OGAMC4_C;
 540         uint32_t saveOV_OGAMC5_C;
 541
 542         /* DSI register save */
 543         uint32_t saveDEVICE_READY_REG;
 544         uint32_t saveINTR_EN_REG;
 545         uint32_t saveDSI_FUNC_PRG_REG;
 546         uint32_t saveHS_TX_TIMEOUT_REG;
 547         uint32_t saveLP_RX_TIMEOUT_REG;
 548         uint32_t saveTURN_AROUND_TIMEOUT_REG;
 549         uint32_t saveDEVICE_RESET_REG;
 550         uint32_t saveDPI_RESOLUTION_REG;
 551         uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
 552         uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
 553         uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
 554         uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
 555         uint32_t saveVERT_SYNC_PAD_COUNT_REG;
 556         uint32_t saveVERT_BACK_PORCH_COUNT_REG;
 557         uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
 558         uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
 559         uint32_t saveINIT_COUNT_REG;
 560         uint32_t saveMAX_RET_PAK_REG;
 561         uint32_t saveVIDEO_FMT_REG;
 562         uint32_t saveEOT_DISABLE_REG;
 563         uint32_t saveLP_BYTECLK_REG;
 564         uint32_t saveHS_LS_DBI_ENABLE_REG;
 565         uint32_t saveTXCLKESC_REG;
 566         uint32_t saveDPHY_PARAM_REG;
 567         uint32_t saveMIPI_CONTROL_REG;
 568         uint32_t saveMIPI;
 569         uint32_t saveMIPI_C;
 570
 571         /* DPST register save */
 572         uint32_t saveHISTOGRAM_INT_CONTROL_REG;
 573         uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
 574         uint32_t savePWM_CONTROL_LOGIC;
 575
 576         /*
 577          * DSI info.
 578          */
 579         void * dbi_dsr_info;
 580         void * dbi_dpu_info;
 581         void * dsi_configs[2];
 582         /*
 583          * LID-Switch
 584          */
 585         spinlock_t lid_lock;
 586         struct timer_list lid_timer;
 587         struct psb_intel_opregion opregion;
 588         u32 *lid_state;
 589         u32 lid_last_state;
 590
 591         /*
 592          * Watchdog
 593          */
 594
 595         uint32_t apm_reg;
 596         uint16_t apm_base;
 597
 598         /*
 599          * Used for modifying backlight from
 600          * xrandr -- consider removing and using HAL instead
 601          */
 602         struct backlight_device *backlight_device;
 603         struct drm_property *backlight_property;
 604         uint32_t blc_adj1;
 605         uint32_t blc_adj2;
 606
 607         void *fbdev;
 608         /* DPST state */
 609         uint32_t dsr_idle_count;
 610         bool is_in_idle;
 611         bool dsr_enable;
 612         void (*exit_idle)(struct drm_device *dev, u32 update_src);
 613
 614         /* 2D acceleration */
 615         spinlock_t lock_2d;
 616
 617         /* FIXME: Arrays anyone ? */
 618         struct mdfld_dsi_encoder *encoder0;
 619         struct mdfld_dsi_encoder *encoder2;
 620         struct mdfld_dsi_dbi_output * dbi_output;
 621         struct mdfld_dsi_dbi_output * dbi_output2;
 622         u32 bpp;
 623         u32 bpp2;
 624
 625         bool dispstatus;
 626 };
 627
 628
 629 /*
 630  *      Operations for each board type
 631  */
 632
 633 struct psb_ops {
 634         const char *name;
 635         unsigned int accel_2d:1;
 636         int pipes;              /* Number of output pipes */
 637         int crtcs;              /* Number of CRTCs */
 638         int sgx_offset;         /* Base offset of SGX device */
 639
 640         /* Sub functions */
 641         struct drm_crtc_helper_funcs const *crtc_helper;
 642         struct drm_crtc_funcs const *crtc_funcs;
 643
 644         /* Setup hooks */
 645         int (*chip_setup)(struct drm_device *dev);
 646         void (*chip_teardown)(struct drm_device *dev);
 647
 648         /* Display management hooks */
 649         int (*output_init)(struct drm_device *dev);
 650         /* Power management hooks */
 651         void (*init_pm)(struct drm_device *dev);
 652         int (*save_regs)(struct drm_device *dev);
 653         int (*restore_regs)(struct drm_device *dev);
 654         int (*power_up)(struct drm_device *dev);
 655         int (*power_down)(struct drm_device *dev);
 656
 657         void (*lvds_bl_power)(struct drm_device *dev, bool on);
 658 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 659         /* Backlight */
 660         int (*backlight_init)(struct drm_device *dev);
 661 #endif
 662         int i2c_bus;            /* I2C bus identifier for Moorestown */
 663 };
 664
 665
 666
 667 struct psb_mmu_driver;
 668
 669 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 670 extern int drm_pick_crtcs(struct drm_device *dev);
 671
 672 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 673 {
 674         return (struct drm_psb_private *) dev->dev_private;
 675 }
 676
 677 /*
 678  * MMU stuff.
 679  */
 680
 681 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 682                                         int trap_pagefaults,
 683                                         int invalid_type,
 684                                         struct drm_psb_private *dev_priv);
 685 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 686 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 687                                                  *driver);
 688 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 689                                uint32_t gtt_start, uint32_t gtt_pages);
 690 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 691                                            int trap_pagefaults,
 692                                            int invalid_type);
 693 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 694 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 695 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 696                                         unsigned long address,
 697                                         uint32_t num_pages);
 698 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 699                                        uint32_t start_pfn,
 700                                        unsigned long address,
 701                                        uint32_t num_pages, int type);
 702 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 703                                   unsigned long *pfn);
 704
 705 /*
 706  * Enable / disable MMU for different requestors.
 707  */
 708
 709
 710 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 711 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 712                                 unsigned long address, uint32_t num_pages,
 713                                 uint32_t desired_tile_stride,
 714                                 uint32_t hw_tile_stride, int type);
 715 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 716                                  unsigned long address, uint32_t num_pages,
 717                                  uint32_t desired_tile_stride,
 718                                  uint32_t hw_tile_stride);
 719 /*
 720  *psb_irq.c
 721  */
 722
 723 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 724 extern int psb_irq_enable_dpst(struct drm_device *dev);
 725 extern int psb_irq_disable_dpst(struct drm_device *dev);
 726 extern void psb_irq_preinstall(struct drm_device *dev);
 727 extern int psb_irq_postinstall(struct drm_device *dev);
 728 extern void psb_irq_uninstall(struct drm_device *dev);
 729 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 730 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 731
 732 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 733 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
 734 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 735 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 736 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 737 void
 738 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 739
 740 void
 741 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 742
 743 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 744
 745 extern int mdfld_enable_te(struct drm_device *dev, int pipe);
 746 extern void mdfld_disable_te(struct drm_device *dev, int pipe);
 747
 748 /*
 749  * intel_opregion.c
 750  */
 751 extern int gma_intel_opregion_init(struct drm_device *dev);
 752 extern int gma_intel_opregion_exit(struct drm_device *dev);
 753
 754 /*
 755  * framebuffer.c
 756  */
 757 extern int psbfb_probed(struct drm_device *dev);
 758 extern int psbfb_remove(struct drm_device *dev,
 759                         struct drm_framebuffer *fb);
 760 /*
 761  * accel_2d.c
 762  */
 763 extern void psbfb_copyarea(struct fb_info *info,
 764                                         const struct fb_copyarea *region);
 765 extern int psbfb_sync(struct fb_info *info);
 766 extern void psb_spank(struct drm_psb_private *dev_priv);
 767 extern int psb_accel_ioctl(struct drm_device *dev, void *data,
 768                                                         struct drm_file *file);
 769
 770 /*
 771  * psb_reset.c
 772  */
 773
 774 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 775 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 776 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 777
 778 /* modesetting */
 779 extern void psb_modeset_init(struct drm_device *dev);
 780 extern void psb_modeset_cleanup(struct drm_device *dev);
 781 extern int psb_fbdev_init(struct drm_device *dev);
 782
 783 /* backlight.c */
 784 int gma_backlight_init(struct drm_device *dev);
 785 void gma_backlight_exit(struct drm_device *dev);
 786
 787 /* mrst_crtc.c */
 788 extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
 789
 790 /* mrst_lvds.c */
 791 extern void mrst_lvds_init(struct drm_device *dev,
 792                     struct psb_intel_mode_device *mode_dev);
 793
 794 /* psb_intel_display.c */
 795 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
 796 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
 797
 798 /* psb_intel_lvds.c */
 799 extern const struct drm_connector_helper_funcs
 800                                         psb_intel_lvds_connector_helper_funcs;
 801 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 802
 803 /* gem.c */
 804 extern int psb_gem_init_object(struct drm_gem_object *obj);
 805 extern void psb_gem_free_object(struct drm_gem_object *obj);
 806 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
 807                         struct drm_file *file);
 808 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 809                         struct drm_mode_create_dumb *args);
 810 extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 811                         uint32_t handle);
 812 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
 813                         uint32_t handle, uint64_t *offset);
 814 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 815 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
 816                         struct drm_file *file);
 817 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
 818                                         struct drm_file *file);
 819
 820 /* psb_device.c */
 821 extern const struct psb_ops psb_chip_ops;
 822
 823 /* mrst_device.c */
 824 extern const struct psb_ops mrst_chip_ops;
 825
 826 /* mdfld_device.c */
 827 extern const struct psb_ops mdfld_chip_ops;
 828
 829 /* cdv_device.c */
 830 extern const struct psb_ops cdv_chip_ops;
 831
 832 /*
 833  * Debug print bits setting
 834  */
 835 #define PSB_D_GENERAL (1 << 0)
 836 #define PSB_D_INIT    (1 << 1)
 837 #define PSB_D_IRQ     (1 << 2)
 838 #define PSB_D_ENTRY   (1 << 3)
 839 /* debug the get H/V BP/FP count */
 840 #define PSB_D_HV      (1 << 4)
 841 #define PSB_D_DBI_BF  (1 << 5)
 842 #define PSB_D_PM      (1 << 6)
 843 #define PSB_D_RENDER  (1 << 7)
 844 #define PSB_D_REG     (1 << 8)
 845 #define PSB_D_MSVDX   (1 << 9)
 846 #define PSB_D_TOPAZ   (1 << 10)
 847
 848 extern int drm_psb_no_fb;
 849 extern int drm_idle_check_interval;
 850
 851 /*
 852  *      Utilities
 853  */
 854
 855 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 856 {
 857         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 858         uint32_t ret_val = 0;
 859         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 860         pci_write_config_dword(pci_root, 0xD0, mcr);
 861         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 862         pci_dev_put(pci_root);
 863         return ret_val;
 864 }
 865 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 866 {
 867         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 868         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 869         pci_write_config_dword(pci_root, 0xD4, value);
 870         pci_write_config_dword(pci_root, 0xD0, mcr);
 871         pci_dev_put(pci_root);
 872 }
 873 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 874 {
 875         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 876         uint32_t ret_val = 0;
 877         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 878         pci_write_config_dword(pci_root, 0xD0, mcr);
 879         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 880         pci_dev_put(pci_root);
 881         return ret_val;
 882 }
 883 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 884 {
 885         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 886         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 887         pci_write_config_dword(pci_root, 0xD4, value);
 888         pci_write_config_dword(pci_root, 0xD0, mcr);
 889         pci_dev_put(pci_root);
 890 }
 891
 892 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
 893 {
 894         struct drm_psb_private *dev_priv = dev->dev_private;
 895         return ioread32(dev_priv->vdc_reg + reg);
 896 }
 897
 898 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
 899
 900 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
 901                                       uint32_t val)
 902 {
 903         struct drm_psb_private *dev_priv = dev->dev_private;
 904         iowrite32((val), dev_priv->vdc_reg + (reg));
 905 }
 906
 907 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
 908
 909 static inline void REGISTER_WRITE16(struct drm_device *dev,
 910                                         uint32_t reg, uint32_t val)
 911 {
 912         struct drm_psb_private *dev_priv = dev->dev_private;
 913         iowrite16((val), dev_priv->vdc_reg + (reg));
 914 }
 915
 916 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
 917
 918 static inline void REGISTER_WRITE8(struct drm_device *dev,
 919                                        uint32_t reg, uint32_t val)
 920 {
 921         struct drm_psb_private *dev_priv = dev->dev_private;
 922         iowrite8((val), dev_priv->vdc_reg + (reg));
 923 }
 924
 925 #define REG_WRITE8(reg, val)            REGISTER_WRITE8(dev, (reg), (val))
 926
 927 #define PSB_WVDC32(_val, _offs)         iowrite32(_val, dev_priv->vdc_reg + (_offs))
 928 #define PSB_RVDC32(_offs)               ioread32(dev_priv->vdc_reg + (_offs))
 929
 930 /* #define TRAP_SGX_PM_FAULT 1 */
 931 #ifdef TRAP_SGX_PM_FAULT
 932 #define PSB_RSGX32(_offs)                                               \
 933 ({                                                                      \
 934         if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {              \
 935                 printk(KERN_ERR                                         \
 936                         "access sgx when it's off!! (READ) %s, %d\n",   \
 937                __FILE__, __LINE__);                                     \
 938                 melay(1000);                                            \
 939         }                                                               \
 940         ioread32(dev_priv->sgx_reg + (_offs));                          \
 941 })
 942 #else
 943 #define PSB_RSGX32(_offs)               ioread32(dev_priv->sgx_reg + (_offs))
 944 #endif
 945 #define PSB_WSGX32(_val, _offs)         iowrite32(_val, dev_priv->sgx_reg + (_offs))
 946
 947 #define MSVDX_REG_DUMP 0
 948
 949 #define PSB_WMSVDX32(_val, _offs)       iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 950 #define PSB_RMSVDX32(_offs)             ioread32(dev_priv->msvdx_reg + (_offs))
 951
 952 #endif