drivers/staging/octeon/cvmx-asxx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2008 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_ASXX_DEFS_H__
  29 #define __CVMX_ASXX_DEFS_H__
  30
  31 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \
  32          CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull))
  33 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \
  34          CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull))
  35 #define CVMX_ASXX_INT_EN(block_id) \
  36          CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull))
  37 #define CVMX_ASXX_INT_REG(block_id) \
  38          CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull))
  39 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) \
  40          CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull))
  41 #define CVMX_ASXX_PRT_LOOP(block_id) \
  42          CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull))
  43 #define CVMX_ASXX_RLD_BYPASS(block_id) \
  44          CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull))
  45 #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \
  46          CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull))
  47 #define CVMX_ASXX_RLD_COMP(block_id) \
  48          CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull))
  49 #define CVMX_ASXX_RLD_DATA_DRV(block_id) \
  50          CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull))
  51 #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \
  52          CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull))
  53 #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \
  54          CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull))
  55 #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \
  56          CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull))
  57 #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \
  58          CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull))
  59 #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \
  60          CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull))
  61 #define CVMX_ASXX_RLD_SETTING(block_id) \
  62          CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull))
  63 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
  64          CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
  65 #define CVMX_ASXX_RX_PRT_EN(block_id) \
  66          CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull))
  67 #define CVMX_ASXX_RX_WOL(block_id) \
  68          CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull))
  69 #define CVMX_ASXX_RX_WOL_MSK(block_id) \
  70          CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull))
  71 #define CVMX_ASXX_RX_WOL_POWOK(block_id) \
  72          CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull))
  73 #define CVMX_ASXX_RX_WOL_SIG(block_id) \
  74          CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull))
  75 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
  76          CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
  77 #define CVMX_ASXX_TX_COMP_BYP(block_id) \
  78          CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull))
  79 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
  80          CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
  81 #define CVMX_ASXX_TX_PRT_EN(block_id) \
  82          CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull))
  83
  84 union cvmx_asxx_gmii_rx_clk_set {
  85         uint64_t u64;
  86         struct cvmx_asxx_gmii_rx_clk_set_s {
  87                 uint64_t reserved_5_63:59;
  88                 uint64_t setting:5;
  89         } s;
  90         struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
  91         struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
  92         struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
  93 };
  94
  95 union cvmx_asxx_gmii_rx_dat_set {
  96         uint64_t u64;
  97         struct cvmx_asxx_gmii_rx_dat_set_s {
  98                 uint64_t reserved_5_63:59;
  99                 uint64_t setting:5;
 100         } s;
 101         struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
 102         struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
 103         struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
 104 };
 105
 106 union cvmx_asxx_int_en {
 107         uint64_t u64;
 108         struct cvmx_asxx_int_en_s {
 109                 uint64_t reserved_12_63:52;
 110                 uint64_t txpsh:4;
 111                 uint64_t txpop:4;
 112                 uint64_t ovrflw:4;
 113         } s;
 114         struct cvmx_asxx_int_en_cn30xx {
 115                 uint64_t reserved_11_63:53;
 116                 uint64_t txpsh:3;
 117                 uint64_t reserved_7_7:1;
 118                 uint64_t txpop:3;
 119                 uint64_t reserved_3_3:1;
 120                 uint64_t ovrflw:3;
 121         } cn30xx;
 122         struct cvmx_asxx_int_en_cn30xx cn31xx;
 123         struct cvmx_asxx_int_en_s cn38xx;
 124         struct cvmx_asxx_int_en_s cn38xxp2;
 125         struct cvmx_asxx_int_en_cn30xx cn50xx;
 126         struct cvmx_asxx_int_en_s cn58xx;
 127         struct cvmx_asxx_int_en_s cn58xxp1;
 128 };
 129
 130 union cvmx_asxx_int_reg {
 131         uint64_t u64;
 132         struct cvmx_asxx_int_reg_s {
 133                 uint64_t reserved_12_63:52;
 134                 uint64_t txpsh:4;
 135                 uint64_t txpop:4;
 136                 uint64_t ovrflw:4;
 137         } s;
 138         struct cvmx_asxx_int_reg_cn30xx {
 139                 uint64_t reserved_11_63:53;
 140                 uint64_t txpsh:3;
 141                 uint64_t reserved_7_7:1;
 142                 uint64_t txpop:3;
 143                 uint64_t reserved_3_3:1;
 144                 uint64_t ovrflw:3;
 145         } cn30xx;
 146         struct cvmx_asxx_int_reg_cn30xx cn31xx;
 147         struct cvmx_asxx_int_reg_s cn38xx;
 148         struct cvmx_asxx_int_reg_s cn38xxp2;
 149         struct cvmx_asxx_int_reg_cn30xx cn50xx;
 150         struct cvmx_asxx_int_reg_s cn58xx;
 151         struct cvmx_asxx_int_reg_s cn58xxp1;
 152 };
 153
 154 union cvmx_asxx_mii_rx_dat_set {
 155         uint64_t u64;
 156         struct cvmx_asxx_mii_rx_dat_set_s {
 157                 uint64_t reserved_5_63:59;
 158                 uint64_t setting:5;
 159         } s;
 160         struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
 161         struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
 162 };
 163
 164 union cvmx_asxx_prt_loop {
 165         uint64_t u64;
 166         struct cvmx_asxx_prt_loop_s {
 167                 uint64_t reserved_8_63:56;
 168                 uint64_t ext_loop:4;
 169                 uint64_t int_loop:4;
 170         } s;
 171         struct cvmx_asxx_prt_loop_cn30xx {
 172                 uint64_t reserved_7_63:57;
 173                 uint64_t ext_loop:3;
 174                 uint64_t reserved_3_3:1;
 175                 uint64_t int_loop:3;
 176         } cn30xx;
 177         struct cvmx_asxx_prt_loop_cn30xx cn31xx;
 178         struct cvmx_asxx_prt_loop_s cn38xx;
 179         struct cvmx_asxx_prt_loop_s cn38xxp2;
 180         struct cvmx_asxx_prt_loop_cn30xx cn50xx;
 181         struct cvmx_asxx_prt_loop_s cn58xx;
 182         struct cvmx_asxx_prt_loop_s cn58xxp1;
 183 };
 184
 185 union cvmx_asxx_rld_bypass {
 186         uint64_t u64;
 187         struct cvmx_asxx_rld_bypass_s {
 188                 uint64_t reserved_1_63:63;
 189                 uint64_t bypass:1;
 190         } s;
 191         struct cvmx_asxx_rld_bypass_s cn38xx;
 192         struct cvmx_asxx_rld_bypass_s cn38xxp2;
 193         struct cvmx_asxx_rld_bypass_s cn58xx;
 194         struct cvmx_asxx_rld_bypass_s cn58xxp1;
 195 };
 196
 197 union cvmx_asxx_rld_bypass_setting {
 198         uint64_t u64;
 199         struct cvmx_asxx_rld_bypass_setting_s {
 200                 uint64_t reserved_5_63:59;
 201                 uint64_t setting:5;
 202         } s;
 203         struct cvmx_asxx_rld_bypass_setting_s cn38xx;
 204         struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
 205         struct cvmx_asxx_rld_bypass_setting_s cn58xx;
 206         struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
 207 };
 208
 209 union cvmx_asxx_rld_comp {
 210         uint64_t u64;
 211         struct cvmx_asxx_rld_comp_s {
 212                 uint64_t reserved_9_63:55;
 213                 uint64_t pctl:5;
 214                 uint64_t nctl:4;
 215         } s;
 216         struct cvmx_asxx_rld_comp_cn38xx {
 217                 uint64_t reserved_8_63:56;
 218                 uint64_t pctl:4;
 219                 uint64_t nctl:4;
 220         } cn38xx;
 221         struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
 222         struct cvmx_asxx_rld_comp_s cn58xx;
 223         struct cvmx_asxx_rld_comp_s cn58xxp1;
 224 };
 225
 226 union cvmx_asxx_rld_data_drv {
 227         uint64_t u64;
 228         struct cvmx_asxx_rld_data_drv_s {
 229                 uint64_t reserved_8_63:56;
 230                 uint64_t pctl:4;
 231                 uint64_t nctl:4;
 232         } s;
 233         struct cvmx_asxx_rld_data_drv_s cn38xx;
 234         struct cvmx_asxx_rld_data_drv_s cn38xxp2;
 235         struct cvmx_asxx_rld_data_drv_s cn58xx;
 236         struct cvmx_asxx_rld_data_drv_s cn58xxp1;
 237 };
 238
 239 union cvmx_asxx_rld_fcram_mode {
 240         uint64_t u64;
 241         struct cvmx_asxx_rld_fcram_mode_s {
 242                 uint64_t reserved_1_63:63;
 243                 uint64_t mode:1;
 244         } s;
 245         struct cvmx_asxx_rld_fcram_mode_s cn38xx;
 246         struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
 247 };
 248
 249 union cvmx_asxx_rld_nctl_strong {
 250         uint64_t u64;
 251         struct cvmx_asxx_rld_nctl_strong_s {
 252                 uint64_t reserved_5_63:59;
 253                 uint64_t nctl:5;
 254         } s;
 255         struct cvmx_asxx_rld_nctl_strong_s cn38xx;
 256         struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
 257         struct cvmx_asxx_rld_nctl_strong_s cn58xx;
 258         struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
 259 };
 260
 261 union cvmx_asxx_rld_nctl_weak {
 262         uint64_t u64;
 263         struct cvmx_asxx_rld_nctl_weak_s {
 264                 uint64_t reserved_5_63:59;
 265                 uint64_t nctl:5;
 266         } s;
 267         struct cvmx_asxx_rld_nctl_weak_s cn38xx;
 268         struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
 269         struct cvmx_asxx_rld_nctl_weak_s cn58xx;
 270         struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
 271 };
 272
 273 union cvmx_asxx_rld_pctl_strong {
 274         uint64_t u64;
 275         struct cvmx_asxx_rld_pctl_strong_s {
 276                 uint64_t reserved_5_63:59;
 277                 uint64_t pctl:5;
 278         } s;
 279         struct cvmx_asxx_rld_pctl_strong_s cn38xx;
 280         struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
 281         struct cvmx_asxx_rld_pctl_strong_s cn58xx;
 282         struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
 283 };
 284
 285 union cvmx_asxx_rld_pctl_weak {
 286         uint64_t u64;
 287         struct cvmx_asxx_rld_pctl_weak_s {
 288                 uint64_t reserved_5_63:59;
 289                 uint64_t pctl:5;
 290         } s;
 291         struct cvmx_asxx_rld_pctl_weak_s cn38xx;
 292         struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
 293         struct cvmx_asxx_rld_pctl_weak_s cn58xx;
 294         struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
 295 };
 296
 297 union cvmx_asxx_rld_setting {
 298         uint64_t u64;
 299         struct cvmx_asxx_rld_setting_s {
 300                 uint64_t reserved_13_63:51;
 301                 uint64_t dfaset:5;
 302                 uint64_t dfalag:1;
 303                 uint64_t dfalead:1;
 304                 uint64_t dfalock:1;
 305                 uint64_t setting:5;
 306         } s;
 307         struct cvmx_asxx_rld_setting_cn38xx {
 308                 uint64_t reserved_5_63:59;
 309                 uint64_t setting:5;
 310         } cn38xx;
 311         struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
 312         struct cvmx_asxx_rld_setting_s cn58xx;
 313         struct cvmx_asxx_rld_setting_s cn58xxp1;
 314 };
 315
 316 union cvmx_asxx_rx_clk_setx {
 317         uint64_t u64;
 318         struct cvmx_asxx_rx_clk_setx_s {
 319                 uint64_t reserved_5_63:59;
 320                 uint64_t setting:5;
 321         } s;
 322         struct cvmx_asxx_rx_clk_setx_s cn30xx;
 323         struct cvmx_asxx_rx_clk_setx_s cn31xx;
 324         struct cvmx_asxx_rx_clk_setx_s cn38xx;
 325         struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
 326         struct cvmx_asxx_rx_clk_setx_s cn50xx;
 327         struct cvmx_asxx_rx_clk_setx_s cn58xx;
 328         struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
 329 };
 330
 331 union cvmx_asxx_rx_prt_en {
 332         uint64_t u64;
 333         struct cvmx_asxx_rx_prt_en_s {
 334                 uint64_t reserved_4_63:60;
 335                 uint64_t prt_en:4;
 336         } s;
 337         struct cvmx_asxx_rx_prt_en_cn30xx {
 338                 uint64_t reserved_3_63:61;
 339                 uint64_t prt_en:3;
 340         } cn30xx;
 341         struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
 342         struct cvmx_asxx_rx_prt_en_s cn38xx;
 343         struct cvmx_asxx_rx_prt_en_s cn38xxp2;
 344         struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
 345         struct cvmx_asxx_rx_prt_en_s cn58xx;
 346         struct cvmx_asxx_rx_prt_en_s cn58xxp1;
 347 };
 348
 349 union cvmx_asxx_rx_wol {
 350         uint64_t u64;
 351         struct cvmx_asxx_rx_wol_s {
 352                 uint64_t reserved_2_63:62;
 353                 uint64_t status:1;
 354                 uint64_t enable:1;
 355         } s;
 356         struct cvmx_asxx_rx_wol_s cn38xx;
 357         struct cvmx_asxx_rx_wol_s cn38xxp2;
 358 };
 359
 360 union cvmx_asxx_rx_wol_msk {
 361         uint64_t u64;
 362         struct cvmx_asxx_rx_wol_msk_s {
 363                 uint64_t msk:64;
 364         } s;
 365         struct cvmx_asxx_rx_wol_msk_s cn38xx;
 366         struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
 367 };
 368
 369 union cvmx_asxx_rx_wol_powok {
 370         uint64_t u64;
 371         struct cvmx_asxx_rx_wol_powok_s {
 372                 uint64_t reserved_1_63:63;
 373                 uint64_t powerok:1;
 374         } s;
 375         struct cvmx_asxx_rx_wol_powok_s cn38xx;
 376         struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
 377 };
 378
 379 union cvmx_asxx_rx_wol_sig {
 380         uint64_t u64;
 381         struct cvmx_asxx_rx_wol_sig_s {
 382                 uint64_t reserved_32_63:32;
 383                 uint64_t sig:32;
 384         } s;
 385         struct cvmx_asxx_rx_wol_sig_s cn38xx;
 386         struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
 387 };
 388
 389 union cvmx_asxx_tx_clk_setx {
 390         uint64_t u64;
 391         struct cvmx_asxx_tx_clk_setx_s {
 392                 uint64_t reserved_5_63:59;
 393                 uint64_t setting:5;
 394         } s;
 395         struct cvmx_asxx_tx_clk_setx_s cn30xx;
 396         struct cvmx_asxx_tx_clk_setx_s cn31xx;
 397         struct cvmx_asxx_tx_clk_setx_s cn38xx;
 398         struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
 399         struct cvmx_asxx_tx_clk_setx_s cn50xx;
 400         struct cvmx_asxx_tx_clk_setx_s cn58xx;
 401         struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
 402 };
 403
 404 union cvmx_asxx_tx_comp_byp {
 405         uint64_t u64;
 406         struct cvmx_asxx_tx_comp_byp_s {
 407                 uint64_t reserved_0_63:64;
 408         } s;
 409         struct cvmx_asxx_tx_comp_byp_cn30xx {
 410                 uint64_t reserved_9_63:55;
 411                 uint64_t bypass:1;
 412                 uint64_t pctl:4;
 413                 uint64_t nctl:4;
 414         } cn30xx;
 415         struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
 416         struct cvmx_asxx_tx_comp_byp_cn38xx {
 417                 uint64_t reserved_8_63:56;
 418                 uint64_t pctl:4;
 419                 uint64_t nctl:4;
 420         } cn38xx;
 421         struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
 422         struct cvmx_asxx_tx_comp_byp_cn50xx {
 423                 uint64_t reserved_17_63:47;
 424                 uint64_t bypass:1;
 425                 uint64_t reserved_13_15:3;
 426                 uint64_t pctl:5;
 427                 uint64_t reserved_5_7:3;
 428                 uint64_t nctl:5;
 429         } cn50xx;
 430         struct cvmx_asxx_tx_comp_byp_cn58xx {
 431                 uint64_t reserved_13_63:51;
 432                 uint64_t pctl:5;
 433                 uint64_t reserved_5_7:3;
 434                 uint64_t nctl:5;
 435         } cn58xx;
 436         struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
 437 };
 438
 439 union cvmx_asxx_tx_hi_waterx {
 440         uint64_t u64;
 441         struct cvmx_asxx_tx_hi_waterx_s {
 442                 uint64_t reserved_4_63:60;
 443                 uint64_t mark:4;
 444         } s;
 445         struct cvmx_asxx_tx_hi_waterx_cn30xx {
 446                 uint64_t reserved_3_63:61;
 447                 uint64_t mark:3;
 448         } cn30xx;
 449         struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
 450         struct cvmx_asxx_tx_hi_waterx_s cn38xx;
 451         struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
 452         struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
 453         struct cvmx_asxx_tx_hi_waterx_s cn58xx;
 454         struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
 455 };
 456
 457 union cvmx_asxx_tx_prt_en {
 458         uint64_t u64;
 459         struct cvmx_asxx_tx_prt_en_s {
 460                 uint64_t reserved_4_63:60;
 461                 uint64_t prt_en:4;
 462         } s;
 463         struct cvmx_asxx_tx_prt_en_cn30xx {
 464                 uint64_t reserved_3_63:61;
 465                 uint64_t prt_en:3;
 466         } cn30xx;
 467         struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
 468         struct cvmx_asxx_tx_prt_en_s cn38xx;
 469         struct cvmx_asxx_tx_prt_en_s cn38xxp2;
 470         struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
 471         struct cvmx_asxx_tx_prt_en_s cn58xx;
 472         struct cvmx_asxx_tx_prt_en_s cn58xxp1;
 473 };
 474
 475 #endif