| blob | 4730016d7cd42d8644e8fb5fa8791fc9df080591 |
1 /*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
13 /*
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
17 *
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
20 * by BIOS init).
21 *
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24 * can be used with gadget ether.
25 */
27 /* debug control */
28 /* #define UDC_VERBOSE */
30 /* Driver strings */
34 /* system */
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/ioport.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/errno.h>
43 #include <linux/init.h>
44 #include <linux/timer.h>
45 #include <linux/list.h>
46 #include <linux/interrupt.h>
47 #include <linux/ioctl.h>
48 #include <linux/fs.h>
49 #include <linux/dmapool.h>
50 #include <linux/moduleparam.h>
51 #include <linux/device.h>
52 #include <linux/io.h>
53 #include <linux/irq.h>
54 #include <linux/prefetch.h>
56 #include <asm/byteorder.h>
57 #include <asm/system.h>
58 #include <asm/unaligned.h>
60 /* gadget stack */
61 #include <linux/usb/ch9.h>
62 #include <linux/usb/gadget.h>
64 /* udc specific */
83 /* description */
87 /* structure to hold endpoint function pointers */
90 /* received setup data */
93 /* pointer to device object */
96 /* irq spin lock for soft reset */
98 /* stall spin lock */
101 /*
102 * slave mode: pending bytes in rx fifo after nyet,
103 * used if EPIN irq came but no req was available
104 */
107 /* count soft resets after suspend to avoid loop */
111 /* timer */
115 /* set_rde -- Is used to control enabling of RX DMA. Problem is
116 * that UDC has only one bit (RDE) to enable/disable RX DMA for
117 * all OUT endpoints. So we have to handle race conditions like
118 * when OUT data reaches the fifo but no request was queued yet.
119 * This cannot be solved by letting the RX DMA disabled until a
120 * request gets queued because there may be other OUT packets
121 * in the FIFO (important for not blocking control traffic).
122 * The value of set_rde controls the correspondig timer.
123 *
124 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
125 * set_rde 0 == do not touch RDE, do no start the RDE timer
126 * set_rde 1 == timer function will look whether FIFO has data
127 * set_rde 2 == set by timer function to enable RX DMA on next call
128 */
136 /* tasklet for usb disconnect */
141 /* endpoint names used for print */
144 ep0_string,
152 };
154 /* DMA usage flag */
156 /* packet per buffer dma */
158 /* with per descr. update */
160 /* buffer fill mode */
162 /* full speed only mode */
164 /* tx buffer size for high speed */
167 /* module parameters */
178 /*---------------------------------------------------------------------------*/
179 /* Prints UDC device registers and endpoint irq registers */
181 {
202 }
206 }
209 }
211 }
213 /* Masks unused interrupts */
215 {
216 u32 tmp;
218 /* mask all dev interrupts */
229 /* mask all ep interrupts */
233 }
235 /* Enables endpoint 0 interrupts */
237 {
238 u32 tmp;
242 /* read irq mask */
244 /* enable ep0 irq's */
250 }
252 /* Enables device interrupts for SET_INTF and SET_CONFIG */
254 {
255 u32 tmp;
259 /* read irq mask */
262 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
271 }
273 /* Calculates fifo start of endpoint based on preceding endpoints */
275 {
277 u32 tmp;
286 /* traverse ep's */
289 /* read fifo size */
293 }
294 }
296 }
298 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
302 {
309 }
312 /* Enables endpoint, is called by gadget driver */
313 static int
315 {
318 u32 tmp;
320 u8 udc_csr_epix;
325 || !desc
342 /* set traffic type */
347 /* set max packet size */
354 /* IN ep */
357 /* ep ix in UDC CSR register space */
360 /* set buffer size (tx fifo entries) */
362 /* double buffering: fifo size = 2 x max packet size */
364 tmp,
365 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
367 UDC_EPIN_BUFF_SIZE);
370 /* calc. tx fifo base addr */
373 /* flush fifo */
378 /* OUT ep */
380 /* ep ix in UDC CSR register space */
383 /* set max packet size UDC CSR */
386 UDC_CSR_NE_MAX_PKT);
390 /* alloc and init BNA dummy request */
393 }
397 }
399 /* set ep values */
401 /* max packet */
403 /* ep number */
405 /* ep direction */
407 /* ep type */
409 /* ep config */
411 /* ep interface */
413 /* ep alt */
415 /* write reg */
418 /* enable ep irq */
423 /*
424 * clear NAK by writing CNAK
425 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
426 */
433 }
439 }
441 /* Resets endpoint */
443 {
444 u32 tmp;
452 /* set NAK */
458 /* disable interrupt */
464 /* unset P and IN bit of potential former DMA */
473 /* flush the fifo */
478 }
479 /* reset desc pointer */
481 }
483 /* Disables endpoint, is called by gadget driver */
485 {
505 }
507 /* Allocates request packet, called by gadget driver */
510 {
529 /* ep0 in requests are allocated from data pool here */
535 }
541 /* prevent from using desc. - set HOST BUSY */
543 UDC_DMA_STP_STS_BS_HOST_BUSY,
544 UDC_DMA_STP_STS_BS);
549 }
552 }
554 /* Frees request packet, called by gadget driver */
555 static void
557 {
571 /* free dma chain if created */
574 }
578 }
580 }
582 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
584 {
586 /* set last bit */
588 /* set next pointer to itself */
590 /* set HOST BUSY */
593 UDC_DMA_STP_STS_BS_DMA_DONE,
594 UDC_DMA_STP_STS_BS);
595 #ifdef UDC_VERBOSE
598 #endif
599 }
600 }
602 /* Allocate BNA dummy descriptor */
604 {
608 /* alloc the dummy request */
614 }
616 }
618 /* Write data to TX fifo for IN packets */
619 static void
621 {
641 /* dwords first */
644 }
646 /* remaining bytes must be written by byte access */
650 }
652 /* dummy write confirm */
654 }
656 /* Read dwords from RX fifo for OUT transfers */
658 {
665 }
667 }
669 /* Read bytes from RX fifo for OUT transfers */
671 {
673 u32 tmp;
677 /* dwords first */
680 }
682 /* remaining bytes must be read by byte access */
688 }
689 }
692 }
694 /* Read data from RX fifo for OUT transfers */
695 static int
697 {
703 /* received number bytes */
715 }
717 }
720 /* last packet ? */
725 /* read rx fifo bytes */
730 }
732 /* create/re-init a DMA descriptor or a DMA descriptor chain */
734 {
736 u32 tmp;
742 /* set buffer pointer */
745 /* set last bit */
748 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
756 }
759 /* write tx bytes */
763 UDC_DMA_IN_STS_TXBYTES);
765 }
766 }
768 }
775 /*
776 * if bytes < max packet then tx bytes must
777 * be written in packet per buffer mode
778 */
782 /* write tx bytes */
786 UDC_DMA_IN_STS_TXBYTES);
787 /* reset frame num */
791 UDC_DMA_IN_STS_FRAMENUM);
792 }
793 /* set HOST BUSY */
796 UDC_DMA_STP_STS_BS_HOST_BUSY,
797 UDC_DMA_STP_STS_BS);
800 /* set HOST READY */
803 UDC_DMA_STP_STS_BS_HOST_READY,
804 UDC_DMA_STP_STS_BS);
807 /* clear NAK by writing CNAK */
814 }
816 }
819 }
821 /* Completes request packet ... caller MUST hold lock */
822 static void
826 {
833 /* unmap DMA */
839 PCI_DMA_TODEVICE);
840 else
844 PCI_DMA_FROMDEVICE);
847 }
852 /* set new status if pending */
856 /* remove from ep queue */
866 }
868 /* frees pci pool descriptors of a DMA chain */
870 {
879 /* do not free first desc., will be done by free for request */
889 }
892 }
894 /* Iterates to the end of a DMA chain and returns last descriptor */
896 {
902 }
906 }
908 /* Iterates to the end of a DMA chain and counts bytes received */
910 {
912 u32 count;
915 /* received number bytes */
920 /* received number bytes */
923 UDC_DMA_OUT_STS_RXBYTES);
924 }
925 }
929 }
931 /* Creates or re-inits a DMA chain */
936 )
937 {
940 dma_addr_t dma_addr;
951 /* unset L bit in first desc for OUT */
954 }
956 /* alloc only new desc's if not already available */
959 len++;
960 }
963 /* shorter chain already allocated before */
966 }
969 }
972 /* gen. required number of descriptors and buffers */
974 /* create or determine next desc. */
984 /* first td */
991 }
996 else
999 /* short packet ? */
1003 /* short packet */
1005 }
1007 /* link td and assign tx bytes */
1012 /* req->td_data->next = virt_to_phys(td); */
1013 }
1014 /* write tx bytes */
1016 /* first desc */
1020 UDC_DMA_IN_STS_TXBYTES);
1021 /* second desc */
1023 txbytes,
1024 UDC_DMA_IN_STS_TXBYTES);
1025 }
1030 /* last->next = virt_to_phys(td); */
1031 }
1033 /* write tx bytes */
1035 txbytes,
1036 UDC_DMA_IN_STS_TXBYTES);
1037 }
1038 }
1040 }
1041 /* set last bit */
1044 /* last desc. points to itself */
1046 }
1049 }
1051 /* Enabling RX DMA */
1053 {
1054 u32 tmp;
1057 /* stop RDE timer */
1061 }
1062 /* set RDE */
1066 }
1068 /* Queues a request packet, called by gadget driver */
1069 static int
1071 {
1078 u32 tmp;
1080 /* check the inputs */
1097 /* map dma (usually done before) */
1105 PCI_DMA_TODEVICE);
1106 else
1110 PCI_DMA_FROMDEVICE);
1112 }
1123 /* on empty queue just do first transfer */
1125 /* zlp */
1127 /* IN zlp's are handled by hardware */
1130 /*
1131 * if set_config or set_intf is waiting for ack by zlp
1132 * then set CSR_DONE
1133 */
1139 }
1140 /* setup command is ACK'ed now by zlp */
1142 /* clear NAK by writing CNAK in EP0_IN */
1148 UDC_EP0IN_IX);
1150 }
1152 }
1157 /* write desc pointer to enable DMA */
1159 /* set HOST READY */
1162 UDC_DMA_IN_STS_BS_HOST_READY,
1163 UDC_DMA_IN_STS_BS);
1164 }
1166 /* disabled rx dma while descriptor update */
1168 /* stop RDE timer */
1172 }
1173 /* clear RDE */
1179 /*
1180 * if BNA occurred then let BNA dummy desc.
1181 * point to current desc.
1182 */
1188 }
1189 }
1190 /* write desc pointer */
1193 /* clear NAK by writing CNAK */
1200 }
1203 /* enable ep irq */
1207 }
1209 /* enable ep irq */
1213 }
1217 /*
1218 * prep_dma not used for OUT ep's, this is not possible
1219 * for PPB modes, because of chain creation reasons
1220 */
1225 }
1226 }
1228 /* add request to ep queue */
1233 /* open rxfifo if out data queued */
1235 /* enable DMA */
1240 }
1241 /* stop OUT naking */
1246 /*
1247 * read pending bytes afer nyet:
1248 * referring to isr
1249 */
1251 /* finish */
1253 }
1256 }
1257 }
1258 }
1260 finished:
1263 }
1265 /* Empty request queue of an endpoint; caller holds spinlock */
1267 {
1274 queue);
1276 }
1277 }
1279 /* Dequeues a request packet, called by gadget driver */
1281 {
1297 /* request in processing or next one */
1303 u32 tmp;
1304 u32 dma_sts;
1305 /* stop potential receive DMA */
1309 /*
1310 * Cancel transfer later in ISR
1311 * if descriptor was touched.
1312 */
1314 UDC_DMA_OUT_STS_BS);
1321 }
1323 }
1324 }
1325 }
1331 }
1333 /* Halt or clear halt of endpoint */
1334 static int
1336 {
1338 u32 tmp;
1354 /* halt or clear halt */
1359 /*
1360 * set STALL
1361 * rxfifo empty not taken into acount
1362 */
1368 /* setup poll timer */
1371 HZ * UDC_POLLSTALL_TIMER_USECONDS
1376 }
1377 }
1378 }
1380 /* ep is halted by set_halt() before */
1383 /* clear stall bit */
1385 /* clear NAK by writing CNAK */
1390 }
1391 }
1394 }
1396 /* gadget interface */
1408 /* fifo ops not implemented */
1409 };
1411 /*-------------------------------------------------------------------------*/
1413 /* Get frame counter (not implemented) */
1415 {
1417 }
1419 /* Remote wakeup gadget interface */
1421 {
1430 }
1435 /* gadget operations */
1441 };
1443 /* Setups endpoint parameters, adds endpoints to linked list */
1445 {
1446 /* make gadget ep lists */
1455 /* fifo config */
1462 }
1464 /* init registers at driver load time */
1466 {
1467 u32 tmp;
1469 /* init controller by soft reset */
1472 /* mask not needed interrupts */
1475 /* put into initial config */
1477 /* link up all endpoints */
1480 /* program speed */
1486 }
1490 }
1492 /* Inits UDC context */
1494 {
1495 u32 tmp;
1501 /* stop RDE timer */
1505 }
1506 /* stop poll stall timer */
1509 }
1510 /* disable DMA */
1516 /* enable dynamic CSR programming */
1519 /* set self powered */
1521 /* set remote wakeupable */
1529 }
1531 /* Sets initial endpoint parameters */
1533 {
1535 u32 tmp;
1536 u32 reg;
1540 /* read enum speed */
1547 }
1549 /* set basic ep parameters */
1555 /* txfifo size is calculated at enable time */
1558 /* fifo size */
1566 }
1568 /*
1569 * ep will be reset only if ep was not enabled before to avoid
1570 * disabling ep interrupts when ENUM interrupt occurs but ep is
1571 * not enabled by gadget driver
1572 */
1575 }
1578 /*
1579 * ep->dma is not really used, just to indicate that
1580 * DMA is active: remove this
1581 * dma regs = dev control regs
1582 */
1585 /* nak OUT endpoints until enable - not for ep0 */
1588 /* set NAK */
1594 }
1595 }
1596 }
1597 /* EP0 max packet */
1601 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1605 }
1607 /*
1608 * with suspend bug workaround, ep0 params for gadget driver
1609 * are set at gadget driver bind() call
1610 */
1615 /* init cfg/alt/int */
1619 }
1621 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1623 {
1629 /* put into initial config */
1632 /* enable device setup interrupts */
1634 }
1636 /*
1637 * Calls gadget with disconnect event and resets the UDC and makes
1638 * initial bringup to be ready for ep0 events
1639 */
1641 {
1647 /* mask interrupts */
1650 /* REVISIT there doesn't seem to be a point to having this
1651 * talk to a tasklet ... do it directly, we already hold
1652 * the spinlock needed to process the disconnect.
1653 */
1656 }
1658 /* Tasklet for disconnect to be outside of interrupt context */
1660 {
1662 u32 tmp;
1672 /* empty queues */
1675 }
1677 }
1679 /* disable ep0 */
1685 /* init controller by soft reset */
1687 soft_reset_occured++;
1688 }
1690 /* re-enable dev interrupts */
1692 /* back to full speed ? */
1697 }
1700 }
1702 /* Reset the UDC core */
1704 {
1708 /*
1709 * reset possible waiting interrupts, because int.
1710 * status is lost after soft reset,
1711 * ep int. status reset
1712 */
1714 /* device int. status reset */
1722 }
1724 /* RDE timer callback to set RDE bit */
1726 {
1727 u32 tmp;
1732 /*
1733 * open the fifo if fifo was filled on last timer call
1734 * conditionally
1735 */
1737 /* set RDE to receive setup data */
1744 /*
1745 * if fifo empty setup polling, do not just
1746 * open the fifo
1747 */
1751 }
1753 /*
1754 * fifo contains data now, setup timer for opening
1755 * the fifo when timer expires to be able to receive
1756 * setup packets, when data packets gets queued by
1757 * gadget layer then timer will forced to expire with
1758 * set_rde=0 (RDE is set in udc_queue())
1759 */
1760 set_rde++;
1761 /* debug: lhadmot_timer_start = 221070 */
1765 }
1766 }
1774 }
1776 /* Handle halt state, used in stall poll timer */
1778 {
1779 u32 tmp;
1780 /* set stall as long not halted */
1783 /* STALL cleared ? */
1785 /*
1786 * FIXME: MSC spec requires that stall remains
1787 * even on receivng of CLEAR_FEATURE HALT. So
1788 * we would set STALL again here to be compliant.
1789 * But with current mass storage drivers this does
1790 * not work (would produce endless host retries).
1791 * So we clear halt on CLEAR_FEATURE.
1792 *
1793 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1794 tmp |= AMD_BIT(UDC_EPCTL_S);
1795 writel(tmp, &ep->regs->ctl);*/
1797 /* clear NAK by writing CNAK */
1802 }
1803 }
1804 }
1806 /* Stall timer callback to poll S bit and set it again after */
1808 {
1813 /*
1814 * only one IN and OUT endpoints are handled
1815 * IN poll stall
1816 */
1821 /* OUT poll stall */
1827 /* setup timer again when still halted */
1830 HZ * UDC_POLLSTALL_TIMER_USECONDS
1833 }
1838 }
1840 /* Inits endpoint 0 so that SETUP packets are processed */
1842 {
1843 u32 tmp;
1847 /* flush fifo */
1852 /* set ep0 directions */
1856 /* set buffer size (tx fifo entries) of EP0_IN */
1860 UDC_EPIN_BUFF_SIZE);
1863 UDC_EPIN_BUFF_SIZE);
1866 /* set max packet size of EP0_IN */
1870 UDC_EP_MAX_PKT_SIZE);
1873 UDC_EP_MAX_PKT_SIZE);
1876 /* set max packet size of EP0_OUT */
1880 UDC_EP_MAX_PKT_SIZE);
1883 UDC_EP_MAX_PKT_SIZE);
1886 /* set max packet size of EP0 in UDC CSR */
1890 UDC_CSR_NE_MAX_PKT);
1893 UDC_CSR_NE_MAX_PKT);
1899 /* write dma desc address */
1904 /* stop RDE timer */
1908 }
1909 /* stop pollstall timer */
1912 }
1913 /* enable DMA */
1922 }
1924 }
1926 /* clear NAK by writing CNAK for EP0IN */
1933 /* clear NAK by writing CNAK for EP0OUT */
1939 }
1941 /* Make endpoint 0 ready for control traffic */
1943 {
1945 /* enable ep0 interrupts */
1947 /* enable device setup interrupts */
1951 }
1953 /* Called by gadget driver to register itself */
1956 {
1959 u32 tmp;
1975 /* Some gadget drivers use both ep0 directions.
1976 * NOTE: to gadget driver, ep0 is just one endpoint...
1977 */
1987 }
1989 /* get ready for ep0 traffic */
1992 /* clear SD */
2000 }
2002 /* shutdown requests and disconnect from gadget */
2003 static void
2007 {
2014 }
2016 /* empty queues and init hardware */
2022 }
2024 /* Called by gadget driver to unregister itself */
2026 {
2029 u32 tmp;
2045 /* set SD */
2054 }
2056 /* Clear pending NAK bits */
2058 {
2059 u32 tmp;
2060 u32 reg;
2062 /* check epin's */
2067 /* clear NAK by writing CNAK */
2073 }
2074 }
2075 /* ... and ep0out */
2078 /* clear NAK by writing CNAK */
2085 }
2086 }
2088 /* Enabling RX DMA after setup packet */
2090 {
2092 /*
2093 * only enable RXDMA when no data endpoint enabled
2094 * or data is queued
2095 */
2099 /*
2100 * setup timer for enabling RDE (to not enable
2101 * RXFIFO DMA for data endpoints to early)
2102 */
2109 }
2110 }
2111 }
2112 }
2113 }
2116 /* Interrupt handler for data OUT traffic */
2118 {
2120 u32 tmp;
2132 /* BNA event ? */
2136 /* clear BNA */
2140 else
2144 }
2145 }
2146 /* HE event ? */
2150 /* clear HE */
2154 }
2158 /* next request */
2164 }
2166 /* fifo mode */
2169 /* read fifo */
2173 /* finish */
2175 /* next request */
2181 }
2183 /* DMA */
2187 /* check for DMA done */
2190 UDC_DMA_OUT_STS_BS);
2191 /* packet per buffer mode - rx bytes */
2193 /*
2194 * if BNA occurred then recover desc. from
2195 * BNA dummy desc.
2196 */
2203 }
2206 }
2208 /* buffer fill mode - rx bytes */
2210 /* received number bytes */
2212 UDC_DMA_OUT_STS_RXBYTES);
2214 /* packet per buffer mode - rx bytes */
2218 /* received number bytes */
2220 /* every desc. counts bytes */
2223 /* last desc. counts bytes */
2225 UDC_DMA_OUT_STS_RXBYTES);
2228 /*
2229 * on 64k packets the RXBYTES
2230 * field is zero
2231 */
2233 }
2234 }
2236 }
2244 }
2246 }
2249 /* complete request */
2252 /* next request */
2256 queue);
2257 /*
2258 * DMA may be already started by udc_queue()
2259 * called by gadget drivers completion
2260 * routine. This happens when queue
2261 * holds one request only.
2262 */
2264 /* next dma */
2267 /* write desc pointer */
2271 /* enable DMA */
2273 }
2275 /*
2276 * implant BNA dummy descriptor to allow
2277 * RXFIFO opening by RDE
2278 */
2280 /* write desc pointer */
2284 }
2286 /*
2287 * schedule timer for setting RDE if queue
2288 * remains empty to allow ep0 packets pass
2289 * through
2290 */
2294 jiffies
2299 }
2300 }
2303 }
2306 /*
2307 * RX DMA must be reenabled for each desc in PPBDU mode
2308 * and must be enabled for PPBNDU mode in case of BNA
2309 */
2311 }
2316 }
2318 /* check pending CNAKS */
2320 /* CNAk processing when rxfifo empty only */
2323 }
2324 }
2326 /* clear OUT bits in ep status */
2328 finished:
2330 }
2332 /* Interrupt handler for data IN traffic */
2334 {
2336 u32 tmp;
2337 u32 epsts;
2348 /* BNA ? */
2355 /* clear BNA */
2359 }
2360 }
2361 /* HE event ? */
2367 /* clear HE */
2371 }
2373 /* DMA completion */
2380 /*
2381 * length bytes transferred
2382 * check dma done of last desc. in PPBDU mode
2383 */
2387 dma_done =
2389 UDC_DMA_IN_STS_BS);
2390 /* don't care DMA done */
2392 }
2394 /* assume all bytes transferred */
2396 }
2399 /* complete req */
2402 /* further request available ? */
2404 /* disable interrupt */
2408 }
2409 }
2410 }
2413 }
2414 /*
2415 * status reg has IN bit set and TDC not set (if TDC was handled,
2416 * IN must not be handled (UDC defect) ?
2417 */
2422 /* next request */
2425 /* FIFO mode */
2427 /* write fifo */
2435 /* complete req */
2437 }
2438 /* DMA */
2446 /*
2447 * unset L bit of first desc.
2448 * for chain
2449 */
2454 UDC_DMA_IN_STS_L);
2455 }
2457 /* write desc pointer */
2460 /* set HOST READY */
2464 UDC_DMA_IN_STS_BS_HOST_READY,
2465 UDC_DMA_IN_STS_BS);
2467 /* set poll demand bit */
2471 }
2472 }
2475 /* disable interrupt */
2481 }
2482 }
2483 /* clear status bits */
2486 finished:
2489 }
2491 /* Interrupt handler for Control OUT traffic */
2495 {
2497 u32 tmp;
2499 u32 count;
2506 /* clear irq */
2510 /* check BNA and clear if set */
2518 }
2520 /* type of data: SETUP or DATA 0 bytes */
2524 /* setup data */
2531 /* set NAK for EP0_IN */
2536 /* get setup data */
2539 /* clear OUT bits in ep status */
2547 /* set HOST READY */
2549 UDC_DMA_STP_STS_BS_HOST_READY;
2551 /* read fifo */
2553 }
2555 /* determine direction of control data */
2558 /* enable RDE */
2563 /*
2564 * implant BNA dummy descriptor to allow RXFIFO opening
2565 * by RDE
2566 */
2568 /* write desc pointer */
2572 }
2576 /*
2577 * setup timer for enabling RDE (to not enable
2578 * RXFIFO DMA for data to early)
2579 */
2586 }
2587 }
2588 }
2590 /*
2591 * mass storage reset must be processed here because
2592 * next packet may be a CLEAR_FEATURE HALT which would not
2593 * clear the stall bit when no STALL handshake was received
2594 * before (autostall can cause this)
2595 */
2599 /*
2600 * clear stall bits
2601 * only one IN and OUT endpoints are handled
2602 */
2607 }
2609 /* call gadget with setup data received */
2616 /* ep0 in returns data (not zlp) on IN phase */
2618 UDC_EP0IN_MAXPACKET) {
2619 /* clear NAK by writing CNAK in EP0_IN */
2625 /* if unsupported request then stall */
2633 /* clear NAK by writing CNAK in EP0_OUT */
2640 }
2643 /* clear OUT bits in ep status */
2646 }
2648 /* data packet 0 bytes */
2650 /* clear OUT bits in ep status */
2653 /* get setup data: only 0 packet */
2655 /* no req if 0 packet, just reactivate */
2659 /* set HOST READY */
2663 UDC_DMA_OUT_STS_BS_HOST_READY,
2664 UDC_DMA_OUT_STS_BS);
2665 /* enable RDE */
2670 /* control write */
2672 /* re-program desc. pointer for possible ZLPs */
2675 /* enable RDE */
2677 }
2680 /* received number bytes */
2683 /* out data for fifo mode not working */
2686 /* 0 packet or real data ? */
2690 /* dummy read confirm */
2693 }
2694 }
2695 }
2697 /* check pending CNAKS */
2699 /* CNAk processing when rxfifo empty only */
2702 }
2703 }
2705 finished:
2707 }
2709 /* Interrupt handler for Control IN traffic */
2711 {
2713 u32 tmp;
2720 /* clear irq */
2724 /* DMA completion */
2729 /* clear TDC bit */
2733 /* status reg has IN bit set ? */
2738 /* clear IN bit */
2741 }
2744 /* halt ep0in */
2750 /* next request */
2755 /* write desc pointer */
2757 /* set HOST READY */
2761 UDC_DMA_STP_STS_BS_HOST_READY,
2762 UDC_DMA_STP_STS_BS);
2764 /* set poll demand bit */
2765 tmp =
2771 /* all bytes will be transferred */
2774 /* complete req */
2778 /* write fifo */
2781 /* lengh bytes transferred */
2789 /* complete req */
2791 }
2792 }
2794 }
2795 }
2799 /* clear IN bit */
2802 }
2803 }
2806 }
2809 /* Interrupt handler for global device events */
2813 {
2815 u32 tmp;
2816 u32 cfg;
2818 u16 i;
2819 u8 udc_csr_epix;
2821 /* SET_CONFIG irq ? */
2825 /* read config value */
2832 /* make usb request for gadget driver */
2837 /* programm the NE registers */
2842 /* ep ix in UDC CSR register space */
2846 /* OUT ep */
2848 /* ep ix in UDC CSR register space */
2850 }
2853 /* ep cfg */
2855 UDC_CSR_NE_CFG);
2856 /* write reg */
2859 /* clear stall bits */
2864 }
2865 /* call gadget zero with setup data received */
2875 /* read interface and alt setting values */
2880 /* make usb request for gadget driver */
2890 /* programm the NE registers */
2895 /* ep ix in UDC CSR register space */
2899 /* OUT ep */
2901 /* ep ix in UDC CSR register space */
2903 }
2905 /* UDC CSR reg */
2906 /* set ep values */
2908 /* ep interface */
2910 UDC_CSR_NE_INTF);
2911 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2912 /* ep alt */
2914 UDC_CSR_NE_ALT);
2915 /* write reg */
2918 /* clear stall bits */
2923 }
2925 /* call gadget zero with setup data received */
2935 /* allow soft reset when suspend occurs */
2941 /* mask not needed interrupts */
2944 /* call gadget to resume and reset configs etc. */
2949 }
2953 /* disable ep0 to empty req queue */
2957 /* soft reset when rxfifo not empty */
2962 soft_reset_after_usbreset_occured++;
2963 }
2965 /*
2966 * DMA reset to kill potential old DMA hw hang,
2967 * POLL bit is already reset by ep_init() through
2968 * disconnect()
2969 */
2975 /* put into initial config */
2978 /* enable device setup interrupts */
2981 /* enable suspend interrupt */
2995 }
3002 /* disable ep0 to empty req queue */
3006 /* link up all endpoints */
3011 /* init ep 0 */
3014 /* enable ep0 interrupts */
3016 }
3017 /* session valid change interrupt */
3022 /* check that session is not valid to detect disconnect */
3025 /* disable suspend interrupt */
3030 /* cleanup on disconnect */
3032 }
3034 }
3037 }
3039 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3041 {
3043 u32 reg;
3044 u16 i;
3045 u32 ep_irq;
3050 /* check for ep irq */
3058 /*
3059 * data endpoint
3060 * iterate ep's
3061 */
3067 /* clear irq status */
3070 /* irq for out ep ? */
3073 else
3075 }
3077 }
3080 /* check for dev irq */
3083 /* clear irq */
3086 }
3091 }
3093 /* Tears down device */
3095 {
3098 }
3100 /* Cleanup on device remove */
3102 {
3103 /* remove timer */
3104 stop_timer++;
3109 /* remove pollstall timer */
3110 stop_pollstall_timer++;
3116 }
3118 /* Reset all pci context */
3120 {
3126 /* gadget driver must not be registered */
3129 /* dma pool cleanup */
3134 /* cleanup DMA desc's for ep0in */
3143 }
3145 /* reset controller */
3161 }
3163 /* create dma pools on init */
3165 {
3170 /* consistent DMA mode setting ? */
3176 }
3178 /* DMA setup */
3185 }
3187 /* EP0 in dma regs = dev control regs */
3190 /* dma desc for setup data */
3197 }
3198 /* setup */
3204 }
3207 /* data: 0 packets !? */
3213 }
3217 finished:
3219 }
3221 /* Called by pci bus driver to init pci context */
3225 )
3226 {
3232 /* one udc only */
3236 }
3238 /* init */
3243 }
3245 /* pci setup */
3251 }
3254 /* PCI resource allocation */
3264 }
3274 }
3282 }
3285 /* udc csr registers base */
3287 /* dev registers base */
3289 /* ep registers base */
3291 /* fifo's base */
3301 }
3306 /* chip revision for Hs AMD5536 */
3312 /* init dma pools */
3317 }
3325 /* general probing */
3329 finished:
3333 }
3335 /* general probe */
3337 {
3339 u32 reg;
3342 /* mark timer as not initialized */
3346 /* device struct setup */
3354 /* init registers, interrupts, ... */
3369 }
3383 }
3385 /* timer init */
3389 /* timer pollstall init */
3394 /* set SD */
3399 /* print dev register info */
3404 finished:
3406 }
3408 /* Initiates a remote wakeup */
3410 {
3412 u32 tmp;
3426 }
3428 /* PCI device parameters */
3430 {
3434 },
3435 {},
3436 };
3439 /* PCI functions */
3445 };
3447 /* Inits driver */
3449 {
3451 }
3454 /* Cleans driver */
3456 {
3458 }