2 * R8A66597 UDC (USB gadget)
4 * Copyright (C) 2006-2009 Renesas Solutions Corp.
6 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/slab.h>
21 #include <linux/dma-mapping.h>
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/gadget.h>
26 #include "r8a66597-udc.h"
28 #define DRIVER_VERSION "2011-09-26"
30 static const char udc_name
[] = "r8a66597_udc";
31 static const char *r8a66597_ep_name
[] = {
32 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
36 static void init_controller(struct r8a66597
*r8a66597
);
37 static void disable_controller(struct r8a66597
*r8a66597
);
38 static void irq_ep0_write(struct r8a66597_ep
*ep
, struct r8a66597_request
*req
);
39 static void irq_packet_write(struct r8a66597_ep
*ep
,
40 struct r8a66597_request
*req
);
41 static int r8a66597_queue(struct usb_ep
*_ep
, struct usb_request
*_req
,
44 static void transfer_complete(struct r8a66597_ep
*ep
,
45 struct r8a66597_request
*req
, int status
);
47 /*-------------------------------------------------------------------------*/
48 static inline u16
get_usb_speed(struct r8a66597
*r8a66597
)
50 return r8a66597_read(r8a66597
, DVSTCTR0
) & RHST
;
53 static void enable_pipe_irq(struct r8a66597
*r8a66597
, u16 pipenum
,
58 tmp
= r8a66597_read(r8a66597
, INTENB0
);
59 r8a66597_bclr(r8a66597
, BEMPE
| NRDYE
| BRDYE
,
61 r8a66597_bset(r8a66597
, (1 << pipenum
), reg
);
62 r8a66597_write(r8a66597
, tmp
, INTENB0
);
65 static void disable_pipe_irq(struct r8a66597
*r8a66597
, u16 pipenum
,
70 tmp
= r8a66597_read(r8a66597
, INTENB0
);
71 r8a66597_bclr(r8a66597
, BEMPE
| NRDYE
| BRDYE
,
73 r8a66597_bclr(r8a66597
, (1 << pipenum
), reg
);
74 r8a66597_write(r8a66597
, tmp
, INTENB0
);
77 static void r8a66597_usb_connect(struct r8a66597
*r8a66597
)
79 r8a66597_bset(r8a66597
, CTRE
, INTENB0
);
80 r8a66597_bset(r8a66597
, BEMPE
| BRDYE
, INTENB0
);
82 r8a66597_bset(r8a66597
, DPRPU
, SYSCFG0
);
85 static void r8a66597_usb_disconnect(struct r8a66597
*r8a66597
)
86 __releases(r8a66597
->lock
)
87 __acquires(r8a66597
->lock
)
89 r8a66597_bclr(r8a66597
, CTRE
, INTENB0
);
90 r8a66597_bclr(r8a66597
, BEMPE
| BRDYE
, INTENB0
);
91 r8a66597_bclr(r8a66597
, DPRPU
, SYSCFG0
);
93 r8a66597
->gadget
.speed
= USB_SPEED_UNKNOWN
;
94 spin_unlock(&r8a66597
->lock
);
95 r8a66597
->driver
->disconnect(&r8a66597
->gadget
);
96 spin_lock(&r8a66597
->lock
);
98 disable_controller(r8a66597
);
99 init_controller(r8a66597
);
100 r8a66597_bset(r8a66597
, VBSE
, INTENB0
);
101 INIT_LIST_HEAD(&r8a66597
->ep
[0].queue
);
104 static inline u16
control_reg_get_pid(struct r8a66597
*r8a66597
, u16 pipenum
)
107 unsigned long offset
;
110 pid
= r8a66597_read(r8a66597
, DCPCTR
) & PID
;
111 } else if (pipenum
< R8A66597_MAX_NUM_PIPE
) {
112 offset
= get_pipectr_addr(pipenum
);
113 pid
= r8a66597_read(r8a66597
, offset
) & PID
;
115 dev_err(r8a66597_to_dev(r8a66597
), "unexpect pipe num (%d)\n",
122 static inline void control_reg_set_pid(struct r8a66597
*r8a66597
, u16 pipenum
,
125 unsigned long offset
;
128 r8a66597_mdfy(r8a66597
, pid
, PID
, DCPCTR
);
129 } else if (pipenum
< R8A66597_MAX_NUM_PIPE
) {
130 offset
= get_pipectr_addr(pipenum
);
131 r8a66597_mdfy(r8a66597
, pid
, PID
, offset
);
133 dev_err(r8a66597_to_dev(r8a66597
), "unexpect pipe num (%d)\n",
138 static inline void pipe_start(struct r8a66597
*r8a66597
, u16 pipenum
)
140 control_reg_set_pid(r8a66597
, pipenum
, PID_BUF
);
143 static inline void pipe_stop(struct r8a66597
*r8a66597
, u16 pipenum
)
145 control_reg_set_pid(r8a66597
, pipenum
, PID_NAK
);
148 static inline void pipe_stall(struct r8a66597
*r8a66597
, u16 pipenum
)
150 control_reg_set_pid(r8a66597
, pipenum
, PID_STALL
);
153 static inline u16
control_reg_get(struct r8a66597
*r8a66597
, u16 pipenum
)
156 unsigned long offset
;
159 ret
= r8a66597_read(r8a66597
, DCPCTR
);
160 } else if (pipenum
< R8A66597_MAX_NUM_PIPE
) {
161 offset
= get_pipectr_addr(pipenum
);
162 ret
= r8a66597_read(r8a66597
, offset
);
164 dev_err(r8a66597_to_dev(r8a66597
), "unexpect pipe num (%d)\n",
171 static inline void control_reg_sqclr(struct r8a66597
*r8a66597
, u16 pipenum
)
173 unsigned long offset
;
175 pipe_stop(r8a66597
, pipenum
);
178 r8a66597_bset(r8a66597
, SQCLR
, DCPCTR
);
179 } else if (pipenum
< R8A66597_MAX_NUM_PIPE
) {
180 offset
= get_pipectr_addr(pipenum
);
181 r8a66597_bset(r8a66597
, SQCLR
, offset
);
183 dev_err(r8a66597_to_dev(r8a66597
), "unexpect pipe num (%d)\n",
188 static void control_reg_sqset(struct r8a66597
*r8a66597
, u16 pipenum
)
190 unsigned long offset
;
192 pipe_stop(r8a66597
, pipenum
);
195 r8a66597_bset(r8a66597
, SQSET
, DCPCTR
);
196 } else if (pipenum
< R8A66597_MAX_NUM_PIPE
) {
197 offset
= get_pipectr_addr(pipenum
);
198 r8a66597_bset(r8a66597
, SQSET
, offset
);
200 dev_err(r8a66597_to_dev(r8a66597
),
201 "unexpect pipe num(%d)\n", pipenum
);
205 static u16
control_reg_sqmon(struct r8a66597
*r8a66597
, u16 pipenum
)
207 unsigned long offset
;
210 return r8a66597_read(r8a66597
, DCPCTR
) & SQMON
;
211 } else if (pipenum
< R8A66597_MAX_NUM_PIPE
) {
212 offset
= get_pipectr_addr(pipenum
);
213 return r8a66597_read(r8a66597
, offset
) & SQMON
;
215 dev_err(r8a66597_to_dev(r8a66597
),
216 "unexpect pipe num(%d)\n", pipenum
);
222 static u16
save_usb_toggle(struct r8a66597
*r8a66597
, u16 pipenum
)
224 return control_reg_sqmon(r8a66597
, pipenum
);
227 static void restore_usb_toggle(struct r8a66597
*r8a66597
, u16 pipenum
,
231 control_reg_sqset(r8a66597
, pipenum
);
233 control_reg_sqclr(r8a66597
, pipenum
);
236 static inline int get_buffer_size(struct r8a66597
*r8a66597
, u16 pipenum
)
242 tmp
= r8a66597_read(r8a66597
, DCPCFG
);
243 if ((tmp
& R8A66597_CNTMD
) != 0)
246 tmp
= r8a66597_read(r8a66597
, DCPMAXP
);
250 r8a66597_write(r8a66597
, pipenum
, PIPESEL
);
251 tmp
= r8a66597_read(r8a66597
, PIPECFG
);
252 if ((tmp
& R8A66597_CNTMD
) != 0) {
253 tmp
= r8a66597_read(r8a66597
, PIPEBUF
);
254 size
= ((tmp
>> 10) + 1) * 64;
256 tmp
= r8a66597_read(r8a66597
, PIPEMAXP
);
264 static inline unsigned short mbw_value(struct r8a66597
*r8a66597
)
266 if (r8a66597
->pdata
->on_chip
)
272 static void r8a66597_change_curpipe(struct r8a66597
*r8a66597
, u16 pipenum
,
273 u16 isel
, u16 fifosel
)
279 mask
= ISEL
| CURPIPE
;
285 r8a66597_mdfy(r8a66597
, loop
, mask
, fifosel
);
288 tmp
= r8a66597_read(r8a66597
, fifosel
);
290 dev_err(r8a66597_to_dev(r8a66597
),
291 "r8a66597: register%x, loop %x "
292 "is timeout\n", fifosel
, loop
);
296 } while ((tmp
& mask
) != loop
);
299 static inline void pipe_change(struct r8a66597
*r8a66597
, u16 pipenum
)
301 struct r8a66597_ep
*ep
= r8a66597
->pipenum2ep
[pipenum
];
304 r8a66597_bclr(r8a66597
, DREQE
, ep
->fifosel
);
306 r8a66597_mdfy(r8a66597
, pipenum
, CURPIPE
, ep
->fifosel
);
310 if (r8a66597_is_sudmac(r8a66597
) && ep
->use_dma
)
311 r8a66597_bclr(r8a66597
, mbw_value(r8a66597
), ep
->fifosel
);
313 r8a66597_bset(r8a66597
, mbw_value(r8a66597
), ep
->fifosel
);
316 r8a66597_bset(r8a66597
, DREQE
, ep
->fifosel
);
319 static int pipe_buffer_setting(struct r8a66597
*r8a66597
,
320 struct r8a66597_pipe_info
*info
)
322 u16 bufnum
= 0, buf_bsize
= 0;
328 r8a66597_write(r8a66597
, info
->pipe
, PIPESEL
);
331 pipecfg
|= R8A66597_DIR
;
332 pipecfg
|= info
->type
;
333 pipecfg
|= info
->epnum
;
334 switch (info
->type
) {
336 bufnum
= 4 + (info
->pipe
- R8A66597_BASE_PIPENUM_INT
);
340 /* isochronous pipes may be used as bulk pipes */
341 if (info
->pipe
>= R8A66597_BASE_PIPENUM_BULK
)
342 bufnum
= info
->pipe
- R8A66597_BASE_PIPENUM_BULK
;
344 bufnum
= info
->pipe
- R8A66597_BASE_PIPENUM_ISOC
;
346 bufnum
= R8A66597_BASE_BUFNUM
+ (bufnum
* 16);
348 pipecfg
|= R8A66597_DBLB
;
350 pipecfg
|= R8A66597_SHTNAK
;
353 bufnum
= R8A66597_BASE_BUFNUM
+
354 (info
->pipe
- R8A66597_BASE_PIPENUM_ISOC
) * 16;
359 if (buf_bsize
&& ((bufnum
+ 16) >= R8A66597_MAX_BUFNUM
)) {
360 pr_err("r8a66597 pipe memory is insufficient\n");
364 r8a66597_write(r8a66597
, pipecfg
, PIPECFG
);
365 r8a66597_write(r8a66597
, (buf_bsize
<< 10) | (bufnum
), PIPEBUF
);
366 r8a66597_write(r8a66597
, info
->maxpacket
, PIPEMAXP
);
369 r8a66597_write(r8a66597
, info
->interval
, PIPEPERI
);
374 static void pipe_buffer_release(struct r8a66597
*r8a66597
,
375 struct r8a66597_pipe_info
*info
)
380 if (is_bulk_pipe(info
->pipe
)) {
382 } else if (is_interrupt_pipe(info
->pipe
)) {
383 r8a66597
->interrupt
--;
384 } else if (is_isoc_pipe(info
->pipe
)) {
385 r8a66597
->isochronous
--;
386 if (info
->type
== R8A66597_BULK
)
389 dev_err(r8a66597_to_dev(r8a66597
),
390 "ep_release: unexpect pipenum (%d)\n", info
->pipe
);
394 static void pipe_initialize(struct r8a66597_ep
*ep
)
396 struct r8a66597
*r8a66597
= ep
->r8a66597
;
398 r8a66597_mdfy(r8a66597
, 0, CURPIPE
, ep
->fifosel
);
400 r8a66597_write(r8a66597
, ACLRM
, ep
->pipectr
);
401 r8a66597_write(r8a66597
, 0, ep
->pipectr
);
402 r8a66597_write(r8a66597
, SQCLR
, ep
->pipectr
);
404 r8a66597_mdfy(r8a66597
, ep
->pipenum
, CURPIPE
, ep
->fifosel
);
408 r8a66597_bset(r8a66597
, mbw_value(r8a66597
), ep
->fifosel
);
412 static void r8a66597_ep_setting(struct r8a66597
*r8a66597
,
413 struct r8a66597_ep
*ep
,
414 const struct usb_endpoint_descriptor
*desc
,
415 u16 pipenum
, int dma
)
418 ep
->fifoaddr
= CFIFO
;
419 ep
->fifosel
= CFIFOSEL
;
420 ep
->fifoctr
= CFIFOCTR
;
422 ep
->pipectr
= get_pipectr_addr(pipenum
);
423 if (is_bulk_pipe(pipenum
) || is_isoc_pipe(pipenum
)) {
424 ep
->pipetre
= get_pipetre_addr(pipenum
);
425 ep
->pipetrn
= get_pipetrn_addr(pipenum
);
430 ep
->pipenum
= pipenum
;
431 ep
->ep
.maxpacket
= usb_endpoint_maxp(desc
);
432 r8a66597
->pipenum2ep
[pipenum
] = ep
;
433 r8a66597
->epaddr2ep
[desc
->bEndpointAddress
& USB_ENDPOINT_NUMBER_MASK
]
435 INIT_LIST_HEAD(&ep
->queue
);
438 static void r8a66597_ep_release(struct r8a66597_ep
*ep
)
440 struct r8a66597
*r8a66597
= ep
->r8a66597
;
441 u16 pipenum
= ep
->pipenum
;
453 static int alloc_pipe_config(struct r8a66597_ep
*ep
,
454 const struct usb_endpoint_descriptor
*desc
)
456 struct r8a66597
*r8a66597
= ep
->r8a66597
;
457 struct r8a66597_pipe_info info
;
459 unsigned char *counter
;
464 if (ep
->pipenum
) /* already allocated pipe */
467 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
468 case USB_ENDPOINT_XFER_BULK
:
469 if (r8a66597
->bulk
>= R8A66597_MAX_NUM_BULK
) {
470 if (r8a66597
->isochronous
>= R8A66597_MAX_NUM_ISOC
) {
471 dev_err(r8a66597_to_dev(r8a66597
),
472 "bulk pipe is insufficient\n");
475 info
.pipe
= R8A66597_BASE_PIPENUM_ISOC
476 + r8a66597
->isochronous
;
477 counter
= &r8a66597
->isochronous
;
480 info
.pipe
= R8A66597_BASE_PIPENUM_BULK
+ r8a66597
->bulk
;
481 counter
= &r8a66597
->bulk
;
483 info
.type
= R8A66597_BULK
;
486 case USB_ENDPOINT_XFER_INT
:
487 if (r8a66597
->interrupt
>= R8A66597_MAX_NUM_INT
) {
488 dev_err(r8a66597_to_dev(r8a66597
),
489 "interrupt pipe is insufficient\n");
492 info
.pipe
= R8A66597_BASE_PIPENUM_INT
+ r8a66597
->interrupt
;
493 info
.type
= R8A66597_INT
;
494 counter
= &r8a66597
->interrupt
;
496 case USB_ENDPOINT_XFER_ISOC
:
497 if (r8a66597
->isochronous
>= R8A66597_MAX_NUM_ISOC
) {
498 dev_err(r8a66597_to_dev(r8a66597
),
499 "isochronous pipe is insufficient\n");
502 info
.pipe
= R8A66597_BASE_PIPENUM_ISOC
+ r8a66597
->isochronous
;
503 info
.type
= R8A66597_ISO
;
504 counter
= &r8a66597
->isochronous
;
507 dev_err(r8a66597_to_dev(r8a66597
), "unexpect xfer type\n");
510 ep
->type
= info
.type
;
512 info
.epnum
= desc
->bEndpointAddress
& USB_ENDPOINT_NUMBER_MASK
;
513 info
.maxpacket
= usb_endpoint_maxp(desc
);
514 info
.interval
= desc
->bInterval
;
515 if (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
)
520 ret
= pipe_buffer_setting(r8a66597
, &info
);
522 dev_err(r8a66597_to_dev(r8a66597
),
523 "pipe_buffer_setting fail\n");
528 if ((counter
== &r8a66597
->isochronous
) && info
.type
== R8A66597_BULK
)
531 r8a66597_ep_setting(r8a66597
, ep
, desc
, info
.pipe
, dma
);
537 static int free_pipe_config(struct r8a66597_ep
*ep
)
539 struct r8a66597
*r8a66597
= ep
->r8a66597
;
540 struct r8a66597_pipe_info info
;
542 info
.pipe
= ep
->pipenum
;
543 info
.type
= ep
->type
;
544 pipe_buffer_release(r8a66597
, &info
);
545 r8a66597_ep_release(ep
);
550 /*-------------------------------------------------------------------------*/
551 static void pipe_irq_enable(struct r8a66597
*r8a66597
, u16 pipenum
)
553 enable_irq_ready(r8a66597
, pipenum
);
554 enable_irq_nrdy(r8a66597
, pipenum
);
557 static void pipe_irq_disable(struct r8a66597
*r8a66597
, u16 pipenum
)
559 disable_irq_ready(r8a66597
, pipenum
);
560 disable_irq_nrdy(r8a66597
, pipenum
);
563 /* if complete is true, gadget driver complete function is not call */
564 static void control_end(struct r8a66597
*r8a66597
, unsigned ccpl
)
566 r8a66597
->ep
[0].internal_ccpl
= ccpl
;
567 pipe_start(r8a66597
, 0);
568 r8a66597_bset(r8a66597
, CCPL
, DCPCTR
);
571 static void start_ep0_write(struct r8a66597_ep
*ep
,
572 struct r8a66597_request
*req
)
574 struct r8a66597
*r8a66597
= ep
->r8a66597
;
576 pipe_change(r8a66597
, ep
->pipenum
);
577 r8a66597_mdfy(r8a66597
, ISEL
, (ISEL
| CURPIPE
), CFIFOSEL
);
578 r8a66597_write(r8a66597
, BCLR
, ep
->fifoctr
);
579 if (req
->req
.length
== 0) {
580 r8a66597_bset(r8a66597
, BVAL
, ep
->fifoctr
);
581 pipe_start(r8a66597
, 0);
582 transfer_complete(ep
, req
, 0);
584 r8a66597_write(r8a66597
, ~BEMP0
, BEMPSTS
);
585 irq_ep0_write(ep
, req
);
589 static void disable_fifosel(struct r8a66597
*r8a66597
, u16 pipenum
,
594 tmp
= r8a66597_read(r8a66597
, fifosel
) & CURPIPE
;
596 r8a66597_change_curpipe(r8a66597
, 0, 0, fifosel
);
599 static void change_bfre_mode(struct r8a66597
*r8a66597
, u16 pipenum
,
602 struct r8a66597_ep
*ep
= r8a66597
->pipenum2ep
[pipenum
];
605 /* check current BFRE bit */
606 r8a66597_write(r8a66597
, pipenum
, PIPESEL
);
607 tmp
= r8a66597_read(r8a66597
, PIPECFG
) & R8A66597_BFRE
;
608 if ((enable
&& tmp
) || (!enable
&& !tmp
))
611 /* change BFRE bit */
612 pipe_stop(r8a66597
, pipenum
);
613 disable_fifosel(r8a66597
, pipenum
, CFIFOSEL
);
614 disable_fifosel(r8a66597
, pipenum
, D0FIFOSEL
);
615 disable_fifosel(r8a66597
, pipenum
, D1FIFOSEL
);
617 toggle
= save_usb_toggle(r8a66597
, pipenum
);
619 r8a66597_write(r8a66597
, pipenum
, PIPESEL
);
621 r8a66597_bset(r8a66597
, R8A66597_BFRE
, PIPECFG
);
623 r8a66597_bclr(r8a66597
, R8A66597_BFRE
, PIPECFG
);
625 /* initialize for internal BFRE flag */
626 r8a66597_bset(r8a66597
, ACLRM
, ep
->pipectr
);
627 r8a66597_bclr(r8a66597
, ACLRM
, ep
->pipectr
);
629 restore_usb_toggle(r8a66597
, pipenum
, toggle
);
632 static int sudmac_alloc_channel(struct r8a66597
*r8a66597
,
633 struct r8a66597_ep
*ep
,
634 struct r8a66597_request
*req
)
636 struct r8a66597_dma
*dma
;
638 if (!r8a66597_is_sudmac(r8a66597
))
641 /* Check transfer type */
642 if (!is_bulk_pipe(ep
->pipenum
))
645 if (r8a66597
->dma
.used
)
648 /* set SUDMAC parameters */
649 dma
= &r8a66597
->dma
;
651 if (ep
->desc
->bEndpointAddress
& USB_DIR_IN
) {
655 change_bfre_mode(r8a66597
, ep
->pipenum
, 1);
658 /* set r8a66597_ep paramters */
661 ep
->fifoaddr
= D0FIFO
;
662 ep
->fifosel
= D0FIFOSEL
;
663 ep
->fifoctr
= D0FIFOCTR
;
666 req
->req
.dma
= dma_map_single(r8a66597_to_dev(ep
->r8a66597
),
667 req
->req
.buf
, req
->req
.length
,
668 dma
->dir
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
673 static void sudmac_free_channel(struct r8a66597
*r8a66597
,
674 struct r8a66597_ep
*ep
,
675 struct r8a66597_request
*req
)
677 if (!r8a66597_is_sudmac(r8a66597
))
680 dma_unmap_single(r8a66597_to_dev(ep
->r8a66597
),
681 req
->req
.dma
, req
->req
.length
,
682 ep
->dma
->dir
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
684 r8a66597_bclr(r8a66597
, DREQE
, ep
->fifosel
);
685 r8a66597_change_curpipe(r8a66597
, 0, 0, ep
->fifosel
);
689 ep
->fifoaddr
= CFIFO
;
690 ep
->fifosel
= CFIFOSEL
;
691 ep
->fifoctr
= CFIFOCTR
;
694 static void sudmac_start(struct r8a66597
*r8a66597
, struct r8a66597_ep
*ep
,
695 struct r8a66597_request
*req
)
697 BUG_ON(req
->req
.length
== 0);
699 r8a66597_sudmac_write(r8a66597
, LBA_WAIT
, CH0CFG
);
700 r8a66597_sudmac_write(r8a66597
, req
->req
.dma
, CH0BA
);
701 r8a66597_sudmac_write(r8a66597
, req
->req
.length
, CH0BBC
);
702 r8a66597_sudmac_write(r8a66597
, CH0ENDE
, DINTCTRL
);
704 r8a66597_sudmac_write(r8a66597
, DEN
, CH0DEN
);
707 static void start_packet_write(struct r8a66597_ep
*ep
,
708 struct r8a66597_request
*req
)
710 struct r8a66597
*r8a66597
= ep
->r8a66597
;
713 pipe_change(r8a66597
, ep
->pipenum
);
714 disable_irq_empty(r8a66597
, ep
->pipenum
);
715 pipe_start(r8a66597
, ep
->pipenum
);
717 if (req
->req
.length
== 0) {
718 transfer_complete(ep
, req
, 0);
720 r8a66597_write(r8a66597
, ~(1 << ep
->pipenum
), BRDYSTS
);
721 if (sudmac_alloc_channel(r8a66597
, ep
, req
) < 0) {
723 pipe_change(r8a66597
, ep
->pipenum
);
724 disable_irq_empty(r8a66597
, ep
->pipenum
);
725 pipe_start(r8a66597
, ep
->pipenum
);
726 tmp
= r8a66597_read(r8a66597
, ep
->fifoctr
);
727 if (unlikely((tmp
& FRDY
) == 0))
728 pipe_irq_enable(r8a66597
, ep
->pipenum
);
730 irq_packet_write(ep
, req
);
733 pipe_change(r8a66597
, ep
->pipenum
);
734 disable_irq_nrdy(r8a66597
, ep
->pipenum
);
735 pipe_start(r8a66597
, ep
->pipenum
);
736 enable_irq_nrdy(r8a66597
, ep
->pipenum
);
737 sudmac_start(r8a66597
, ep
, req
);
742 static void start_packet_read(struct r8a66597_ep
*ep
,
743 struct r8a66597_request
*req
)
745 struct r8a66597
*r8a66597
= ep
->r8a66597
;
746 u16 pipenum
= ep
->pipenum
;
748 if (ep
->pipenum
== 0) {
749 r8a66597_mdfy(r8a66597
, 0, (ISEL
| CURPIPE
), CFIFOSEL
);
750 r8a66597_write(r8a66597
, BCLR
, ep
->fifoctr
);
751 pipe_start(r8a66597
, pipenum
);
752 pipe_irq_enable(r8a66597
, pipenum
);
754 pipe_stop(r8a66597
, pipenum
);
756 enable_irq_nrdy(r8a66597
, pipenum
);
757 r8a66597_write(r8a66597
, TRCLR
, ep
->pipetre
);
758 r8a66597_write(r8a66597
,
759 DIV_ROUND_UP(req
->req
.length
, ep
->ep
.maxpacket
),
761 r8a66597_bset(r8a66597
, TRENB
, ep
->pipetre
);
764 if (sudmac_alloc_channel(r8a66597
, ep
, req
) < 0) {
766 change_bfre_mode(r8a66597
, ep
->pipenum
, 0);
767 pipe_start(r8a66597
, pipenum
); /* trigger once */
768 pipe_irq_enable(r8a66597
, pipenum
);
770 pipe_change(r8a66597
, pipenum
);
771 sudmac_start(r8a66597
, ep
, req
);
772 pipe_start(r8a66597
, pipenum
); /* trigger once */
777 static void start_packet(struct r8a66597_ep
*ep
, struct r8a66597_request
*req
)
779 if (ep
->desc
->bEndpointAddress
& USB_DIR_IN
)
780 start_packet_write(ep
, req
);
782 start_packet_read(ep
, req
);
785 static void start_ep0(struct r8a66597_ep
*ep
, struct r8a66597_request
*req
)
789 ctsq
= r8a66597_read(ep
->r8a66597
, INTSTS0
) & CTSQ
;
793 start_ep0_write(ep
, req
);
796 start_packet_read(ep
, req
);
800 control_end(ep
->r8a66597
, 0);
803 dev_err(r8a66597_to_dev(ep
->r8a66597
),
804 "start_ep0: unexpect ctsq(%x)\n", ctsq
);
809 static void init_controller(struct r8a66597
*r8a66597
)
811 u16 vif
= r8a66597
->pdata
->vif
? LDRV
: 0;
812 u16 irq_sense
= r8a66597
->irq_sense_low
? INTL
: 0;
813 u16 endian
= r8a66597
->pdata
->endian
? BIGEND
: 0;
815 if (r8a66597
->pdata
->on_chip
) {
816 if (r8a66597
->pdata
->buswait
)
817 r8a66597_write(r8a66597
, r8a66597
->pdata
->buswait
,
820 r8a66597_write(r8a66597
, 0x0f, SYSCFG1
);
821 r8a66597_bset(r8a66597
, HSE
, SYSCFG0
);
823 r8a66597_bclr(r8a66597
, USBE
, SYSCFG0
);
824 r8a66597_bclr(r8a66597
, DPRPU
, SYSCFG0
);
825 r8a66597_bset(r8a66597
, USBE
, SYSCFG0
);
827 r8a66597_bset(r8a66597
, SCKE
, SYSCFG0
);
829 r8a66597_bset(r8a66597
, irq_sense
, INTENB1
);
830 r8a66597_write(r8a66597
, BURST
| CPU_ADR_RD_WR
,
833 r8a66597_bset(r8a66597
, vif
| endian
, PINCFG
);
834 r8a66597_bset(r8a66597
, HSE
, SYSCFG0
); /* High spd */
835 r8a66597_mdfy(r8a66597
, get_xtal_from_pdata(r8a66597
->pdata
),
838 r8a66597_bclr(r8a66597
, USBE
, SYSCFG0
);
839 r8a66597_bclr(r8a66597
, DPRPU
, SYSCFG0
);
840 r8a66597_bset(r8a66597
, USBE
, SYSCFG0
);
842 r8a66597_bset(r8a66597
, XCKE
, SYSCFG0
);
846 r8a66597_bset(r8a66597
, PLLC
, SYSCFG0
);
850 r8a66597_bset(r8a66597
, SCKE
, SYSCFG0
);
852 r8a66597_bset(r8a66597
, irq_sense
, INTENB1
);
853 r8a66597_write(r8a66597
, BURST
| CPU_ADR_RD_WR
,
858 static void disable_controller(struct r8a66597
*r8a66597
)
860 if (r8a66597
->pdata
->on_chip
) {
861 r8a66597_bset(r8a66597
, SCKE
, SYSCFG0
);
862 r8a66597_bclr(r8a66597
, UTST
, TESTMODE
);
864 /* disable interrupts */
865 r8a66597_write(r8a66597
, 0, INTENB0
);
866 r8a66597_write(r8a66597
, 0, INTENB1
);
867 r8a66597_write(r8a66597
, 0, BRDYENB
);
868 r8a66597_write(r8a66597
, 0, BEMPENB
);
869 r8a66597_write(r8a66597
, 0, NRDYENB
);
872 r8a66597_write(r8a66597
, 0, BRDYSTS
);
873 r8a66597_write(r8a66597
, 0, NRDYSTS
);
874 r8a66597_write(r8a66597
, 0, BEMPSTS
);
876 r8a66597_bclr(r8a66597
, USBE
, SYSCFG0
);
877 r8a66597_bclr(r8a66597
, SCKE
, SYSCFG0
);
880 r8a66597_bclr(r8a66597
, UTST
, TESTMODE
);
881 r8a66597_bclr(r8a66597
, SCKE
, SYSCFG0
);
883 r8a66597_bclr(r8a66597
, PLLC
, SYSCFG0
);
886 r8a66597_bclr(r8a66597
, XCKE
, SYSCFG0
);
890 static void r8a66597_start_xclock(struct r8a66597
*r8a66597
)
894 if (!r8a66597
->pdata
->on_chip
) {
895 tmp
= r8a66597_read(r8a66597
, SYSCFG0
);
897 r8a66597_bset(r8a66597
, XCKE
, SYSCFG0
);
901 static struct r8a66597_request
*get_request_from_ep(struct r8a66597_ep
*ep
)
903 return list_entry(ep
->queue
.next
, struct r8a66597_request
, queue
);
906 /*-------------------------------------------------------------------------*/
907 static void transfer_complete(struct r8a66597_ep
*ep
,
908 struct r8a66597_request
*req
, int status
)
909 __releases(r8a66597
->lock
)
910 __acquires(r8a66597
->lock
)
914 if (unlikely(ep
->pipenum
== 0)) {
915 if (ep
->internal_ccpl
) {
916 ep
->internal_ccpl
= 0;
921 list_del_init(&req
->queue
);
922 if (ep
->r8a66597
->gadget
.speed
== USB_SPEED_UNKNOWN
)
923 req
->req
.status
= -ESHUTDOWN
;
925 req
->req
.status
= status
;
927 if (!list_empty(&ep
->queue
))
931 sudmac_free_channel(ep
->r8a66597
, ep
, req
);
933 spin_unlock(&ep
->r8a66597
->lock
);
934 req
->req
.complete(&ep
->ep
, &req
->req
);
935 spin_lock(&ep
->r8a66597
->lock
);
938 req
= get_request_from_ep(ep
);
940 start_packet(ep
, req
);
944 static void irq_ep0_write(struct r8a66597_ep
*ep
, struct r8a66597_request
*req
)
951 u16 pipenum
= ep
->pipenum
;
952 struct r8a66597
*r8a66597
= ep
->r8a66597
;
954 pipe_change(r8a66597
, pipenum
);
955 r8a66597_bset(r8a66597
, ISEL
, ep
->fifosel
);
959 tmp
= r8a66597_read(r8a66597
, ep
->fifoctr
);
961 dev_err(r8a66597_to_dev(r8a66597
),
962 "pipe0 is busy. maybe cpu i/o bus "
963 "conflict. please power off this controller.");
967 } while ((tmp
& FRDY
) == 0);
969 /* prepare parameters */
970 bufsize
= get_buffer_size(r8a66597
, pipenum
);
971 buf
= req
->req
.buf
+ req
->req
.actual
;
972 size
= min(bufsize
, req
->req
.length
- req
->req
.actual
);
977 r8a66597_write_fifo(r8a66597
, ep
, buf
, size
);
978 if ((size
== 0) || ((size
% ep
->ep
.maxpacket
) != 0))
979 r8a66597_bset(r8a66597
, BVAL
, ep
->fifoctr
);
982 /* update parameters */
983 req
->req
.actual
+= size
;
985 /* check transfer finish */
986 if ((!req
->req
.zero
&& (req
->req
.actual
== req
->req
.length
))
987 || (size
% ep
->ep
.maxpacket
)
989 disable_irq_ready(r8a66597
, pipenum
);
990 disable_irq_empty(r8a66597
, pipenum
);
992 disable_irq_ready(r8a66597
, pipenum
);
993 enable_irq_empty(r8a66597
, pipenum
);
995 pipe_start(r8a66597
, pipenum
);
998 static void irq_packet_write(struct r8a66597_ep
*ep
,
999 struct r8a66597_request
*req
)
1005 u16 pipenum
= ep
->pipenum
;
1006 struct r8a66597
*r8a66597
= ep
->r8a66597
;
1008 pipe_change(r8a66597
, pipenum
);
1009 tmp
= r8a66597_read(r8a66597
, ep
->fifoctr
);
1010 if (unlikely((tmp
& FRDY
) == 0)) {
1011 pipe_stop(r8a66597
, pipenum
);
1012 pipe_irq_disable(r8a66597
, pipenum
);
1013 dev_err(r8a66597_to_dev(r8a66597
),
1014 "write fifo not ready. pipnum=%d\n", pipenum
);
1018 /* prepare parameters */
1019 bufsize
= get_buffer_size(r8a66597
, pipenum
);
1020 buf
= req
->req
.buf
+ req
->req
.actual
;
1021 size
= min(bufsize
, req
->req
.length
- req
->req
.actual
);
1025 r8a66597_write_fifo(r8a66597
, ep
, buf
, size
);
1027 || ((size
% ep
->ep
.maxpacket
) != 0)
1028 || ((bufsize
!= ep
->ep
.maxpacket
)
1029 && (bufsize
> size
)))
1030 r8a66597_bset(r8a66597
, BVAL
, ep
->fifoctr
);
1033 /* update parameters */
1034 req
->req
.actual
+= size
;
1035 /* check transfer finish */
1036 if ((!req
->req
.zero
&& (req
->req
.actual
== req
->req
.length
))
1037 || (size
% ep
->ep
.maxpacket
)
1039 disable_irq_ready(r8a66597
, pipenum
);
1040 enable_irq_empty(r8a66597
, pipenum
);
1042 disable_irq_empty(r8a66597
, pipenum
);
1043 pipe_irq_enable(r8a66597
, pipenum
);
1047 static void irq_packet_read(struct r8a66597_ep
*ep
,
1048 struct r8a66597_request
*req
)
1051 int rcv_len
, bufsize
, req_len
;
1054 u16 pipenum
= ep
->pipenum
;
1055 struct r8a66597
*r8a66597
= ep
->r8a66597
;
1058 pipe_change(r8a66597
, pipenum
);
1059 tmp
= r8a66597_read(r8a66597
, ep
->fifoctr
);
1060 if (unlikely((tmp
& FRDY
) == 0)) {
1061 req
->req
.status
= -EPIPE
;
1062 pipe_stop(r8a66597
, pipenum
);
1063 pipe_irq_disable(r8a66597
, pipenum
);
1064 dev_err(r8a66597_to_dev(r8a66597
), "read fifo not ready");
1068 /* prepare parameters */
1069 rcv_len
= tmp
& DTLN
;
1070 bufsize
= get_buffer_size(r8a66597
, pipenum
);
1072 buf
= req
->req
.buf
+ req
->req
.actual
;
1073 req_len
= req
->req
.length
- req
->req
.actual
;
1074 if (rcv_len
< bufsize
)
1075 size
= min(rcv_len
, req_len
);
1077 size
= min(bufsize
, req_len
);
1079 /* update parameters */
1080 req
->req
.actual
+= size
;
1082 /* check transfer finish */
1083 if ((!req
->req
.zero
&& (req
->req
.actual
== req
->req
.length
))
1084 || (size
% ep
->ep
.maxpacket
)
1086 pipe_stop(r8a66597
, pipenum
);
1087 pipe_irq_disable(r8a66597
, pipenum
);
1094 r8a66597_write(r8a66597
, BCLR
, ep
->fifoctr
);
1096 r8a66597_read_fifo(r8a66597
, ep
->fifoaddr
, buf
, size
);
1100 if ((ep
->pipenum
!= 0) && finish
)
1101 transfer_complete(ep
, req
, 0);
1104 static void irq_pipe_ready(struct r8a66597
*r8a66597
, u16 status
, u16 enb
)
1108 struct r8a66597_ep
*ep
;
1109 struct r8a66597_request
*req
;
1111 if ((status
& BRDY0
) && (enb
& BRDY0
)) {
1112 r8a66597_write(r8a66597
, ~BRDY0
, BRDYSTS
);
1113 r8a66597_mdfy(r8a66597
, 0, CURPIPE
, CFIFOSEL
);
1115 ep
= &r8a66597
->ep
[0];
1116 req
= get_request_from_ep(ep
);
1117 irq_packet_read(ep
, req
);
1119 for (pipenum
= 1; pipenum
< R8A66597_MAX_NUM_PIPE
; pipenum
++) {
1120 check
= 1 << pipenum
;
1121 if ((status
& check
) && (enb
& check
)) {
1122 r8a66597_write(r8a66597
, ~check
, BRDYSTS
);
1123 ep
= r8a66597
->pipenum2ep
[pipenum
];
1124 req
= get_request_from_ep(ep
);
1125 if (ep
->desc
->bEndpointAddress
& USB_DIR_IN
)
1126 irq_packet_write(ep
, req
);
1128 irq_packet_read(ep
, req
);
1134 static void irq_pipe_empty(struct r8a66597
*r8a66597
, u16 status
, u16 enb
)
1139 struct r8a66597_ep
*ep
;
1140 struct r8a66597_request
*req
;
1142 if ((status
& BEMP0
) && (enb
& BEMP0
)) {
1143 r8a66597_write(r8a66597
, ~BEMP0
, BEMPSTS
);
1145 ep
= &r8a66597
->ep
[0];
1146 req
= get_request_from_ep(ep
);
1147 irq_ep0_write(ep
, req
);
1149 for (pipenum
= 1; pipenum
< R8A66597_MAX_NUM_PIPE
; pipenum
++) {
1150 check
= 1 << pipenum
;
1151 if ((status
& check
) && (enb
& check
)) {
1152 r8a66597_write(r8a66597
, ~check
, BEMPSTS
);
1153 tmp
= control_reg_get(r8a66597
, pipenum
);
1154 if ((tmp
& INBUFM
) == 0) {
1155 disable_irq_empty(r8a66597
, pipenum
);
1156 pipe_irq_disable(r8a66597
, pipenum
);
1157 pipe_stop(r8a66597
, pipenum
);
1158 ep
= r8a66597
->pipenum2ep
[pipenum
];
1159 req
= get_request_from_ep(ep
);
1160 if (!list_empty(&ep
->queue
))
1161 transfer_complete(ep
, req
, 0);
1168 static void get_status(struct r8a66597
*r8a66597
, struct usb_ctrlrequest
*ctrl
)
1169 __releases(r8a66597
->lock
)
1170 __acquires(r8a66597
->lock
)
1172 struct r8a66597_ep
*ep
;
1175 u16 w_index
= le16_to_cpu(ctrl
->wIndex
);
1177 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1178 case USB_RECIP_DEVICE
:
1179 status
= 1 << USB_DEVICE_SELF_POWERED
;
1181 case USB_RECIP_INTERFACE
:
1184 case USB_RECIP_ENDPOINT
:
1185 ep
= r8a66597
->epaddr2ep
[w_index
& USB_ENDPOINT_NUMBER_MASK
];
1186 pid
= control_reg_get_pid(r8a66597
, ep
->pipenum
);
1187 if (pid
== PID_STALL
)
1188 status
= 1 << USB_ENDPOINT_HALT
;
1193 pipe_stall(r8a66597
, 0);
1197 r8a66597
->ep0_data
= cpu_to_le16(status
);
1198 r8a66597
->ep0_req
->buf
= &r8a66597
->ep0_data
;
1199 r8a66597
->ep0_req
->length
= 2;
1200 /* AV: what happens if we get called again before that gets through? */
1201 spin_unlock(&r8a66597
->lock
);
1202 r8a66597_queue(r8a66597
->gadget
.ep0
, r8a66597
->ep0_req
, GFP_KERNEL
);
1203 spin_lock(&r8a66597
->lock
);
1206 static void clear_feature(struct r8a66597
*r8a66597
,
1207 struct usb_ctrlrequest
*ctrl
)
1209 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1210 case USB_RECIP_DEVICE
:
1211 control_end(r8a66597
, 1);
1213 case USB_RECIP_INTERFACE
:
1214 control_end(r8a66597
, 1);
1216 case USB_RECIP_ENDPOINT
: {
1217 struct r8a66597_ep
*ep
;
1218 struct r8a66597_request
*req
;
1219 u16 w_index
= le16_to_cpu(ctrl
->wIndex
);
1221 ep
= r8a66597
->epaddr2ep
[w_index
& USB_ENDPOINT_NUMBER_MASK
];
1223 pipe_stop(r8a66597
, ep
->pipenum
);
1224 control_reg_sqclr(r8a66597
, ep
->pipenum
);
1225 spin_unlock(&r8a66597
->lock
);
1226 usb_ep_clear_halt(&ep
->ep
);
1227 spin_lock(&r8a66597
->lock
);
1230 control_end(r8a66597
, 1);
1232 req
= get_request_from_ep(ep
);
1235 if (list_empty(&ep
->queue
))
1237 start_packet(ep
, req
);
1238 } else if (!list_empty(&ep
->queue
))
1239 pipe_start(r8a66597
, ep
->pipenum
);
1243 pipe_stall(r8a66597
, 0);
1248 static void set_feature(struct r8a66597
*r8a66597
, struct usb_ctrlrequest
*ctrl
)
1253 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1254 case USB_RECIP_DEVICE
:
1255 switch (le16_to_cpu(ctrl
->wValue
)) {
1256 case USB_DEVICE_TEST_MODE
:
1257 control_end(r8a66597
, 1);
1258 /* Wait for the completion of status stage */
1260 tmp
= r8a66597_read(r8a66597
, INTSTS0
) & CTSQ
;
1262 } while (tmp
!= CS_IDST
|| timeout
-- > 0);
1265 r8a66597_bset(r8a66597
,
1266 le16_to_cpu(ctrl
->wIndex
>> 8),
1270 pipe_stall(r8a66597
, 0);
1274 case USB_RECIP_INTERFACE
:
1275 control_end(r8a66597
, 1);
1277 case USB_RECIP_ENDPOINT
: {
1278 struct r8a66597_ep
*ep
;
1279 u16 w_index
= le16_to_cpu(ctrl
->wIndex
);
1281 ep
= r8a66597
->epaddr2ep
[w_index
& USB_ENDPOINT_NUMBER_MASK
];
1282 pipe_stall(r8a66597
, ep
->pipenum
);
1284 control_end(r8a66597
, 1);
1288 pipe_stall(r8a66597
, 0);
1293 /* if return value is true, call class driver's setup() */
1294 static int setup_packet(struct r8a66597
*r8a66597
, struct usb_ctrlrequest
*ctrl
)
1296 u16
*p
= (u16
*)ctrl
;
1297 unsigned long offset
= USBREQ
;
1301 r8a66597_write(r8a66597
, ~VALID
, INTSTS0
);
1303 for (i
= 0; i
< 4; i
++)
1304 p
[i
] = r8a66597_read(r8a66597
, offset
+ i
*2);
1307 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1308 switch (ctrl
->bRequest
) {
1309 case USB_REQ_GET_STATUS
:
1310 get_status(r8a66597
, ctrl
);
1312 case USB_REQ_CLEAR_FEATURE
:
1313 clear_feature(r8a66597
, ctrl
);
1315 case USB_REQ_SET_FEATURE
:
1316 set_feature(r8a66597
, ctrl
);
1327 static void r8a66597_update_usb_speed(struct r8a66597
*r8a66597
)
1329 u16 speed
= get_usb_speed(r8a66597
);
1333 r8a66597
->gadget
.speed
= USB_SPEED_HIGH
;
1336 r8a66597
->gadget
.speed
= USB_SPEED_FULL
;
1339 r8a66597
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1340 dev_err(r8a66597_to_dev(r8a66597
), "USB speed unknown\n");
1344 static void irq_device_state(struct r8a66597
*r8a66597
)
1348 dvsq
= r8a66597_read(r8a66597
, INTSTS0
) & DVSQ
;
1349 r8a66597_write(r8a66597
, ~DVST
, INTSTS0
);
1351 if (dvsq
== DS_DFLT
) {
1353 spin_unlock(&r8a66597
->lock
);
1354 r8a66597
->driver
->disconnect(&r8a66597
->gadget
);
1355 spin_lock(&r8a66597
->lock
);
1356 r8a66597_update_usb_speed(r8a66597
);
1358 if (r8a66597
->old_dvsq
== DS_CNFG
&& dvsq
!= DS_CNFG
)
1359 r8a66597_update_usb_speed(r8a66597
);
1360 if ((dvsq
== DS_CNFG
|| dvsq
== DS_ADDS
)
1361 && r8a66597
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1362 r8a66597_update_usb_speed(r8a66597
);
1364 r8a66597
->old_dvsq
= dvsq
;
1367 static void irq_control_stage(struct r8a66597
*r8a66597
)
1368 __releases(r8a66597
->lock
)
1369 __acquires(r8a66597
->lock
)
1371 struct usb_ctrlrequest ctrl
;
1374 ctsq
= r8a66597_read(r8a66597
, INTSTS0
) & CTSQ
;
1375 r8a66597_write(r8a66597
, ~CTRT
, INTSTS0
);
1379 struct r8a66597_ep
*ep
;
1380 struct r8a66597_request
*req
;
1381 ep
= &r8a66597
->ep
[0];
1382 req
= get_request_from_ep(ep
);
1383 transfer_complete(ep
, req
, 0);
1390 if (setup_packet(r8a66597
, &ctrl
)) {
1391 spin_unlock(&r8a66597
->lock
);
1392 if (r8a66597
->driver
->setup(&r8a66597
->gadget
, &ctrl
)
1394 pipe_stall(r8a66597
, 0);
1395 spin_lock(&r8a66597
->lock
);
1400 control_end(r8a66597
, 0);
1403 dev_err(r8a66597_to_dev(r8a66597
),
1404 "ctrl_stage: unexpect ctsq(%x)\n", ctsq
);
1409 static void sudmac_finish(struct r8a66597
*r8a66597
, struct r8a66597_ep
*ep
)
1412 struct r8a66597_request
*req
;
1416 pipenum
= ep
->pipenum
;
1417 pipe_change(r8a66597
, pipenum
);
1419 while (!(r8a66597_read(r8a66597
, ep
->fifoctr
) & FRDY
)) {
1421 if (unlikely(i
++ >= 10000)) { /* timeout = 10 msec */
1422 dev_err(r8a66597_to_dev(r8a66597
),
1423 "%s: FRDY was not set (%d)\n",
1429 r8a66597_bset(r8a66597
, BCLR
, ep
->fifoctr
);
1430 req
= get_request_from_ep(ep
);
1432 /* prepare parameters */
1433 len
= r8a66597_sudmac_read(r8a66597
, CH0CBC
);
1434 req
->req
.actual
+= len
;
1437 r8a66597_sudmac_write(r8a66597
, CH0STCLR
, DSTSCLR
);
1439 /* check transfer finish */
1440 if ((!req
->req
.zero
&& (req
->req
.actual
== req
->req
.length
))
1441 || (len
% ep
->ep
.maxpacket
)) {
1443 disable_irq_ready(r8a66597
, pipenum
);
1444 enable_irq_empty(r8a66597
, pipenum
);
1446 /* Clear the interrupt flag for next transfer */
1447 r8a66597_write(r8a66597
, ~(1 << pipenum
), BRDYSTS
);
1448 transfer_complete(ep
, req
, 0);
1453 static void r8a66597_sudmac_irq(struct r8a66597
*r8a66597
)
1456 struct r8a66597_ep
*ep
;
1459 irqsts
= r8a66597_sudmac_read(r8a66597
, DINTSTS
);
1460 if (irqsts
& CH0ENDS
) {
1461 r8a66597_sudmac_write(r8a66597
, CH0ENDC
, DINTSTSCLR
);
1462 pipenum
= (r8a66597_read(r8a66597
, D0FIFOSEL
) & CURPIPE
);
1463 ep
= r8a66597
->pipenum2ep
[pipenum
];
1464 sudmac_finish(r8a66597
, ep
);
1468 static irqreturn_t
r8a66597_irq(int irq
, void *_r8a66597
)
1470 struct r8a66597
*r8a66597
= _r8a66597
;
1473 u16 brdysts
, nrdysts
, bempsts
;
1474 u16 brdyenb
, nrdyenb
, bempenb
;
1478 if (r8a66597_is_sudmac(r8a66597
))
1479 r8a66597_sudmac_irq(r8a66597
);
1481 spin_lock(&r8a66597
->lock
);
1483 intsts0
= r8a66597_read(r8a66597
, INTSTS0
);
1484 intenb0
= r8a66597_read(r8a66597
, INTENB0
);
1486 savepipe
= r8a66597_read(r8a66597
, CFIFOSEL
);
1488 mask0
= intsts0
& intenb0
;
1490 brdysts
= r8a66597_read(r8a66597
, BRDYSTS
);
1491 nrdysts
= r8a66597_read(r8a66597
, NRDYSTS
);
1492 bempsts
= r8a66597_read(r8a66597
, BEMPSTS
);
1493 brdyenb
= r8a66597_read(r8a66597
, BRDYENB
);
1494 nrdyenb
= r8a66597_read(r8a66597
, NRDYENB
);
1495 bempenb
= r8a66597_read(r8a66597
, BEMPENB
);
1497 if (mask0
& VBINT
) {
1498 r8a66597_write(r8a66597
, 0xffff & ~VBINT
,
1500 r8a66597_start_xclock(r8a66597
);
1502 /* start vbus sampling */
1503 r8a66597
->old_vbus
= r8a66597_read(r8a66597
, INTSTS0
)
1505 r8a66597
->scount
= R8A66597_MAX_SAMPLING
;
1507 mod_timer(&r8a66597
->timer
,
1508 jiffies
+ msecs_to_jiffies(50));
1511 irq_device_state(r8a66597
);
1513 if ((intsts0
& BRDY
) && (intenb0
& BRDYE
)
1514 && (brdysts
& brdyenb
))
1515 irq_pipe_ready(r8a66597
, brdysts
, brdyenb
);
1516 if ((intsts0
& BEMP
) && (intenb0
& BEMPE
)
1517 && (bempsts
& bempenb
))
1518 irq_pipe_empty(r8a66597
, bempsts
, bempenb
);
1521 irq_control_stage(r8a66597
);
1524 r8a66597_write(r8a66597
, savepipe
, CFIFOSEL
);
1526 spin_unlock(&r8a66597
->lock
);
1530 static void r8a66597_timer(unsigned long _r8a66597
)
1532 struct r8a66597
*r8a66597
= (struct r8a66597
*)_r8a66597
;
1533 unsigned long flags
;
1536 spin_lock_irqsave(&r8a66597
->lock
, flags
);
1537 tmp
= r8a66597_read(r8a66597
, SYSCFG0
);
1538 if (r8a66597
->scount
> 0) {
1539 tmp
= r8a66597_read(r8a66597
, INTSTS0
) & VBSTS
;
1540 if (tmp
== r8a66597
->old_vbus
) {
1542 if (r8a66597
->scount
== 0) {
1544 r8a66597_usb_connect(r8a66597
);
1546 r8a66597_usb_disconnect(r8a66597
);
1548 mod_timer(&r8a66597
->timer
,
1549 jiffies
+ msecs_to_jiffies(50));
1552 r8a66597
->scount
= R8A66597_MAX_SAMPLING
;
1553 r8a66597
->old_vbus
= tmp
;
1554 mod_timer(&r8a66597
->timer
,
1555 jiffies
+ msecs_to_jiffies(50));
1558 spin_unlock_irqrestore(&r8a66597
->lock
, flags
);
1561 /*-------------------------------------------------------------------------*/
1562 static int r8a66597_enable(struct usb_ep
*_ep
,
1563 const struct usb_endpoint_descriptor
*desc
)
1565 struct r8a66597_ep
*ep
;
1567 ep
= container_of(_ep
, struct r8a66597_ep
, ep
);
1568 return alloc_pipe_config(ep
, desc
);
1571 static int r8a66597_disable(struct usb_ep
*_ep
)
1573 struct r8a66597_ep
*ep
;
1574 struct r8a66597_request
*req
;
1575 unsigned long flags
;
1577 ep
= container_of(_ep
, struct r8a66597_ep
, ep
);
1580 while (!list_empty(&ep
->queue
)) {
1581 req
= get_request_from_ep(ep
);
1582 spin_lock_irqsave(&ep
->r8a66597
->lock
, flags
);
1583 transfer_complete(ep
, req
, -ECONNRESET
);
1584 spin_unlock_irqrestore(&ep
->r8a66597
->lock
, flags
);
1587 pipe_irq_disable(ep
->r8a66597
, ep
->pipenum
);
1588 return free_pipe_config(ep
);
1591 static struct usb_request
*r8a66597_alloc_request(struct usb_ep
*_ep
,
1594 struct r8a66597_request
*req
;
1596 req
= kzalloc(sizeof(struct r8a66597_request
), gfp_flags
);
1600 INIT_LIST_HEAD(&req
->queue
);
1605 static void r8a66597_free_request(struct usb_ep
*_ep
, struct usb_request
*_req
)
1607 struct r8a66597_request
*req
;
1609 req
= container_of(_req
, struct r8a66597_request
, req
);
1613 static int r8a66597_queue(struct usb_ep
*_ep
, struct usb_request
*_req
,
1616 struct r8a66597_ep
*ep
;
1617 struct r8a66597_request
*req
;
1618 unsigned long flags
;
1621 ep
= container_of(_ep
, struct r8a66597_ep
, ep
);
1622 req
= container_of(_req
, struct r8a66597_request
, req
);
1624 if (ep
->r8a66597
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1627 spin_lock_irqsave(&ep
->r8a66597
->lock
, flags
);
1629 if (list_empty(&ep
->queue
))
1632 list_add_tail(&req
->queue
, &ep
->queue
);
1633 req
->req
.actual
= 0;
1634 req
->req
.status
= -EINPROGRESS
;
1636 if (ep
->desc
== NULL
) /* control */
1639 if (request
&& !ep
->busy
)
1640 start_packet(ep
, req
);
1643 spin_unlock_irqrestore(&ep
->r8a66597
->lock
, flags
);
1648 static int r8a66597_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
1650 struct r8a66597_ep
*ep
;
1651 struct r8a66597_request
*req
;
1652 unsigned long flags
;
1654 ep
= container_of(_ep
, struct r8a66597_ep
, ep
);
1655 req
= container_of(_req
, struct r8a66597_request
, req
);
1657 spin_lock_irqsave(&ep
->r8a66597
->lock
, flags
);
1658 if (!list_empty(&ep
->queue
))
1659 transfer_complete(ep
, req
, -ECONNRESET
);
1660 spin_unlock_irqrestore(&ep
->r8a66597
->lock
, flags
);
1665 static int r8a66597_set_halt(struct usb_ep
*_ep
, int value
)
1667 struct r8a66597_ep
*ep
;
1668 struct r8a66597_request
*req
;
1669 unsigned long flags
;
1672 ep
= container_of(_ep
, struct r8a66597_ep
, ep
);
1673 req
= get_request_from_ep(ep
);
1675 spin_lock_irqsave(&ep
->r8a66597
->lock
, flags
);
1676 if (!list_empty(&ep
->queue
)) {
1682 pipe_stall(ep
->r8a66597
, ep
->pipenum
);
1686 pipe_stop(ep
->r8a66597
, ep
->pipenum
);
1690 spin_unlock_irqrestore(&ep
->r8a66597
->lock
, flags
);
1694 static int r8a66597_set_wedge(struct usb_ep
*_ep
)
1696 struct r8a66597_ep
*ep
;
1697 unsigned long flags
;
1699 ep
= container_of(_ep
, struct r8a66597_ep
, ep
);
1701 if (!ep
|| !ep
->desc
)
1704 spin_lock_irqsave(&ep
->r8a66597
->lock
, flags
);
1706 spin_unlock_irqrestore(&ep
->r8a66597
->lock
, flags
);
1708 return usb_ep_set_halt(_ep
);
1711 static void r8a66597_fifo_flush(struct usb_ep
*_ep
)
1713 struct r8a66597_ep
*ep
;
1714 unsigned long flags
;
1716 ep
= container_of(_ep
, struct r8a66597_ep
, ep
);
1717 spin_lock_irqsave(&ep
->r8a66597
->lock
, flags
);
1718 if (list_empty(&ep
->queue
) && !ep
->busy
) {
1719 pipe_stop(ep
->r8a66597
, ep
->pipenum
);
1720 r8a66597_bclr(ep
->r8a66597
, BCLR
, ep
->fifoctr
);
1722 spin_unlock_irqrestore(&ep
->r8a66597
->lock
, flags
);
1725 static struct usb_ep_ops r8a66597_ep_ops
= {
1726 .enable
= r8a66597_enable
,
1727 .disable
= r8a66597_disable
,
1729 .alloc_request
= r8a66597_alloc_request
,
1730 .free_request
= r8a66597_free_request
,
1732 .queue
= r8a66597_queue
,
1733 .dequeue
= r8a66597_dequeue
,
1735 .set_halt
= r8a66597_set_halt
,
1736 .set_wedge
= r8a66597_set_wedge
,
1737 .fifo_flush
= r8a66597_fifo_flush
,
1740 /*-------------------------------------------------------------------------*/
1741 static int r8a66597_start(struct usb_gadget
*gadget
,
1742 struct usb_gadget_driver
*driver
)
1744 struct r8a66597
*r8a66597
= gadget_to_r8a66597(gadget
);
1748 || driver
->speed
!= USB_SPEED_HIGH
1754 /* hook up the driver */
1755 driver
->driver
.bus
= NULL
;
1756 r8a66597
->driver
= driver
;
1757 r8a66597
->gadget
.dev
.driver
= &driver
->driver
;
1759 retval
= device_add(&r8a66597
->gadget
.dev
);
1761 dev_err(r8a66597_to_dev(r8a66597
), "device_add error (%d)\n",
1766 init_controller(r8a66597
);
1767 r8a66597_bset(r8a66597
, VBSE
, INTENB0
);
1768 if (r8a66597_read(r8a66597
, INTSTS0
) & VBSTS
) {
1769 r8a66597_start_xclock(r8a66597
);
1770 /* start vbus sampling */
1771 r8a66597
->old_vbus
= r8a66597_read(r8a66597
,
1773 r8a66597
->scount
= R8A66597_MAX_SAMPLING
;
1774 mod_timer(&r8a66597
->timer
, jiffies
+ msecs_to_jiffies(50));
1780 r8a66597
->driver
= NULL
;
1781 r8a66597
->gadget
.dev
.driver
= NULL
;
1786 static int r8a66597_stop(struct usb_gadget
*gadget
,
1787 struct usb_gadget_driver
*driver
)
1789 struct r8a66597
*r8a66597
= gadget_to_r8a66597(gadget
);
1790 unsigned long flags
;
1792 spin_lock_irqsave(&r8a66597
->lock
, flags
);
1793 r8a66597_bclr(r8a66597
, VBSE
, INTENB0
);
1794 disable_controller(r8a66597
);
1795 spin_unlock_irqrestore(&r8a66597
->lock
, flags
);
1797 device_del(&r8a66597
->gadget
.dev
);
1798 r8a66597
->driver
= NULL
;
1802 /*-------------------------------------------------------------------------*/
1803 static int r8a66597_get_frame(struct usb_gadget
*_gadget
)
1805 struct r8a66597
*r8a66597
= gadget_to_r8a66597(_gadget
);
1806 return r8a66597_read(r8a66597
, FRMNUM
) & 0x03FF;
1809 static int r8a66597_pullup(struct usb_gadget
*gadget
, int is_on
)
1811 struct r8a66597
*r8a66597
= gadget_to_r8a66597(gadget
);
1812 unsigned long flags
;
1814 spin_lock_irqsave(&r8a66597
->lock
, flags
);
1816 r8a66597_bset(r8a66597
, DPRPU
, SYSCFG0
);
1818 r8a66597_bclr(r8a66597
, DPRPU
, SYSCFG0
);
1819 spin_unlock_irqrestore(&r8a66597
->lock
, flags
);
1824 static struct usb_gadget_ops r8a66597_gadget_ops
= {
1825 .get_frame
= r8a66597_get_frame
,
1826 .udc_start
= r8a66597_start
,
1827 .udc_stop
= r8a66597_stop
,
1828 .pullup
= r8a66597_pullup
,
1831 static int __exit
r8a66597_remove(struct platform_device
*pdev
)
1833 struct r8a66597
*r8a66597
= dev_get_drvdata(&pdev
->dev
);
1835 usb_del_gadget_udc(&r8a66597
->gadget
);
1836 del_timer_sync(&r8a66597
->timer
);
1837 iounmap(r8a66597
->reg
);
1838 if (r8a66597
->pdata
->sudmac
)
1839 iounmap(r8a66597
->sudmac_reg
);
1840 free_irq(platform_get_irq(pdev
, 0), r8a66597
);
1841 r8a66597_free_request(&r8a66597
->ep
[0].ep
, r8a66597
->ep0_req
);
1842 #ifdef CONFIG_HAVE_CLK
1843 if (r8a66597
->pdata
->on_chip
) {
1844 clk_disable(r8a66597
->clk
);
1845 clk_put(r8a66597
->clk
);
1852 static void nop_completion(struct usb_ep
*ep
, struct usb_request
*r
)
1856 static int __init
r8a66597_sudmac_ioremap(struct r8a66597
*r8a66597
,
1857 struct platform_device
*pdev
)
1859 struct resource
*res
;
1861 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "sudmac");
1863 dev_err(&pdev
->dev
, "platform_get_resource error(sudmac).\n");
1867 r8a66597
->sudmac_reg
= ioremap(res
->start
, resource_size(res
));
1868 if (r8a66597
->sudmac_reg
== NULL
) {
1869 dev_err(&pdev
->dev
, "ioremap error(sudmac).\n");
1876 static int __init
r8a66597_probe(struct platform_device
*pdev
)
1878 #ifdef CONFIG_HAVE_CLK
1881 struct resource
*res
, *ires
;
1883 void __iomem
*reg
= NULL
;
1884 struct r8a66597
*r8a66597
= NULL
;
1887 unsigned long irq_trigger
;
1889 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1892 dev_err(&pdev
->dev
, "platform_get_resource error.\n");
1896 ires
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1898 irq_trigger
= ires
->flags
& IRQF_TRIGGER_MASK
;
1902 dev_err(&pdev
->dev
, "platform_get_irq error.\n");
1906 reg
= ioremap(res
->start
, resource_size(res
));
1909 dev_err(&pdev
->dev
, "ioremap error.\n");
1913 /* initialize ucd */
1914 r8a66597
= kzalloc(sizeof(struct r8a66597
), GFP_KERNEL
);
1915 if (r8a66597
== NULL
) {
1917 dev_err(&pdev
->dev
, "kzalloc error\n");
1921 spin_lock_init(&r8a66597
->lock
);
1922 dev_set_drvdata(&pdev
->dev
, r8a66597
);
1923 r8a66597
->pdata
= pdev
->dev
.platform_data
;
1924 r8a66597
->irq_sense_low
= irq_trigger
== IRQF_TRIGGER_LOW
;
1926 r8a66597
->gadget
.ops
= &r8a66597_gadget_ops
;
1927 device_initialize(&r8a66597
->gadget
.dev
);
1928 dev_set_name(&r8a66597
->gadget
.dev
, "gadget");
1929 r8a66597
->gadget
.is_dualspeed
= 1;
1930 r8a66597
->gadget
.dev
.parent
= &pdev
->dev
;
1931 r8a66597
->gadget
.dev
.dma_mask
= pdev
->dev
.dma_mask
;
1932 r8a66597
->gadget
.dev
.release
= pdev
->dev
.release
;
1933 r8a66597
->gadget
.name
= udc_name
;
1935 init_timer(&r8a66597
->timer
);
1936 r8a66597
->timer
.function
= r8a66597_timer
;
1937 r8a66597
->timer
.data
= (unsigned long)r8a66597
;
1938 r8a66597
->reg
= reg
;
1940 #ifdef CONFIG_HAVE_CLK
1941 if (r8a66597
->pdata
->on_chip
) {
1942 snprintf(clk_name
, sizeof(clk_name
), "usb%d", pdev
->id
);
1943 r8a66597
->clk
= clk_get(&pdev
->dev
, clk_name
);
1944 if (IS_ERR(r8a66597
->clk
)) {
1945 dev_err(&pdev
->dev
, "cannot get clock \"%s\"\n",
1947 ret
= PTR_ERR(r8a66597
->clk
);
1950 clk_enable(r8a66597
->clk
);
1953 if (r8a66597
->pdata
->sudmac
) {
1954 ret
= r8a66597_sudmac_ioremap(r8a66597
, pdev
);
1959 disable_controller(r8a66597
); /* make sure controller is disabled */
1961 ret
= request_irq(irq
, r8a66597_irq
, IRQF_SHARED
,
1962 udc_name
, r8a66597
);
1964 dev_err(&pdev
->dev
, "request_irq error (%d)\n", ret
);
1968 INIT_LIST_HEAD(&r8a66597
->gadget
.ep_list
);
1969 r8a66597
->gadget
.ep0
= &r8a66597
->ep
[0].ep
;
1970 INIT_LIST_HEAD(&r8a66597
->gadget
.ep0
->ep_list
);
1971 for (i
= 0; i
< R8A66597_MAX_NUM_PIPE
; i
++) {
1972 struct r8a66597_ep
*ep
= &r8a66597
->ep
[i
];
1975 INIT_LIST_HEAD(&r8a66597
->ep
[i
].ep
.ep_list
);
1976 list_add_tail(&r8a66597
->ep
[i
].ep
.ep_list
,
1977 &r8a66597
->gadget
.ep_list
);
1979 ep
->r8a66597
= r8a66597
;
1980 INIT_LIST_HEAD(&ep
->queue
);
1981 ep
->ep
.name
= r8a66597_ep_name
[i
];
1982 ep
->ep
.ops
= &r8a66597_ep_ops
;
1983 ep
->ep
.maxpacket
= 512;
1985 r8a66597
->ep
[0].ep
.maxpacket
= 64;
1986 r8a66597
->ep
[0].pipenum
= 0;
1987 r8a66597
->ep
[0].fifoaddr
= CFIFO
;
1988 r8a66597
->ep
[0].fifosel
= CFIFOSEL
;
1989 r8a66597
->ep
[0].fifoctr
= CFIFOCTR
;
1990 r8a66597
->ep
[0].pipectr
= get_pipectr_addr(0);
1991 r8a66597
->pipenum2ep
[0] = &r8a66597
->ep
[0];
1992 r8a66597
->epaddr2ep
[0] = &r8a66597
->ep
[0];
1994 r8a66597
->ep0_req
= r8a66597_alloc_request(&r8a66597
->ep
[0].ep
,
1996 if (r8a66597
->ep0_req
== NULL
)
1998 r8a66597
->ep0_req
->complete
= nop_completion
;
2000 ret
= usb_add_gadget_udc(&pdev
->dev
, &r8a66597
->gadget
);
2004 dev_info(&pdev
->dev
, "version %s\n", DRIVER_VERSION
);
2008 r8a66597_free_request(&r8a66597
->ep
[0].ep
, r8a66597
->ep0_req
);
2010 free_irq(irq
, r8a66597
);
2012 #ifdef CONFIG_HAVE_CLK
2013 if (r8a66597
->pdata
->on_chip
) {
2014 clk_disable(r8a66597
->clk
);
2015 clk_put(r8a66597
->clk
);
2020 if (r8a66597
->sudmac_reg
)
2021 iounmap(r8a66597
->sudmac_reg
);
2022 if (r8a66597
->ep0_req
)
2023 r8a66597_free_request(&r8a66597
->ep
[0].ep
,
2033 /*-------------------------------------------------------------------------*/
2034 static struct platform_driver r8a66597_driver
= {
2035 .remove
= __exit_p(r8a66597_remove
),
2037 .name
= (char *) udc_name
,
2040 MODULE_ALIAS("platform:r8a66597_udc");
2042 static int __init
r8a66597_udc_init(void)
2044 return platform_driver_probe(&r8a66597_driver
, r8a66597_probe
);
2046 module_init(r8a66597_udc_init
);
2048 static void __exit
r8a66597_udc_cleanup(void)
2050 platform_driver_unregister(&r8a66597_driver
);
2052 module_exit(r8a66597_udc_cleanup
);
2054 MODULE_DESCRIPTION("R8A66597 USB gadget driver");
2055 MODULE_LICENSE("GPL");
2056 MODULE_AUTHOR("Yoshihiro Shimoda");