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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
[linux-btrfs-devel.git] / drivers / staging / bcm / DDRInit.c
blob1c7db81a1ee8554e14581ce68f27f6e5fcea3d0e
1 #include "headers.h"
2
3
4
5 #define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
6 #define MIPS_CLOCK_REG 0x0f000820
7
8 //DDR INIT-133Mhz
9 #define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 //index for 0x0F007000
10 static DDR_SET_NODE asT3_DDRSetting133MHz[]= {// # DPLL Clock Setting
11 {0x0F000800,0x00007212},
12 {0x0f000820,0x07F13FFF},
13 {0x0f000810,0x00000F95},
14 {0x0f000860,0x00000000},
15 {0x0f000880,0x000003DD},
16 // Changed source for X-bar and MIPS clock to APLL
17 {0x0f000840,0x0FFF1B00},
18 {0x0f000870,0x00000002},
19 {0x0F00a044,0x1fffffff},
20 {0x0F00a040,0x1f000000},
21 {0x0F00a084,0x1Cffffff},
22 {0x0F00a080,0x1C000000},
23 {0x0F00a04C,0x0000000C},
24 //Memcontroller Default values
25 {0x0F007000,0x00010001},
26 {0x0F007004,0x01010100},
27 {0x0F007008,0x01000001},
28 {0x0F00700c,0x00000000},
29 {0x0F007010,0x01000000},
30 {0x0F007014,0x01000100},
31 {0x0F007018,0x01000000},
32 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
33 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
34 {0x0F007024,0x02000007},
35 {0x0F007028,0x02020202},
36 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
37 {0x0F007030,0x05000000},
38 {0x0F007034,0x00000003},
39 {0x0F007038,0x110a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
40 {0x0F00703C,0x02101010},//ROB - 0x02101010,//0x02101018},
41 {0x0F007040,0x45751200},//ROB - 0x45751200,//0x450f1200},
42 {0x0F007044,0x110a0d00},//ROB - 0x110a0d00//0x111f0d00
43 {0x0F007048,0x081b0306},
44 {0x0F00704c,0x00000000},
45 {0x0F007050,0x0000001c},
46 {0x0F007054,0x00000000},
47 {0x0F007058,0x00000000},
48 {0x0F00705c,0x00000000},
49 {0x0F007060,0x0010246c},
50 {0x0F007064,0x00000010},
51 {0x0F007068,0x00000000},
52 {0x0F00706c,0x00000001},
53 {0x0F007070,0x00007000},
54 {0x0F007074,0x00000000},
55 {0x0F007078,0x00000000},
56 {0x0F00707C,0x00000000},
57 {0x0F007080,0x00000000},
58 {0x0F007084,0x00000000},
59 //# Enable BW improvement within memory controller
60 {0x0F007094,0x00000104},
61 //# Enable 2 ports within X-bar
62 {0x0F00A000,0x00000016},
63 //# Enable start bit within memory controller
64 {0x0F007018,0x01010000}
65 };
66 //80Mhz
67 #define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 //index for 0x0F007000
68 static DDR_SET_NODE asT3_DDRSetting80MHz[]= {// # DPLL Clock Setting
69 {0x0f000810,0x00000F95},
70 {0x0f000820,0x07f1ffff},
71 {0x0f000860,0x00000000},
72 {0x0f000880,0x000003DD},
73 {0x0F00a044,0x1fffffff},
74 {0x0F00a040,0x1f000000},
75 {0x0F00a084,0x1Cffffff},
76 {0x0F00a080,0x1C000000},
77 {0x0F00a000,0x00000016},
78 {0x0F00a04C,0x0000000C},
79 //Memcontroller Default values
80 {0x0F007000,0x00010001},
81 {0x0F007004,0x01000000},
82 {0x0F007008,0x01000001},
83 {0x0F00700c,0x00000000},
84 {0x0F007010,0x01000000},
85 {0x0F007014,0x01000100},
86 {0x0F007018,0x01000000},
87 {0x0F00701c,0x01020000},
88 {0x0F007020,0x04020107},
89 {0x0F007024,0x00000007},
90 {0x0F007028,0x02020201},
91 {0x0F00702c,0x0204040a},
92 {0x0F007030,0x04000000},
93 {0x0F007034,0x00000002},
94 {0x0F007038,0x1F060200},
95 {0x0F00703C,0x1C22221F},
96 {0x0F007040,0x8A006600},
97 {0x0F007044,0x221a0800},
98 {0x0F007048,0x02690204},
99 {0x0F00704c,0x00000000},
100 {0x0F007050,0x0000001c},
101 {0x0F007054,0x00000000},
102 {0x0F007058,0x00000000},
103 {0x0F00705c,0x00000000},
104 {0x0F007060,0x000A15D6},
105 {0x0F007064,0x0000000A},
106 {0x0F007068,0x00000000},
107 {0x0F00706c,0x00000001},
108 {0x0F007070,0x00004000},
109 {0x0F007074,0x00000000},
110 {0x0F007078,0x00000000},
111 {0x0F00707C,0x00000000},
112 {0x0F007080,0x00000000},
113 {0x0F007084,0x00000000},
114 {0x0F007094,0x00000104},
115 //# Enable start bit within memory controller
116 {0x0F007018,0x01010000}
117 };
118 //100Mhz
119 #define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 //index for 0x0F007000
120 static DDR_SET_NODE asT3_DDRSetting100MHz[]= {// # DPLL Clock Setting
121 {0x0F000800,0x00007008},
122 {0x0f000810,0x00000F95},
123 {0x0f000820,0x07F13E3F},
124 {0x0f000860,0x00000000},
125 {0x0f000880,0x000003DD},
126 // Changed source for X-bar and MIPS clock to APLL
127 //0x0f000840,0x0FFF1800,
128 {0x0f000840,0x0FFF1B00},
129 {0x0f000870,0x00000002},
130 {0x0F00a044,0x1fffffff},
131 {0x0F00a040,0x1f000000},
132 {0x0F00a084,0x1Cffffff},
133 {0x0F00a080,0x1C000000},
134 {0x0F00a04C,0x0000000C},
135 //# Enable 2 ports within X-bar
136 {0x0F00A000,0x00000016},
137 //Memcontroller Default values
138 {0x0F007000,0x00010001},
139 {0x0F007004,0x01010100},
140 {0x0F007008,0x01000001},
141 {0x0F00700c,0x00000000},
142 {0x0F007010,0x01000000},
143 {0x0F007014,0x01000100},
144 {0x0F007018,0x01000000},
145 {0x0F00701c,0x01020001}, // POP - 0x00020000 Normal 0x01020000
146 {0x0F007020,0x04020107},//Normal - 0x04030107 POP - 0x05030107
147 {0x0F007024,0x00000007},
148 {0x0F007028,0x01020201},
149 {0x0F00702c,0x0204040A},
150 {0x0F007030,0x06000000},
151 {0x0F007034,0x00000004},
152 {0x0F007038,0x20080200},
153 {0x0F00703C,0x02030320},
154 {0x0F007040,0x6E7F1200},
155 {0x0F007044,0x01190A00},
156 {0x0F007048,0x06120305},//0x02690204 // 0x06120305
157 {0x0F00704c,0x00000000},
158 {0x0F007050,0x0000001C},
159 {0x0F007054,0x00000000},
160 {0x0F007058,0x00000000},
161 {0x0F00705c,0x00000000},
162 {0x0F007060,0x00082ED6},
163 {0x0F007064,0x0000000A},
164 {0x0F007068,0x00000000},
165 {0x0F00706c,0x00000001},
166 {0x0F007070,0x00005000},
167 {0x0F007074,0x00000000},
168 {0x0F007078,0x00000000},
169 {0x0F00707C,0x00000000},
170 {0x0F007080,0x00000000},
171 {0x0F007084,0x00000000},
172 //# Enable BW improvement within memory controller
173 {0x0F007094,0x00000104},
174 //# Enable start bit within memory controller
175 {0x0F007018,0x01010000}
176 };
177
178 //Net T3B DDR Settings
179 //DDR INIT-133Mhz
180 static DDR_SET_NODE asDPLL_266MHZ[] = {
181 {0x0F000800,0x00007212},
182 {0x0f000820,0x07F13FFF},
183 {0x0f000810,0x00000F95},
184 {0x0f000860,0x00000000},
185 {0x0f000880,0x000003DD},
186 // Changed source for X-bar and MIPS clock to APLL
187 {0x0f000840,0x0FFF1B00},
188 {0x0f000870,0x00000002}
189 };
190
191 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 //index for 0x0F007000
192 static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {// # DPLL Clock Setting
193 {0x0f000810,0x00000F95},
194 {0x0f000810,0x00000F95},
195 {0x0f000810,0x00000F95},
196 {0x0f000820,0x07F13652},
197 {0x0f000840,0x0FFF0800},
198 // Changed source for X-bar and MIPS clock to APLL
199 {0x0f000880,0x000003DD},
200 {0x0f000860,0x00000000},
201 // Changed source for X-bar and MIPS clock to APLL
202 {0x0F00a044,0x1fffffff},
203 {0x0F00a040,0x1f000000},
204 {0x0F00a084,0x1Cffffff},
205 {0x0F00a080,0x1C000000},
206 //# Enable 2 ports within X-bar
207 {0x0F00A000,0x00000016},
208 //Memcontroller Default values
209 {0x0F007000,0x00010001},
210 {0x0F007004,0x01010100},
211 {0x0F007008,0x01000001},
212 {0x0F00700c,0x00000000},
213 {0x0F007010,0x01000000},
214 {0x0F007014,0x01000100},
215 {0x0F007018,0x01000000},
216 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
217 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
218 {0x0F007024,0x02000007},
219 {0x0F007028,0x02020202},
220 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
221 {0x0F007030,0x05000000},
222 {0x0F007034,0x00000003},
223 {0x0F007038,0x130a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
224 {0x0F00703C,0x02101012},//ROB - 0x02101010,//0x02101018},
225 {0x0F007040,0x457D1200},//ROB - 0x45751200,//0x450f1200},
226 {0x0F007044,0x11130d00},//ROB - 0x110a0d00//0x111f0d00
227 {0x0F007048,0x040D0306},
228 {0x0F00704c,0x00000000},
229 {0x0F007050,0x0000001c},
230 {0x0F007054,0x00000000},
231 {0x0F007058,0x00000000},
232 {0x0F00705c,0x00000000},
233 {0x0F007060,0x0010246c},
234 {0x0F007064,0x00000012},
235 {0x0F007068,0x00000000},
236 {0x0F00706c,0x00000001},
237 {0x0F007070,0x00007000},
238 {0x0F007074,0x00000000},
239 {0x0F007078,0x00000000},
240 {0x0F00707C,0x00000000},
241 {0x0F007080,0x00000000},
242 {0x0F007084,0x00000000},
243 //# Enable BW improvement within memory controller
244 {0x0F007094,0x00000104},
245 //# Enable start bit within memory controller
246 {0x0F007018,0x01010000},
247 };
248
249 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 //index for 0x0F007000
250 static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {// # DPLL Clock Setting
251 {0x0f000810,0x00000F95},
252 {0x0f000820,0x07F13FFF},
253 {0x0f000840,0x0FFF1F00},
254 {0x0f000880,0x000003DD},
255 {0x0f000860,0x00000000},
256
257 {0x0F00a044,0x1fffffff},
258 {0x0F00a040,0x1f000000},
259 {0x0F00a084,0x1Cffffff},
260 {0x0F00a080,0x1C000000},
261 {0x0F00a000,0x00000016},
262 //Memcontroller Default values
263 {0x0F007000,0x00010001},
264 {0x0F007004,0x01000000},
265 {0x0F007008,0x01000001},
266 {0x0F00700c,0x00000000},
267 {0x0F007010,0x01000000},
268 {0x0F007014,0x01000100},
269 {0x0F007018,0x01000000},
270 {0x0F00701c,0x01020000},
271 {0x0F007020,0x04020107},
272 {0x0F007024,0x00000007},
273 {0x0F007028,0x02020201},
274 {0x0F00702c,0x0204040a},
275 {0x0F007030,0x04000000},
276 {0x0F007034,0x02000002},
277 {0x0F007038,0x1F060202},
278 {0x0F00703C,0x1C22221F},
279 {0x0F007040,0x8A006600},
280 {0x0F007044,0x221a0800},
281 {0x0F007048,0x02690204},
282 {0x0F00704c,0x00000000},
283 {0x0F007050,0x0100001c},
284 {0x0F007054,0x00000000},
285 {0x0F007058,0x00000000},
286 {0x0F00705c,0x00000000},
287 {0x0F007060,0x000A15D6},
288 {0x0F007064,0x0000000A},
289 {0x0F007068,0x00000000},
290 {0x0F00706c,0x00000001},
291 {0x0F007070,0x00004000},
292 {0x0F007074,0x00000000},
293 {0x0F007078,0x00000000},
294 {0x0F00707C,0x00000000},
295 {0x0F007080,0x00000000},
296 {0x0F007084,0x00000000},
297 {0x0F007094,0x00000104},
298 //# Enable start bit within memory controller
299 {0x0F007018,0x01010000}
300 };
301
302 //100Mhz
303 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 //index for 0x0F007000
304 static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {// # DPLL Clock Setting
305 {0x0f000810,0x00000F95},
306 {0x0f000820,0x07F1369B},
307 {0x0f000840,0x0FFF0800},
308 {0x0f000880,0x000003DD},
309 {0x0f000860,0x00000000},
310 {0x0F00a044,0x1fffffff},
311 {0x0F00a040,0x1f000000},
312 {0x0F00a084,0x1Cffffff},
313 {0x0F00a080,0x1C000000},
314 //# Enable 2 ports within X-bar
315 {0x0F00A000,0x00000016},
316 //Memcontroller Default values
317 {0x0F007000,0x00010001},
318 {0x0F007004,0x01010100},
319 {0x0F007008,0x01000001},
320 {0x0F00700c,0x00000000},
321 {0x0F007010,0x01000000},
322 {0x0F007014,0x01000100},
323 {0x0F007018,0x01000000},
324 {0x0F00701c,0x01020000}, // POP - 0x00020000 Normal 0x01020000
325 {0x0F007020,0x04020107},//Normal - 0x04030107 POP - 0x05030107
326 {0x0F007024,0x00000007},
327 {0x0F007028,0x01020201},
328 {0x0F00702c,0x0204040A},
329 {0x0F007030,0x06000000},
330 {0x0F007034,0x02000004},
331 {0x0F007038,0x20080200},
332 {0x0F00703C,0x02030320},
333 {0x0F007040,0x6E7F1200},
334 {0x0F007044,0x01190A00},
335 {0x0F007048,0x06120305},//0x02690204 // 0x06120305
336 {0x0F00704c,0x00000000},
337 {0x0F007050,0x0100001C},
338 {0x0F007054,0x00000000},
339 {0x0F007058,0x00000000},
340 {0x0F00705c,0x00000000},
341 {0x0F007060,0x00082ED6},
342 {0x0F007064,0x0000000A},
343 {0x0F007068,0x00000000},
344 {0x0F00706c,0x00000001},
345 {0x0F007070,0x00005000},
346 {0x0F007074,0x00000000},
347 {0x0F007078,0x00000000},
348 {0x0F00707C,0x00000000},
349 {0x0F007080,0x00000000},
350 {0x0F007084,0x00000000},
351 //# Enable BW improvement within memory controller
352 {0x0F007094,0x00000104},
353 //# Enable start bit within memory controller
354 {0x0F007018,0x01010000}
355 };
356
357
358 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 //index for 0x0F007000
359 static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {// # DPLL Clock Setting
360 {0x0f000820,0x03F1365B},
361 {0x0f000810,0x00002F95},
362 {0x0f000880,0x000003DD},
363 // Changed source for X-bar and MIPS clock to APLL
364 {0x0f000840,0x0FFF0000},
365 {0x0f000860,0x00000000},
366 {0x0F00a044,0x1fffffff},
367 {0x0F00a040,0x1f000000},
368 {0x0F00a084,0x1Cffffff},
369 {0x0F00a080,0x1C000000},
370 {0x0F00A000,0x00000016},
371 //Memcontroller Default values
372 {0x0F007000,0x00010001},
373 {0x0F007004,0x01010100},
374 {0x0F007008,0x01000001},
375 {0x0F00700c,0x00000000},
376 {0x0F007010,0x01000000},
377 {0x0F007014,0x01000100},
378 {0x0F007018,0x01000000},
379 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
380 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
381 {0x0F007024,0x02000007},
382 {0x0F007028,0x02020200},
383 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
384 {0x0F007030,0x05000000},
385 {0x0F007034,0x00000003},
386 {0x0F007038,0x200a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
387 {0x0F00703C,0x02101020},//ROB - 0x02101010,//0x02101018,
388 {0x0F007040,0x45711200},//ROB - 0x45751200,//0x450f1200,
389 {0x0F007044,0x110D0D00},//ROB - 0x110a0d00//0x111f0d00
390 {0x0F007048,0x04080306},
391 {0x0F00704c,0x00000000},
392 {0x0F007050,0x0100001c},
393 {0x0F007054,0x00000000},
394 {0x0F007058,0x00000000},
395 {0x0F00705c,0x00000000},
396 {0x0F007060,0x0010245F},
397 {0x0F007064,0x00000010},
398 {0x0F007068,0x00000000},
399 {0x0F00706c,0x00000001},
400 {0x0F007070,0x00007000},
401 {0x0F007074,0x00000000},
402 {0x0F007078,0x00000000},
403 {0x0F00707C,0x00000000},
404 {0x0F007080,0x00000000},
405 {0x0F007084,0x00000000},
406 {0x0F007088,0x01000001},
407 {0x0F00708c,0x00000101},
408 {0x0F007090,0x00000000},
409 //# Enable BW improvement within memory controller
410 {0x0F007094,0x00040000},
411 {0x0F007098,0x00000000},
412 {0x0F0070c8,0x00000104},
413 //# Enable 2 ports within X-bar
414 //# Enable start bit within memory controller
415 {0x0F007018,0x01010000}
416 };
417
418 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 //index for 0x0F007000
419 static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {// # DPLL Clock Setting
420 {0x0f000810,0x00002F95},
421 {0x0f000820,0x03F1369B},
422 {0x0f000840,0x0fff0000},
423 {0x0f000860,0x00000000},
424 {0x0f000880,0x000003DD},
425 // Changed source for X-bar and MIPS clock to APLL
426 {0x0f000840,0x0FFF0000},
427 {0x0F00a044,0x1fffffff},
428 {0x0F00a040,0x1f000000},
429 {0x0F00a084,0x1Cffffff},
430 {0x0F00a080,0x1C000000},
431 //Memcontroller Default values
432 {0x0F007000,0x00010001},
433 {0x0F007004,0x01010100},
434 {0x0F007008,0x01000001},
435 {0x0F00700c,0x00000000},
436 {0x0F007010,0x01000000},
437 {0x0F007014,0x01000100},
438 {0x0F007018,0x01000000},
439 {0x0F00701c,0x01020000},// POP - 0x00020001 Normal 0x01020001
440 {0x0F007020,0x04020107}, //Normal - 0x04030107 POP - 0x05030107
441 {0x0F007024,0x00000007},
442 {0x0F007028,0x01020200},
443 {0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
444 {0x0F007030,0x06000000},
445 {0x0F007034,0x00000004},
446 {0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
447 {0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
448 {0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
449 {0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
450 {0x0F007048,0x03000305},
451 {0x0F00704c,0x00000000},
452 {0x0F007050,0x0100001c},
453 {0x0F007054,0x00000000},
454 {0x0F007058,0x00000000},
455 {0x0F00705c,0x00000000},
456 {0x0F007060,0x00082ED6},
457 {0x0F007064,0x0000000A},
458 {0x0F007068,0x00000000},
459 {0x0F00706c,0x00000001},
460 {0x0F007070,0x00005000},
461 {0x0F007074,0x00000000},
462 {0x0F007078,0x00000000},
463 {0x0F00707C,0x00000000},
464 {0x0F007080,0x00000000},
465 {0x0F007084,0x00000000},
466 {0x0F007088,0x01000001},
467 {0x0F00708c,0x00000101},
468 {0x0F007090,0x00000000},
469 {0x0F007094,0x00010000},
470 {0x0F007098,0x00000000},
471 {0x0F0070C8,0x00000104},
472 //# Enable 2 ports within X-bar
473 {0x0F00A000,0x00000016},
474 //# Enable start bit within memory controller
475 {0x0F007018,0x01010000}
476 };
477
478 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 //index for 0x0F007000
479 static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {// # DPLL Clock Setting
480 {0x0f000820,0x07F13FFF},
481 {0x0f000810,0x00002F95},
482 {0x0f000860,0x00000000},
483 {0x0f000880,0x000003DD},
484 {0x0f000840,0x0FFF1F00},
485 {0x0F00a044,0x1fffffff},
486 {0x0F00a040,0x1f000000},
487 {0x0F00a084,0x1Cffffff},
488 {0x0F00a080,0x1C000000},
489 {0x0F00A000,0x00000016},
490 {0x0f007000,0x00010001},
491 {0x0f007004,0x01000000},
492 {0x0f007008,0x01000001},
493 {0x0f00700c,0x00000000},
494 {0x0f007010,0x01000000},
495 {0x0f007014,0x01000100},
496 {0x0f007018,0x01000000},
497 {0x0f00701c,0x01020000},
498 {0x0f007020,0x04020107},
499 {0x0f007024,0x00000007},
500 {0x0f007028,0x02020200},
501 {0x0f00702c,0x0204040a},
502 {0x0f007030,0x04000000},
503 {0x0f007034,0x00000002},
504 {0x0f007038,0x1d060200},
505 {0x0f00703c,0x1c22221d},
506 {0x0f007040,0x8A116600},
507 {0x0f007044,0x222d0800},
508 {0x0f007048,0x02690204},
509 {0x0f00704c,0x00000000},
510 {0x0f007050,0x0100001c},
511 {0x0f007054,0x00000000},
512 {0x0f007058,0x00000000},
513 {0x0f00705c,0x00000000},
514 {0x0f007060,0x000A15D6},
515 {0x0f007064,0x0000000A},
516 {0x0f007068,0x00000000},
517 {0x0f00706c,0x00000001},
518 {0x0f007070,0x00004000},
519 {0x0f007074,0x00000000},
520 {0x0f007078,0x00000000},
521 {0x0f00707c,0x00000000},
522 {0x0f007080,0x00000000},
523 {0x0f007084,0x00000000},
524 {0x0f007088,0x01000001},
525 {0x0f00708c,0x00000101},
526 {0x0f007090,0x00000000},
527 {0x0f007094,0x00010000},
528 {0x0f007098,0x00000000},
529 {0x0F0070C8,0x00000104},
530 {0x0F007018,0x01010000}
531 };
532
533
534
535
536 ///T3 LP-B (UMA-B)
537
538 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 //index for 0x0F007000
539 static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {// # DPLL Clock Setting
540
541 {0x0f000820,0x03F137DB},
542 {0x0f000810,0x01842795},
543 {0x0f000860,0x00000000},
544 {0x0f000880,0x000003DD},
545 {0x0f000840,0x0FFF0400},
546 {0x0F00a044,0x1fffffff},
547 {0x0F00a040,0x1f000000},
548 {0x0f003050,0x00000021},//this is flash/eeprom clock divisor which set the flash clock to 20 MHz
549 {0x0F00a084,0x1Cffffff},//Now dump from her in internal memory
550 {0x0F00a080,0x1C000000},
551 {0x0F00A000,0x00000016},
552 {0x0f007000,0x00010001},
553 {0x0f007004,0x01000001},
554 {0x0f007008,0x01000101},
555 {0x0f00700c,0x00000000},
556 {0x0f007010,0x01000100},
557 {0x0f007014,0x01000100},
558 {0x0f007018,0x01000000},
559 {0x0f00701c,0x01020000},
560 {0x0f007020,0x04030107},
561 {0x0f007024,0x02000007},
562 {0x0f007028,0x02020200},
563 {0x0f00702c,0x0206060a},
564 {0x0f007030,0x050d0d00},
565 {0x0f007034,0x00000003},
566 {0x0f007038,0x170a0200},
567 {0x0f00703c,0x02101012},
568 {0x0f007040,0x45161200},
569 {0x0f007044,0x11250c00},
570 {0x0f007048,0x04da0307},
571 {0x0f00704c,0x00000000},
572 {0x0f007050,0x0000001c},
573 {0x0f007054,0x00000000},
574 {0x0f007058,0x00000000},
575 {0x0f00705c,0x00000000},
576 {0x0f007060,0x00142bb6},
577 {0x0f007064,0x20430014},
578 {0x0f007068,0x00000000},
579 {0x0f00706c,0x00000001},
580 {0x0f007070,0x00009000},
581 {0x0f007074,0x00000000},
582 {0x0f007078,0x00000000},
583 {0x0f00707c,0x00000000},
584 {0x0f007080,0x00000000},
585 {0x0f007084,0x00000000},
586 {0x0f007088,0x01000001},
587 {0x0f00708c,0x00000101},
588 {0x0f007090,0x00000000},
589 {0x0f007094,0x00040000},
590 {0x0f007098,0x00000000},
591 {0x0F0070C8,0x00000104},
592 {0x0F007018,0x01010000}
593 };
594
595
596 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 //index for 0x0F007000
597 static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {// # DPLL Clock Setting
598 {0x0f000820,0x03F1365B},
599 {0x0f000810,0x00002F95},
600 {0x0f000880,0x000003DD},
601 // Changed source for X-bar and MIPS clock to APLL
602 {0x0f000840,0x0FFF0000},
603 {0x0f000860,0x00000000},
604 {0x0F00a044,0x1fffffff},
605 {0x0F00a040,0x1f000000},
606 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
607 {0x0F00a084,0x1Cffffff},//dump from here in internal memory
608 {0x0F00a080,0x1C000000},
609 {0x0F00A000,0x00000016},
610 //Memcontroller Default values
611 {0x0F007000,0x00010001},
612 {0x0F007004,0x01010100},
613 {0x0F007008,0x01000001},
614 {0x0F00700c,0x00000000},
615 {0x0F007010,0x01000000},
616 {0x0F007014,0x01000100},
617 {0x0F007018,0x01000000},
618 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
619 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
620 {0x0F007024,0x02000007},
621 {0x0F007028,0x02020200},
622 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
623 {0x0F007030,0x05000000},
624 {0x0F007034,0x00000003},
625 {0x0F007038,0x190a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
626 {0x0F00703C,0x02101017},//ROB - 0x02101010,//0x02101018,
627 {0x0F007040,0x45171200},//ROB - 0x45751200,//0x450f1200,
628 {0x0F007044,0x11290D00},//ROB - 0x110a0d00//0x111f0d00
629 {0x0F007048,0x04080306},
630 {0x0F00704c,0x00000000},
631 {0x0F007050,0x0100001c},
632 {0x0F007054,0x00000000},
633 {0x0F007058,0x00000000},
634 {0x0F00705c,0x00000000},
635 {0x0F007060,0x0010245F},
636 {0x0F007064,0x00000010},
637 {0x0F007068,0x00000000},
638 {0x0F00706c,0x00000001},
639 {0x0F007070,0x00007000},
640 {0x0F007074,0x00000000},
641 {0x0F007078,0x00000000},
642 {0x0F00707C,0x00000000},
643 {0x0F007080,0x00000000},
644 {0x0F007084,0x00000000},
645 {0x0F007088,0x01000001},
646 {0x0F00708c,0x00000101},
647 {0x0F007090,0x00000000},
648 //# Enable BW improvement within memory controller
649 {0x0F007094,0x00040000},
650 {0x0F007098,0x00000000},
651 {0x0F0070c8,0x00000104},
652 //# Enable 2 ports within X-bar
653 //# Enable start bit within memory controller
654 {0x0F007018,0x01010000}
655 };
656
657 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 //index for 0x0F007000
658 static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {// # DPLL Clock Setting
659 {0x0f000810,0x00002F95},
660 {0x0f000820,0x03F1369B},
661 {0x0f000840,0x0fff0000},
662 {0x0f000860,0x00000000},
663 {0x0f000880,0x000003DD},
664 // Changed source for X-bar and MIPS clock to APLL
665 {0x0f000840,0x0FFF0000},
666 {0x0F00a044,0x1fffffff},
667 {0x0F00a040,0x1f000000},
668 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
669 {0x0F00a084,0x1Cffffff}, //dump from here in internal memory
670 {0x0F00a080,0x1C000000},
671 //Memcontroller Default values
672 {0x0F007000,0x00010001},
673 {0x0F007004,0x01010100},
674 {0x0F007008,0x01000001},
675 {0x0F00700c,0x00000000},
676 {0x0F007010,0x01000000},
677 {0x0F007014,0x01000100},
678 {0x0F007018,0x01000000},
679 {0x0F00701c,0x01020000},// POP - 0x00020001 Normal 0x01020001
680 {0x0F007020,0x04020107}, //Normal - 0x04030107 POP - 0x05030107
681 {0x0F007024,0x00000007},
682 {0x0F007028,0x01020200},
683 {0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
684 {0x0F007030,0x06000000},
685 {0x0F007034,0x00000004},
686 {0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
687 {0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
688 {0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
689 {0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
690 {0x0F007048,0x03000305},
691 {0x0F00704c,0x00000000},
692 {0x0F007050,0x0100001c},
693 {0x0F007054,0x00000000},
694 {0x0F007058,0x00000000},
695 {0x0F00705c,0x00000000},
696 {0x0F007060,0x00082ED6},
697 {0x0F007064,0x0000000A},
698 {0x0F007068,0x00000000},
699 {0x0F00706c,0x00000001},
700 {0x0F007070,0x00005000},
701 {0x0F007074,0x00000000},
702 {0x0F007078,0x00000000},
703 {0x0F00707C,0x00000000},
704 {0x0F007080,0x00000000},
705 {0x0F007084,0x00000000},
706 {0x0F007088,0x01000001},
707 {0x0F00708c,0x00000101},
708 {0x0F007090,0x00000000},
709 {0x0F007094,0x00010000},
710 {0x0F007098,0x00000000},
711 {0x0F0070C8,0x00000104},
712 //# Enable 2 ports within X-bar
713 {0x0F00A000,0x00000016},
714 //# Enable start bit within memory controller
715 {0x0F007018,0x01010000}
716 };
717
718 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 //index for 0x0F007000
719 static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {// # DPLL Clock Setting
720 {0x0f000820,0x07F13FFF},
721 {0x0f000810,0x00002F95},
722 {0x0f000860,0x00000000},
723 {0x0f000880,0x000003DD},
724 {0x0f000840,0x0FFF1F00},
725 {0x0F00a044,0x1fffffff},
726 {0x0F00a040,0x1f000000},
727 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
728 {0x0F00a084,0x1Cffffff},// dump from here in internal memory
729 {0x0F00a080,0x1C000000},
730 {0x0F00A000,0x00000016},
731 {0x0f007000,0x00010001},
732 {0x0f007004,0x01000000},
733 {0x0f007008,0x01000001},
734 {0x0f00700c,0x00000000},
735 {0x0f007010,0x01000000},
736 {0x0f007014,0x01000100},
737 {0x0f007018,0x01000000},
738 {0x0f00701c,0x01020000},
739 {0x0f007020,0x04020107},
740 {0x0f007024,0x00000007},
741 {0x0f007028,0x02020200},
742 {0x0f00702c,0x0204040a},
743 {0x0f007030,0x04000000},
744 {0x0f007034,0x00000002},
745 {0x0f007038,0x1d060200},
746 {0x0f00703c,0x1c22221d},
747 {0x0f007040,0x8A116600},
748 {0x0f007044,0x222d0800},
749 {0x0f007048,0x02690204},
750 {0x0f00704c,0x00000000},
751 {0x0f007050,0x0100001c},
752 {0x0f007054,0x00000000},
753 {0x0f007058,0x00000000},
754 {0x0f00705c,0x00000000},
755 {0x0f007060,0x000A15D6},
756 {0x0f007064,0x0000000A},
757 {0x0f007068,0x00000000},
758 {0x0f00706c,0x00000001},
759 {0x0f007070,0x00004000},
760 {0x0f007074,0x00000000},
761 {0x0f007078,0x00000000},
762 {0x0f00707c,0x00000000},
763 {0x0f007080,0x00000000},
764 {0x0f007084,0x00000000},
765 {0x0f007088,0x01000001},
766 {0x0f00708c,0x00000101},
767 {0x0f007090,0x00000000},
768 {0x0f007094,0x00010000},
769 {0x0f007098,0x00000000},
770 {0x0F0070C8,0x00000104},
771 {0x0F007018,0x01010000}
772 };
773
774
775 int ddr_init(MINI_ADAPTER *Adapter)
776 {
777 PDDR_SETTING psDDRSetting=NULL;
778 ULONG RegCount=0;
779 UINT value = 0;
780 UINT uiResetValue = 0;
781 UINT uiClockSetting = 0;
782 int retval = STATUS_SUCCESS;
783
784 switch (Adapter->chip_id)
785 {
786 case 0xbece3200:
787 switch (Adapter->DDRSetting)
788 {
789 case DDR_80_MHZ:
790 psDDRSetting=asT3LP_DDRSetting80MHz;
791 RegCount=(sizeof(asT3LP_DDRSetting80MHz)/
792 sizeof(DDR_SETTING));
793 break;
794 case DDR_100_MHZ:
795 psDDRSetting=asT3LP_DDRSetting100MHz;
796 RegCount=(sizeof(asT3LP_DDRSetting100MHz)/
797 sizeof(DDR_SETTING));
798 break;
799 case DDR_133_MHZ:
800 psDDRSetting=asT3LP_DDRSetting133MHz;
801 RegCount=(sizeof(asT3LP_DDRSetting133MHz)/
802 sizeof(DDR_SETTING));
803 if(Adapter->bMipsConfig == MIPS_200_MHZ)
804 {
805 uiClockSetting = 0x03F13652;
806 }
807 else
808 {
809 uiClockSetting = 0x03F1365B;
810 }
811 break;
812 default:
813 return -EINVAL;
814 }
815
816 break;
817 case T3LPB:
818 case BCS220_2:
819 case BCS220_2BC:
820 case BCS250_BC:
821 case BCS220_3 :
822 /* Set bit 2 and bit 6 to 1 for BBIC 2mA drive
823 * (please check current value and additionally set these bits)
824 */
825 if( (Adapter->chip_id != BCS220_2) &&
826 (Adapter->chip_id != BCS220_2BC) &&
827 (Adapter->chip_id != BCS220_3) )
828 {
829 retval= rdmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
830 if(retval < 0) {
831 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
832 return retval;
833 }
834 uiResetValue |= 0x44;
835 retval = wrmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
836 if(retval < 0) {
837 BCM_DEBUG_PRINT(Adapter,CMHOST, WRM, DBG_LVL_ALL, "%s:%d WRM failed\n", __FUNCTION__, __LINE__);
838 return retval;
839 }
840 }
841 switch(Adapter->DDRSetting)
842 {
843
844
845
846 case DDR_80_MHZ:
847 psDDRSetting = asT3LPB_DDRSetting80MHz;
848 RegCount=(sizeof(asT3B_DDRSetting80MHz)/
849 sizeof(DDR_SETTING));
850 break;
851 case DDR_100_MHZ:
852 psDDRSetting=asT3LPB_DDRSetting100MHz;
853 RegCount=(sizeof(asT3B_DDRSetting100MHz)/
854 sizeof(DDR_SETTING));
855 break;
856 case DDR_133_MHZ:
857 psDDRSetting = asT3LPB_DDRSetting133MHz;
858 RegCount=(sizeof(asT3B_DDRSetting133MHz)/
859 sizeof(DDR_SETTING));
860
861 if(Adapter->bMipsConfig == MIPS_200_MHZ)
862 {
863 uiClockSetting = 0x03F13652;
864 }
865 else
866 {
867 uiClockSetting = 0x03F1365B;
868 }
869 break;
870
871 case DDR_160_MHZ:
872 psDDRSetting = asT3LPB_DDRSetting160MHz;
873 RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SETTING);
874
875 if(Adapter->bMipsConfig == MIPS_200_MHZ)
876 {
877 uiClockSetting = 0x03F137D2;
878 }
879 else
880 {
881 uiClockSetting = 0x03F137DB;
882 }
883 }
884 break;
885
886 case 0xbece0110:
887 case 0xbece0120:
888 case 0xbece0121:
889 case 0xbece0130:
890 case 0xbece0300:
891 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "DDR Setting: %x\n", Adapter->DDRSetting);
892 switch (Adapter->DDRSetting)
893 {
894 case DDR_80_MHZ:
895 psDDRSetting = asT3_DDRSetting80MHz;
896 RegCount = (sizeof(asT3_DDRSetting80MHz)/
897 sizeof(DDR_SETTING));
898 break;
899 case DDR_100_MHZ:
900 psDDRSetting = asT3_DDRSetting100MHz;
901 RegCount = (sizeof(asT3_DDRSetting100MHz)/
902 sizeof(DDR_SETTING));
903 break;
904 case DDR_133_MHZ:
905 psDDRSetting = asT3_DDRSetting133MHz;
906 RegCount = (sizeof(asT3_DDRSetting133MHz)/
907 sizeof(DDR_SETTING));
908 break;
909 default:
910 return -EINVAL;
911 }
912 case 0xbece0310:
913 {
914 switch (Adapter->DDRSetting)
915 {
916 case DDR_80_MHZ:
917 psDDRSetting = asT3B_DDRSetting80MHz;
918 RegCount=(sizeof(asT3B_DDRSetting80MHz)/
919 sizeof(DDR_SETTING));
920 break;
921 case DDR_100_MHZ:
922 psDDRSetting=asT3B_DDRSetting100MHz;
923 RegCount=(sizeof(asT3B_DDRSetting100MHz)/
924 sizeof(DDR_SETTING));
925 break;
926 case DDR_133_MHZ:
927
928 if(Adapter->bDPLLConfig == PLL_266_MHZ)//266Mhz PLL selected.
929 {
930 memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
931 sizeof(asDPLL_266MHZ));
932 psDDRSetting = asT3B_DDRSetting133MHz;
933 RegCount=(sizeof(asT3B_DDRSetting133MHz)/
934 sizeof(DDR_SETTING));
935 }
936 else
937 {
938 psDDRSetting = asT3B_DDRSetting133MHz;
939 RegCount=(sizeof(asT3B_DDRSetting133MHz)/
940 sizeof(DDR_SETTING));
941 if(Adapter->bMipsConfig == MIPS_200_MHZ)
942 {
943 uiClockSetting = 0x07F13652;
944 }
945 else
946 {
947 uiClockSetting = 0x07F1365B;
948 }
949 }
950 break;
951 default:
952 return -EINVAL;
953 }
954 break;
955
956 }
957 default:
958 return -EINVAL;
959 }
960
961 value=0;
962 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "Register Count is =%lu\n", RegCount);
963 while(RegCount && !retval)
964 {
965 if(uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
966 {
967 value = uiClockSetting;
968 }
969 else
970 {
971 value = psDDRSetting->ulRegValue;
972 }
973 retval = wrmalt(Adapter, psDDRSetting->ulRegAddress, &value, sizeof(value));
974 if(STATUS_SUCCESS != retval) {
975 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
976 break;
977 }
978
979 RegCount--;
980 psDDRSetting++;
981 }
982
983 if(Adapter->chip_id >= 0xbece3300 )
984 {
985
986 mdelay(3);
987 if( (Adapter->chip_id != BCS220_2)&&
988 (Adapter->chip_id != BCS220_2BC)&&
989 (Adapter->chip_id != BCS220_3))
990 {
991 /* drive MDDR to half in case of UMA-B: */
992 uiResetValue = 0x01010001;
993 retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
994 if(retval < 0) {
995 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
996 return retval;
997 }
998 uiResetValue = 0x00040020;
999 retval = wrmalt(Adapter, (UINT)0x0F007094, &uiResetValue, sizeof(uiResetValue));
1000 if(retval < 0) {
1001 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1002 return retval;
1003 }
1004 uiResetValue = 0x01020101;
1005 retval = wrmalt(Adapter, (UINT)0x0F00701c, &uiResetValue, sizeof(uiResetValue));
1006 if(retval < 0) {
1007 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1008 return retval;
1009 }
1010 uiResetValue = 0x01010000;
1011 retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
1012 if(retval < 0) {
1013 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1014 return retval;
1015 }
1016 }
1017 mdelay(3);
1018
1019 /* DC/DC standby change...
1020 * This is to be done only for Hybrid PMU mode.
1021 * with the current h/w there is no way to detect this.
1022 * and since we dont have internal PMU lets do it under UMA-B chip id.
1023 * we will change this when we will have internal PMU.
1024 */
1025 if(Adapter->PmuMode == HYBRID_MODE_7C)
1026 {
1027 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1028 if(retval < 0) {
1029 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1030 return retval;
1031 }
1032 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1033 if(retval < 0) {
1034 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1035 return retval;
1036 }
1037 uiResetValue = 0x1322a8;
1038 retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
1039 if(retval < 0) {
1040 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1041 return retval;
1042 }
1043 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1044 if(retval < 0) {
1045 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1046 return retval;
1047 }
1048 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1049 if(retval < 0) {
1050 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1051 return retval;
1052 }
1053 uiResetValue = 0x132296;
1054 retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
1055 if(retval < 0) {
1056 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1057 return retval;
1058 }
1059 }
1060 else if(Adapter->PmuMode == HYBRID_MODE_6 )
1061 {
1062
1063 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1064 if(retval < 0) {
1065 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1066 return retval;
1067 }
1068 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1069 if(retval < 0) {
1070 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1071 return retval;
1072 }
1073 uiResetValue = 0x6003229a;
1074 retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
1075 if(retval < 0) {
1076 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1077 return retval;
1078 }
1079 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1080 if(retval < 0) {
1081 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1082 return retval;
1083 }
1084 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1085 if(retval < 0) {
1086 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1087 return retval;
1088 }
1089 uiResetValue = 0x1322a8;
1090 retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
1091 if(retval < 0) {
1092 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1093 return retval;
1094 }
1095 }
1096
1097 }
1098 Adapter->bDDRInitDone = TRUE;
1099 return retval;
1100 }
1101
1102 int download_ddr_settings(PMINI_ADAPTER Adapter)
1103 {
1104 PDDR_SET_NODE psDDRSetting=NULL;
1105 ULONG RegCount=0;
1106 unsigned long ul_ddr_setting_load_addr = DDR_DUMP_INTERNAL_DEVICE_MEMORY;
1107 UINT value = 0;
1108 int retval = STATUS_SUCCESS;
1109 BOOLEAN bOverrideSelfRefresh = FALSE;
1110
1111 switch (Adapter->chip_id)
1112 {
1113 case 0xbece3200:
1114 switch (Adapter->DDRSetting)
1115 {
1116 case DDR_80_MHZ:
1117 psDDRSetting = asT3LP_DDRSetting80MHz;
1118 RegCount = (sizeof(asT3LP_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1119 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1120 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1121 break;
1122 case DDR_100_MHZ:
1123 psDDRSetting = asT3LP_DDRSetting100MHz;
1124 RegCount = (sizeof(asT3LP_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1125 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1126 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1127 break;
1128 case DDR_133_MHZ:
1129 bOverrideSelfRefresh = TRUE;
1130 psDDRSetting = asT3LP_DDRSetting133MHz;
1131 RegCount = (sizeof(asT3LP_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1132 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1133 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1134 break;
1135 default:
1136 return -EINVAL;
1137 }
1138 break;
1139
1140 case T3LPB:
1141 case BCS220_2:
1142 case BCS220_2BC:
1143 case BCS250_BC:
1144 case BCS220_3 :
1145 switch (Adapter->DDRSetting)
1146 {
1147 case DDR_80_MHZ:
1148 psDDRSetting = asT3LPB_DDRSetting80MHz;
1149 RegCount=(sizeof(asT3LPB_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1150 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1151 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1152 break;
1153 case DDR_100_MHZ:
1154 psDDRSetting = asT3LPB_DDRSetting100MHz;
1155 RegCount = (sizeof(asT3LPB_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1156 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1157 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1158 break;
1159 case DDR_133_MHZ:
1160 bOverrideSelfRefresh = TRUE;
1161 psDDRSetting = asT3LPB_DDRSetting133MHz;
1162 RegCount = (sizeof(asT3LPB_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1163 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1164 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1165 break;
1166
1167 case DDR_160_MHZ:
1168 bOverrideSelfRefresh = TRUE;
1169 psDDRSetting = asT3LPB_DDRSetting160MHz;
1170 RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SET_NODE);
1171 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1172 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1173
1174 break;
1175 default:
1176 return -EINVAL;
1177 }
1178 break;
1179 case 0xbece0300:
1180 switch (Adapter->DDRSetting)
1181 {
1182 case DDR_80_MHZ:
1183 psDDRSetting = asT3_DDRSetting80MHz;
1184 RegCount = (sizeof(asT3_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1185 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1186 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1187 break;
1188 case DDR_100_MHZ:
1189 psDDRSetting = asT3_DDRSetting100MHz;
1190 RegCount = (sizeof(asT3_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1191 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1192 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1193 break;
1194 case DDR_133_MHZ:
1195 psDDRSetting = asT3_DDRSetting133MHz;
1196 RegCount = (sizeof(asT3_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1197 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1198 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1199 break;
1200 default:
1201 return -EINVAL;
1202 }
1203 break;
1204 case 0xbece0310:
1205 {
1206 switch (Adapter->DDRSetting)
1207 {
1208 case DDR_80_MHZ:
1209 psDDRSetting = asT3B_DDRSetting80MHz;
1210 RegCount = (sizeof(asT3B_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1211 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1212 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1213 break;
1214 case DDR_100_MHZ:
1215 psDDRSetting = asT3B_DDRSetting100MHz;
1216 RegCount = (sizeof(asT3B_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1217 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1218 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1219 break;
1220 case DDR_133_MHZ:
1221 bOverrideSelfRefresh = TRUE;
1222 psDDRSetting = asT3B_DDRSetting133MHz;
1223 RegCount = (sizeof(asT3B_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1224 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1225 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1226 break;
1227 }
1228 break;
1229 }
1230 default:
1231 return -EINVAL;
1232 }
1233 //total number of Register that has to be dumped
1234 value =RegCount ;
1235 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1236 if(retval)
1237 {
1238 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1239
1240 return retval;
1241 }
1242 ul_ddr_setting_load_addr+=sizeof(ULONG);
1243 /*signature */
1244 value =(0x1d1e0dd0);
1245 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1246 if(retval)
1247 {
1248 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1249 return retval;
1250 }
1251
1252 ul_ddr_setting_load_addr+=sizeof(ULONG);
1253 RegCount*=(sizeof(DDR_SETTING)/sizeof(ULONG));
1254
1255 while(RegCount && !retval)
1256 {
1257 value = psDDRSetting->ulRegAddress ;
1258 retval = wrmalt( Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1259 ul_ddr_setting_load_addr+=sizeof(ULONG);
1260 if(!retval)
1261 {
1262 if(bOverrideSelfRefresh && (psDDRSetting->ulRegAddress == 0x0F007018))
1263 {
1264 value = (psDDRSetting->ulRegValue |(1<<8));
1265 if(STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr,
1266 &value, sizeof(value))){
1267 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1268 break;
1269 }
1270 }
1271 else
1272 {
1273 value = psDDRSetting->ulRegValue;
1274
1275 if(STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr ,
1276 &value, sizeof(value))){
1277 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1278 break;
1279 }
1280 }
1281 }
1282 ul_ddr_setting_load_addr+=sizeof(ULONG);
1283 RegCount--;
1284 psDDRSetting++;
1285 }
1286 return retval;
1287 }
1288
1289
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