drivers/staging/bcm/Ioctl.h

   1 #ifndef _IOCTL_H_
   2 #define _IOCTL_H_
   3
   4 typedef struct rdmbuffer
   5 {
   6         ULONG   Register;
   7         ULONG   Length;
   8 }__attribute__((packed)) RDM_BUFFER, *PRDM_BUFFER;
   9
  10
  11 typedef struct wrmbuffer
  12 {
  13         ULONG   Register;
  14         ULONG   Length;
  15         UCHAR   Data[4];
  16 }__attribute__((packed)) WRM_BUFFER, *PWRM_BUFFER;
  17
  18
  19 typedef struct ioctlbuffer
  20 {
  21         void __user *InputBuffer;
  22         ULONG   InputLength;
  23         void __user *OutputBuffer;
  24         ULONG   OutputLength;
  25 }__attribute__((packed)) IOCTL_BUFFER, *PIOCTL_BUFFER;
  26
  27 typedef struct stGPIOInfo
  28 {
  29         UINT  uiGpioNumber ; /* valid numbers 0-15 */
  30         UINT uiGpioValue; /* 1 set ; 0 not  set */
  31 }__attribute__((packed))GPIO_INFO,*PGPIO_INFO;
  32 typedef struct stUserThreadReq
  33 {
  34         //0->Inactivate LED thread.
  35         //1->Activate the LED thread
  36         UINT ThreadState;
  37 }__attribute__((packed))USER_THREAD_REQ,*PUSER_THREAD_REQ;
  38 #define LED_THREAD_ACTIVATION_REQ  1
  39
  40
  41 ////********** ioctl codes ***********////
  42
  43 #define BCM_IOCTL                               'k'
  44
  45 //1.Control code for CONTROL MESSAGES
  46
  47 #define IOCTL_SEND_CONTROL_MESSAGE                      _IOW(BCM_IOCTL, 0x801,int)
  48
  49 //2.Control code to write a particular value to a particular register
  50 #define IOCTL_BCM_REGISTER_WRITE            _IOW(BCM_IOCTL, 0x802, int) //
  51
  52 //3.
  53 #define IOCTL_BCM_REGISTER_READ             _IOR(BCM_IOCTL, 0x803, int) //
  54
  55 //4.Control code to write x number of bytes to common memory
  56 //starting from address y
  57 #define IOCTL_BCM_COMMON_MEMORY_WRITE       _IOW(BCM_IOCTL, 0x804, int)//
  58
  59 //5.Control code to write x number of bytes to common memory
  60 //starting from address y
  61 #define IOCTL_BCM_COMMON_MEMORY_READ        _IOR(BCM_IOCTL, 0x805, int)//
  62
  63 //6.Control code for CONTROL MESSAGES
  64 #define IOCTL_GET_CONTROL_MESSAGE                       _IOR(BCM_IOCTL, 0x806, int)//
  65
  66 //7.Control code for FIRMWARE DOWNLOAD
  67 #define IOCTL_BCM_FIRMWARE_DOWNLOAD             _IOW(BCM_IOCTL, 0x807, int)//
  68
  69 #define IOCTL_BCM_SET_SEND_VCID                 _IOW(BCM_IOCTL, 0x808, int)
  70
  71 //9.Control code for TRANSFER MODE SWITCHING
  72 #define IOCTL_BCM_SWITCH_TRANSFER_MODE          _IOW(BCM_IOCTL, 0x809, int)
  73 //10.Control code for LINK UP
  74 #define IOCTL_LINK_REQ                                          _IOW(BCM_IOCTL, 0x80A, int)
  75
  76 //11.Control code for RSSI Level Request
  77 #define IOCTL_RSSI_LEVEL_REQ                            _IOW(BCM_IOCTL, 0x80B, int)
  78 //12.Control code for IDLE MODE CONTROL
  79 #define IOCTL_IDLE_REQ                                          _IOW(BCM_IOCTL, 0x80C, int)
  80 //13.Control code for SS/BS info
  81 #define IOCTL_SS_INFO_REQ                                       _IOW(BCM_IOCTL, 0x80D, int)
  82
  83 #define IOCTL_GET_STATISTICS_POINTER            _IOW(BCM_IOCTL, 0x80E, int)
  84
  85 #define IOCTL_CM_REQUEST                                _IOW(BCM_IOCTL, 0x80F, int)
  86
  87 #define IOCTL_INIT_PARAM_REQ                            _IOW(BCM_IOCTL, 0x810, int)
  88
  89 #define IOCTL_MAC_ADDR_REQ                              _IOW(BCM_IOCTL, 0x811, int)
  90
  91 #define IOCTL_MAC_ADDR_RESP                             _IOWR(BCM_IOCTL, 0x812, int)
  92
  93 #define IOCTL_CLASSIFICATION_RULE               _IOW(BCM_IOCTL, 0x813, char)
  94
  95 #define IOCTL_CLOSE_NOTIFICATION                _IO(BCM_IOCTL, 0x814)
  96
  97 #define IOCTL_LINK_UP                                   _IO(BCM_IOCTL, 0x815)
  98
  99 #define IOCTL_LINK_DOWN                                 _IO(BCM_IOCTL, 0x816, IOCTL_BUFFER)
 100
 101 #define IOCTL_CHIP_RESET                _IO(BCM_IOCTL, 0x816)
 102
 103 #define IOCTL_CINR_LEVEL_REQ                    _IOW(BCM_IOCTL, 0x817, char)
 104
 105 #define IOCTL_WTM_CONTROL_REQ                   _IOW(BCM_IOCTL, 0x817,char)
 106
 107 #define IOCTL_BE_BUCKET_SIZE                    _IOW(BCM_IOCTL, 0x818, unsigned long)
 108
 109 #define IOCTL_RTPS_BUCKET_SIZE                  _IOW(BCM_IOCTL, 0x819, unsigned long)
 110
 111 #define IOCTL_QOS_THRESHOLD                             _IOW(BCM_IOCTL, 0x820, unsigned long)
 112
 113 #define IOCTL_DUMP_PACKET_INFO                          _IO(BCM_IOCTL, 0x821)
 114
 115 #define IOCTL_GET_PACK_INFO                                     _IOR(BCM_IOCTL, 0x823, int)
 116
 117 #define IOCTL_BCM_GET_DRIVER_VERSION            _IOR(BCM_IOCTL, 0x829, int)
 118
 119 #define IOCTL_BCM_GET_CURRENT_STATUS            _IOW(BCM_IOCTL, 0x828, int)
 120
 121 #define IOCTL_BCM_GPIO_SET_REQUEST                      _IOW(BCM_IOCTL, 0x82A, int)
 122
 123 #define IOCTL_BCM_GPIO_STATUS_REQUEST           _IOW(BCM_IOCTL, 0x82b, int)
 124
 125 #define IOCTL_BCM_GET_DSX_INDICATION            _IOR(BCM_IOCTL, 0x854, int)
 126
 127 #define IOCTL_BCM_BUFFER_DOWNLOAD_START         _IOW(BCM_IOCTL, 0x855, int)
 128
 129 #define IOCTL_BCM_BUFFER_DOWNLOAD                       _IOW(BCM_IOCTL, 0x856, int)
 130
 131 #define IOCTL_BCM_BUFFER_DOWNLOAD_STOP          _IOW(BCM_IOCTL, 0x857, int)
 132
 133 #define IOCTL_BCM_REGISTER_WRITE_PRIVATE        _IOW(BCM_IOCTL, 0x826, char)
 134
 135 #define IOCTL_BCM_REGISTER_READ_PRIVATE         _IOW(BCM_IOCTL, 0x827, char)
 136
 137 #define IOCTL_BCM_SET_DEBUG                 _IOW(BCM_IOCTL, 0x824, IOCTL_BUFFER)
 138
 139 #define IOCTL_BCM_EEPROM_REGISTER_WRITE         _IOW(BCM_IOCTL, 0x858, int)
 140
 141 #define IOCTL_BCM_EEPROM_REGISTER_READ          _IOR(BCM_IOCTL, 0x859, int)
 142
 143 #define IOCTL_BCM_WAKE_UP_DEVICE_FROM_IDLE      _IOR(BCM_IOCTL, 0x860, int)
 144
 145 #define IOCTL_BCM_SET_MAC_TRACING               _IOW(BCM_IOCTL, 0x82c, int)
 146
 147 #define IOCTL_BCM_GET_HOST_MIBS                         _IOW(BCM_IOCTL, 0x853, int)
 148
 149 #define IOCTL_BCM_NVM_READ                                      _IOR(BCM_IOCTL, 0x861, int)
 150
 151 #define IOCTL_BCM_NVM_WRITE                                     _IOW(BCM_IOCTL, 0x862, int)
 152
 153 #define IOCTL_BCM_GET_NVM_SIZE                          _IOR(BCM_IOCTL, 0x863, int)
 154
 155 #define IOCTL_BCM_CAL_INIT                                      _IOR(BCM_IOCTL, 0x864, int)
 156
 157 #define IOCTL_BCM_BULK_WRM                                      _IOW(BCM_IOCTL, 0x90B, int)
 158
 159 #define IOCTL_BCM_FLASH2X_SECTION_READ          _IOR(BCM_IOCTL, 0x865, int)
 160
 161 #define IOCTL_BCM_FLASH2X_SECTION_WRITE         _IOW(BCM_IOCTL, 0x866, int)
 162
 163 #define IOCTL_BCM_GET_FLASH2X_SECTION_BITMAP _IOR(BCM_IOCTL,0x867, int)
 164
 165 #define IOCTL_BCM_SET_ACTIVE_SECTION            _IOW(BCM_IOCTL,0x868, int)
 166
 167 #define IOCTL_BCM_IDENTIFY_ACTIVE_SECTION       _IO(BCM_IOCTL,0x869)
 168
 169 #define IOCTL_BCM_COPY_SECTION                          _IOW(BCM_IOCTL, 0x870,int)
 170
 171 #define IOCTL_BCM_GET_FLASH_CS_INFO             _IOR(BCM_IOCTL, 0x871, int)
 172
 173 #define IOCTL_BCM_SELECT_DSD                            _IOW(BCM_IOCTL, 0x872, int)
 174
 175 #define IOCTL_BCM_NVM_RAW_READ                          _IOR(BCM_IOCTL, 0x875, int)
 176
 177 #define IOCTL_BCM_CNTRLMSG_MASK                         _IOW(BCM_IOCTL, 0x874, int)
 178
 179 #define IOCTL_BCM_GET_DEVICE_DRIVER_INFO  _IOR(BCM_IOCTL, 0x877, int)
 180
 181 #define IOCTL_BCM_TIME_SINCE_NET_ENTRY  _IOR(BCM_IOCTL, 0x876, int)
 182
 183 #define BCM_LED_THREAD_STATE_CHANGE_REQ   _IOW(BCM_IOCTL, 0x878, int)
 184
 185 #define IOCTL_BCM_GPIO_MULTI_REQUEST            _IOW(BCM_IOCTL, 0x82D, IOCTL_BUFFER)
 186 #define IOCTL_BCM_GPIO_MODE_REQUEST                     _IOW(BCM_IOCTL, 0x82E, IOCTL_BUFFER)
 187
 188
 189
 190 typedef enum _BCM_INTERFACE_TYPE
 191 {
 192         BCM_MII,
 193         BCM_CARDBUS,
 194         BCM_USB,
 195         BCM_SDIO,
 196         BCM_PCMCIA
 197 }BCM_INTERFACE_TYPE;
 198
 199 typedef struct _DEVICE_DRIVER_INFO
 200 {
 201         NVM_TYPE                        u32NVMType;
 202         UINT                            MaxRDMBufferSize;
 203         BCM_INTERFACE_TYPE      u32InterfaceType;
 204         UINT                            u32DSDStartOffset;
 205         UINT                            u32RxAlignmentCorrection;
 206         UINT                            u32Reserved[10];
 207 } DEVICE_DRIVER_INFO;
 208
 209 typedef  struct _NVM_READWRITE
 210 {
 211
 212         void __user *pBuffer;
 213 // Data to be written from|read to. Memory should be allocated by the caller.
 214
 215         uint32_t  uiOffset;
 216 // offset at which data should be written to or read from.
 217
 218         uint32_t  uiNumBytes;
 219 // No. of bytes to be written or read.
 220
 221         bool  bVerify;
 222 // Applicable only for write. If set verification of written data will be done.
 223
 224 } NVM_READWRITE,*PNVM_READWRITE;
 225 typedef struct bulkwrmbuffer
 226 {
 227         ULONG   Register;
 228         ULONG   SwapEndian;
 229         ULONG   Values[1];
 230
 231 }BULKWRM_BUFFER,*PBULKWRM_BUFFER;
 232
 233
 234 /***********Structure used for FlashMap2.x *******************************/
 235
 236 /*
 237 *       These are Sction present inside the Flash.
 238 *       There is sectional RD/WR for flash Map 2.x.
 239 *       hence these section will be used in read/write API.
 240 */
 241
 242 typedef enum _FLASH2X_SECTION_VAL
 243 {
 244         NO_SECTION_VAL = 0, //no section is chosen when absolute offset is given for RD/WR
 245         ISO_IMAGE1,
 246         ISO_IMAGE2,
 247         DSD0,
 248         DSD1,
 249         DSD2,
 250         VSA0,
 251         VSA1,
 252         VSA2,
 253         SCSI,
 254         CONTROL_SECTION,
 255         ISO_IMAGE1_PART2,
 256         ISO_IMAGE1_PART3,
 257         ISO_IMAGE2_PART2,
 258         ISO_IMAGE2_PART3,
 259         TOTAL_SECTIONS
 260 }FLASH2X_SECTION_VAL;
 261
 262 /*
 263 *       Structure used for READ/WRITE Flash  Map2.x
 264 */
 265 typedef struct _FLASH2X_READWRITE
 266 {
 267
 268         FLASH2X_SECTION_VAL Section; //which section has to be read/written
 269         B_UINT32 offset;                //Offset within Section.
 270         B_UINT32 numOfBytes;    //NOB from the offset
 271         B_UINT32  bVerify;
 272         void __user *pDataBuff; //Buffer for reading/writing
 273
 274 }FLASH2X_READWRITE, *PFLASH2X_READWRITE;
 275 /*
 276 *       This structure is used for coping one section to other.
 277 *       there are two ways to copy one section to other.
 278 *       it NOB =0, complete section will be copied on to other.
 279 *       if NOB !=0, only NOB will be copied from the given offset.
 280 */
 281
 282 typedef struct _FLASH2X_COPY_SECTION
 283 {
 284         //Src Section from which Data has to be copied to DstSection
 285         FLASH2X_SECTION_VAL SrcSection;
 286
 287         //Destination Section from where Data has to be coppied.
 288         FLASH2X_SECTION_VAL DstSection;
 289
 290         //Offset within Section. if NOB =0 it will be ignored and data will be coped from offset 0.
 291         B_UINT32 offset;
 292
 293         //NOB from the offset. if NOB = 0 complete src section will be copied to Destination section.
 294         B_UINT32 numOfBytes;
 295 } FLASH2X_COPY_SECTION, *PFLASH2X_COPY_SECTION;
 296
 297
 298 typedef enum _SECTION_TYPE
 299 {
 300         ISO = 0,
 301         VSA = 1,
 302         DSD = 2
 303 } SECTION_TYPE, *PSECTION_TYPE;
 304
 305 /*
 306 *       This section provide the complete bitmap of the Flash.
 307 *       using this map lib/APP will isssue read/write command.
 308         Fields are defined as :
 309         Bit [0] = section is present  //1:present, 0: Not present
 310 *      Bit [1] = section is valid  //1: valid, 0: not valid
 311 *      Bit [2] = Section is R/W  //0: RW, 1: RO
 312 *       Bit [3] = Section is Active or not 1 means Active, 0->inactive
 313 *      Bit [7...3] = Reserved
 314 */
 315
 316 typedef struct _FLASH2X_BITMAP
 317 {
 318         UCHAR ISO_IMAGE1;
 319         UCHAR ISO_IMAGE2;
 320         UCHAR DSD0;
 321         UCHAR DSD1;
 322         UCHAR DSD2;
 323         UCHAR VSA0;
 324         UCHAR VSA1;
 325         UCHAR VSA2;
 326         UCHAR SCSI;
 327         UCHAR CONTROL_SECTION;
 328         //Reserved for future use
 329         UCHAR Reserved0;
 330         UCHAR Reserved1;
 331         UCHAR Reserved2;
 332 }FLASH2X_BITMAP, *PFLASH2X_BITMAP;
 333
 334 //for net entry time check
 335 typedef struct _ST_TIME_ELAPSED_
 336 {
 337         ULONG64 ul64TimeElapsedSinceNetEntry;
 338         UINT32   uiReserved[4]; //By chance if required for future proofing
 339 }ST_TIME_ELAPSED,*PST_TIME_ELAPSED;
 340
 341 enum {
 342   WIMAX_IDX=0, /*To access WiMAX chip GPIO's for GPIO_MULTI_INFO or GPIO_MULTI_MODE*/
 343   HOST_IDX,    /*To access Host chip GPIO's for GPIO_MULTI_INFO or GPIO_MULTI_MODE*/
 344   MAX_IDX
 345 };
 346 typedef struct stGPIOMultiInfo
 347 {
 348   UINT uiGPIOCommand; /* 1 for set and 0 for get*/
 349   UINT uiGPIOMask;    /* set the correspondig bit to 1 to access GPIO*/
 350   UINT uiGPIOValue;   /* 0 or 1; value to be set when command is 1.*/
 351 }__attribute__((packed))GPIO_MULTI_INFO , *PGPIO_MULTI_INFO;
 352
 353 typedef struct stGPIOMultiMode
 354 {
 355   UINT uiGPIOMode;    /* 1 for OUT mode, 0 for IN mode*/
 356   UINT uiGPIOMask;    /* GPIO mask to set mode*/
 357 }__attribute__((packed))GPIO_MULTI_MODE, *PGPIO_MULTI_MODE;
 358
 359
 360 #endif