drivers/staging/iio/dds/ad9832.c

   1 /*
   2  * AD9832 SPI DDS driver
   3  *
   4  * Copyright 2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/sysfs.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/err.h>
  16 #include <asm/div64.h>
  17
  18 #include "../iio.h"
  19 #include "../sysfs.h"
  20 #include "dds.h"
  21
  22 #include "ad9832.h"
  23
  24 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
  25 {
  26         unsigned long long freqreg = (u64) fout *
  27                                      (u64) ((u64) 1L << AD9832_FREQ_BITS);
  28         do_div(freqreg, mclk);
  29         return freqreg;
  30 }
  31
  32 static int ad9832_write_frequency(struct ad9832_state *st,
  33                                   unsigned addr, unsigned long fout)
  34 {
  35         unsigned long regval;
  36
  37         if (fout > (st->mclk / 2))
  38                 return -EINVAL;
  39
  40         regval = ad9832_calc_freqreg(st->mclk, fout);
  41
  42         st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
  43                                         (addr << ADD_SHIFT) |
  44                                         ((regval >> 24) & 0xFF));
  45         st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
  46                                         ((addr - 1) << ADD_SHIFT) |
  47                                         ((regval >> 16) & 0xFF));
  48         st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
  49                                         ((addr - 2) << ADD_SHIFT) |
  50                                         ((regval >> 8) & 0xFF));
  51         st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
  52                                         ((addr - 3) << ADD_SHIFT) |
  53                                         ((regval >> 0) & 0xFF));
  54
  55         return spi_sync(st->spi, &st->freq_msg);;
  56 }
  57
  58 static int ad9832_write_phase(struct ad9832_state *st,
  59                                   unsigned long addr, unsigned long phase)
  60 {
  61         if (phase > (1 << AD9832_PHASE_BITS))
  62                 return -EINVAL;
  63
  64         st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
  65                                         (addr << ADD_SHIFT) |
  66                                         ((phase >> 8) & 0xFF));
  67         st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
  68                                         ((addr - 1) << ADD_SHIFT) |
  69                                         (phase & 0xFF));
  70
  71         return spi_sync(st->spi, &st->phase_msg);
  72 }
  73
  74 static ssize_t ad9832_write(struct device *dev,
  75                 struct device_attribute *attr,
  76                 const char *buf,
  77                 size_t len)
  78 {
  79         struct iio_dev *dev_info = dev_get_drvdata(dev);
  80         struct ad9832_state *st = iio_priv(dev_info);
  81         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
  82         int ret;
  83         long val;
  84
  85         ret = strict_strtoul(buf, 10, &val);
  86         if (ret)
  87                 goto error_ret;
  88
  89         mutex_lock(&dev_info->mlock);
  90         switch (this_attr->address) {
  91         case AD9832_FREQ0HM:
  92         case AD9832_FREQ1HM:
  93                 ret = ad9832_write_frequency(st, this_attr->address, val);
  94                 break;
  95         case AD9832_PHASE0H:
  96         case AD9832_PHASE1H:
  97         case AD9832_PHASE2H:
  98         case AD9832_PHASE3H:
  99                 ret = ad9832_write_phase(st, this_attr->address, val);
 100                 break;
 101         case AD9832_PINCTRL_EN:
 102                 if (val)
 103                         st->ctrl_ss &= ~AD9832_SELSRC;
 104                 else
 105                         st->ctrl_ss |= AD9832_SELSRC;
 106                 st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
 107                                         st->ctrl_ss);
 108                 ret = spi_sync(st->spi, &st->msg);
 109                 break;
 110         case AD9832_FREQ_SYM:
 111                 if (val == 1)
 112                         st->ctrl_fp |= AD9832_FREQ;
 113                 else if (val == 0)
 114                         st->ctrl_fp &= ~AD9832_FREQ;
 115                 else {
 116                         ret = -EINVAL;
 117                         break;
 118                 }
 119                 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
 120                                         st->ctrl_fp);
 121                 ret = spi_sync(st->spi, &st->msg);
 122                 break;
 123         case AD9832_PHASE_SYM:
 124                 if (val < 0 || val > 3) {
 125                         ret = -EINVAL;
 126                         break;
 127                 }
 128
 129                 st->ctrl_fp &= ~AD9832_PHASE(3);
 130                 st->ctrl_fp |= AD9832_PHASE(val);
 131
 132                 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
 133                                         st->ctrl_fp);
 134                 ret = spi_sync(st->spi, &st->msg);
 135                 break;
 136         case AD9832_OUTPUT_EN:
 137                 if (val)
 138                         st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
 139                                         AD9832_CLR);
 140                 else
 141                         st->ctrl_src |= AD9832_RESET;
 142
 143                 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
 144                                         st->ctrl_src);
 145                 ret = spi_sync(st->spi, &st->msg);
 146                 break;
 147         default:
 148                 ret = -ENODEV;
 149         }
 150         mutex_unlock(&dev_info->mlock);
 151
 152 error_ret:
 153         return ret ? ret : len;
 154 }
 155
 156 /**
 157  * see dds.h for further information
 158  */
 159
 160 static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
 161 static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
 162 static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
 163 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
 164
 165 static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
 166 static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
 167 static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
 168 static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
 169 static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
 170                                 ad9832_write, AD9832_PHASE_SYM);
 171 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
 172
 173 static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
 174                                 ad9832_write, AD9832_PINCTRL_EN);
 175 static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
 176                                 ad9832_write, AD9832_OUTPUT_EN);
 177
 178 static struct attribute *ad9832_attributes[] = {
 179         &iio_dev_attr_dds0_freq0.dev_attr.attr,
 180         &iio_dev_attr_dds0_freq1.dev_attr.attr,
 181         &iio_const_attr_dds0_freq_scale.dev_attr.attr,
 182         &iio_dev_attr_dds0_phase0.dev_attr.attr,
 183         &iio_dev_attr_dds0_phase1.dev_attr.attr,
 184         &iio_dev_attr_dds0_phase2.dev_attr.attr,
 185         &iio_dev_attr_dds0_phase3.dev_attr.attr,
 186         &iio_const_attr_dds0_phase_scale.dev_attr.attr,
 187         &iio_dev_attr_dds0_pincontrol_en.dev_attr.attr,
 188         &iio_dev_attr_dds0_freqsymbol.dev_attr.attr,
 189         &iio_dev_attr_dds0_phasesymbol.dev_attr.attr,
 190         &iio_dev_attr_dds0_out_enable.dev_attr.attr,
 191         NULL,
 192 };
 193
 194 static const struct attribute_group ad9832_attribute_group = {
 195         .attrs = ad9832_attributes,
 196 };
 197
 198 static const struct iio_info ad9832_info = {
 199         .attrs = &ad9832_attribute_group,
 200         .driver_module = THIS_MODULE,
 201 };
 202
 203 static int __devinit ad9832_probe(struct spi_device *spi)
 204 {
 205         struct ad9832_platform_data *pdata = spi->dev.platform_data;
 206         struct iio_dev *indio_dev;
 207         struct ad9832_state *st;
 208         struct regulator *reg;
 209         int ret;
 210
 211         if (!pdata) {
 212                 dev_dbg(&spi->dev, "no platform data?\n");
 213                 return -ENODEV;
 214         }
 215
 216         reg = regulator_get(&spi->dev, "vcc");
 217         if (!IS_ERR(reg)) {
 218                 ret = regulator_enable(reg);
 219                 if (ret)
 220                         goto error_put_reg;
 221         }
 222
 223         indio_dev = iio_allocate_device(sizeof(*st));
 224         if (indio_dev == NULL) {
 225                 ret = -ENOMEM;
 226                 goto error_disable_reg;
 227         }
 228         spi_set_drvdata(spi, indio_dev);
 229         st = iio_priv(indio_dev);
 230         st->reg = reg;
 231         st->mclk = pdata->mclk;
 232         st->spi = spi;
 233
 234         indio_dev->dev.parent = &spi->dev;
 235         indio_dev->name = spi_get_device_id(spi)->name;
 236         indio_dev->info = &ad9832_info;
 237         indio_dev->modes = INDIO_DIRECT_MODE;
 238
 239         /* Setup default messages */
 240
 241         st->xfer.tx_buf = &st->data;
 242         st->xfer.len = 2;
 243
 244         spi_message_init(&st->msg);
 245         spi_message_add_tail(&st->xfer, &st->msg);
 246
 247         st->freq_xfer[0].tx_buf = &st->freq_data[0];
 248         st->freq_xfer[0].len = 2;
 249         st->freq_xfer[0].cs_change = 1;
 250         st->freq_xfer[1].tx_buf = &st->freq_data[1];
 251         st->freq_xfer[1].len = 2;
 252         st->freq_xfer[1].cs_change = 1;
 253         st->freq_xfer[2].tx_buf = &st->freq_data[2];
 254         st->freq_xfer[2].len = 2;
 255         st->freq_xfer[2].cs_change = 1;
 256         st->freq_xfer[3].tx_buf = &st->freq_data[3];
 257         st->freq_xfer[3].len = 2;
 258
 259         spi_message_init(&st->freq_msg);
 260         spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
 261         spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
 262         spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
 263         spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
 264
 265         st->phase_xfer[0].tx_buf = &st->phase_data[0];
 266         st->phase_xfer[0].len = 2;
 267         st->phase_xfer[0].cs_change = 1;
 268         st->phase_xfer[1].tx_buf = &st->phase_data[1];
 269         st->phase_xfer[1].len = 2;
 270
 271         spi_message_init(&st->phase_msg);
 272         spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
 273         spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
 274
 275         st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
 276         st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
 277                                         st->ctrl_src);
 278         ret = spi_sync(st->spi, &st->msg);
 279         if (ret) {
 280                 dev_err(&spi->dev, "device init failed\n");
 281                 goto error_free_device;
 282         }
 283
 284         ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
 285         if (ret)
 286                 goto error_free_device;
 287
 288         ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
 289         if (ret)
 290                 goto error_free_device;
 291
 292         ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
 293         if (ret)
 294                 goto error_free_device;
 295
 296         ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
 297         if (ret)
 298                 goto error_free_device;
 299
 300         ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
 301         if (ret)
 302                 goto error_free_device;
 303
 304         ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
 305         if (ret)
 306                 goto error_free_device;
 307
 308         ret = iio_device_register(indio_dev);
 309         if (ret)
 310                 goto error_free_device;
 311
 312         return 0;
 313
 314 error_free_device:
 315         iio_free_device(indio_dev);
 316 error_disable_reg:
 317         if (!IS_ERR(reg))
 318                 regulator_disable(reg);
 319 error_put_reg:
 320         if (!IS_ERR(reg))
 321                 regulator_put(reg);
 322
 323         return ret;
 324 }
 325
 326 static int __devexit ad9832_remove(struct spi_device *spi)
 327 {
 328         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 329         struct ad9832_state *st = iio_priv(indio_dev);
 330         struct regulator *reg = st->reg;
 331
 332         iio_device_unregister(indio_dev);
 333         if (!IS_ERR(reg)) {
 334                 regulator_disable(reg);
 335                 regulator_put(reg);
 336         }
 337         return 0;
 338 }
 339
 340 static const struct spi_device_id ad9832_id[] = {
 341         {"ad9832", 0},
 342         {"ad9835", 0},
 343         {}
 344 };
 345
 346 static struct spi_driver ad9832_driver = {
 347         .driver = {
 348                 .name   = "ad9832",
 349                 .bus    = &spi_bus_type,
 350                 .owner  = THIS_MODULE,
 351         },
 352         .probe          = ad9832_probe,
 353         .remove         = __devexit_p(ad9832_remove),
 354         .id_table       = ad9832_id,
 355 };
 356
 357 static int __init ad9832_init(void)
 358 {
 359         return spi_register_driver(&ad9832_driver);
 360 }
 361 module_init(ad9832_init);
 362
 363 static void __exit ad9832_exit(void)
 364 {
 365         spi_unregister_driver(&ad9832_driver);
 366 }
 367 module_exit(ad9832_exit);
 368
 369 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 370 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
 371 MODULE_LICENSE("GPL v2");
 372 MODULE_ALIAS("spi:ad9832");