drivers/staging/lirc/lirc_ene0100.h

   1 /*
   2  * driver for ENE KB3926 B/C/D CIR (also known as ENE0100)
   3  *
   4  * Copyright (C) 2009 Maxim Levitsky <maximlevitsky@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of the
   9  * License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  19  * USA
  20  */
  21
  22 #include <media/lirc.h>
  23 #include <media/lirc_dev.h>
  24
  25 /* hardware address */
  26 #define ENE_STATUS              0        /* hardware status - unused */
  27 #define ENE_ADDR_HI             1        /* hi byte of register address */
  28 #define ENE_ADDR_LO             2        /* low byte of register address */
  29 #define ENE_IO                  3        /* read/write window */
  30 #define ENE_MAX_IO              4
  31
  32 /* 8 bytes of samples, divided in 2 halfs*/
  33 #define ENE_SAMPLE_BUFFER       0xF8F0   /* regular sample buffer */
  34 #define ENE_SAMPLE_SPC_MASK     (1 << 7) /* sample is space */
  35 #define ENE_SAMPLE_VALUE_MASK   0x7F
  36 #define ENE_SAMPLE_OVERFLOW     0x7F
  37 #define ENE_SAMPLES_SIZE        4
  38
  39 /* fan input sample buffer */
  40 #define ENE_SAMPLE_BUFFER_FAN   0xF8FB   /* this buffer holds high byte of */
  41                                          /* each sample of normal buffer */
  42
  43 #define ENE_FAN_SMPL_PULS_MSK   0x8000   /* this bit of combined sample */
  44                                          /* if set, says that sample is pulse */
  45 #define ENE_FAN_VALUE_MASK      0x0FFF   /* mask for valid bits of the value */
  46
  47 /* first firmware register */
  48 #define ENE_FW1                 0xF8F8
  49 #define ENE_FW1_ENABLE          (1 << 0) /* enable fw processing */
  50 #define ENE_FW1_TXIRQ           (1 << 1) /* TX interrupt pending */
  51 #define ENE_FW1_WAKE            (1 << 6) /* enable wake from S3 */
  52 #define ENE_FW1_IRQ             (1 << 7) /* enable interrupt */
  53
  54 /* second firmware register */
  55 #define ENE_FW2                 0xF8F9
  56 #define ENE_FW2_BUF_HIGH        (1 << 0) /* which half of the buffer to read */
  57 #define ENE_FW2_IRQ_CLR         (1 << 2) /* clear this on IRQ */
  58 #define ENE_FW2_GP40_AS_LEARN   (1 << 4) /* normal input is used as */
  59                                          /* learning input */
  60 #define ENE_FW2_FAN_AS_NRML_IN  (1 << 6) /* fan is used as normal input */
  61 #define ENE_FW2_LEARNING        (1 << 7) /* hardware supports learning and TX */
  62
  63 /* fan as input settings - only if learning capable */
  64 #define ENE_FAN_AS_IN1          0xFE30   /* fan init reg 1 */
  65 #define ENE_FAN_AS_IN1_EN       0xCD
  66 #define ENE_FAN_AS_IN2          0xFE31   /* fan init reg 2 */
  67 #define ENE_FAN_AS_IN2_EN       0x03
  68 #define ENE_SAMPLE_PERIOD_FAN   61       /* fan input has fixed sample period */
  69
  70 /* IRQ registers block (for revision B) */
  71 #define ENEB_IRQ                0xFD09   /* IRQ number */
  72 #define ENEB_IRQ_UNK1           0xFD17   /* unknown setting = 1 */
  73 #define ENEB_IRQ_STATUS         0xFD80   /* irq status */
  74 #define ENEB_IRQ_STATUS_IR      (1 << 5) /* IR irq */
  75
  76 /* IRQ registers block (for revision C,D) */
  77 #define ENEC_IRQ                0xFE9B   /* new irq settings register */
  78 #define ENEC_IRQ_MASK           0x0F     /* irq number mask */
  79 #define ENEC_IRQ_UNK_EN         (1 << 4) /* always enabled */
  80 #define ENEC_IRQ_STATUS         (1 << 5) /* irq status and ACK */
  81
  82 /* CIR block settings */
  83 #define ENE_CIR_CONF1           0xFEC0
  84 #define ENE_CIR_CONF1_ADC_ON    0x7      /* receiver on gpio40 enabled */
  85 #define ENE_CIR_CONF1_LEARN1    (1 << 3) /* enabled on learning mode */
  86 #define ENE_CIR_CONF1_TX_ON     0x30     /* enabled on transmit */
  87 #define ENE_CIR_CONF1_TX_CARR   (1 << 7) /* send TX carrier or not */
  88
  89 #define ENE_CIR_CONF2           0xFEC1   /* unknown setting = 0 */
  90 #define ENE_CIR_CONF2_LEARN2    (1 << 4) /* set on enable learning */
  91 #define ENE_CIR_CONF2_GPIO40DIS (1 << 5) /* disable normal input via gpio40 */
  92
  93 #define ENE_CIR_SAMPLE_PERIOD   0xFEC8   /* sample period in us */
  94 #define ENE_CIR_SAMPLE_OVERFLOW (1 << 7) /* interrupt on overflows if set */
  95
  96
  97 /* transmitter - not implemented yet */
  98 /* KB3926C and higher */
  99 /* transmission is very similar to receiving, a byte is written to */
 100 /* ENE_TX_INPUT, in same manner as it is read from sample buffer */
 101 /* sample period is fixed*/
 102
 103
 104 /* transmitter ports */
 105 #define ENE_TX_PORT1            0xFC01   /* this enables one or both */
 106 #define ENE_TX_PORT1_EN         (1 << 5) /* TX ports */
 107 #define ENE_TX_PORT2            0xFC08
 108 #define ENE_TX_PORT2_EN         (1 << 1)
 109
 110 #define ENE_TX_INPUT            0xFEC9   /* next byte to transmit */
 111 #define ENE_TX_SPC_MASK         (1 << 7) /* Transmitted sample is space */
 112 #define ENE_TX_UNK1             0xFECB   /* set to 0x63 */
 113 #define ENE_TX_SMPL_PERIOD      50       /* transmit sample period */
 114
 115
 116 #define ENE_TX_CARRIER          0xFECE   /* TX carrier * 2 (khz) */
 117 #define ENE_TX_CARRIER_UNKBIT   0x80     /* This bit set on transmit */
 118 #define ENE_TX_CARRIER_LOW      0xFECF   /* TX carrier / 2 */
 119
 120 /* Hardware versions */
 121 #define ENE_HW_VERSION          0xFF00   /* hardware revision */
 122 #define ENE_HW_UNK              0xFF1D
 123 #define ENE_HW_UNK_CLR          (1 << 2)
 124 #define ENE_HW_VER_MAJOR        0xFF1E   /* chip version */
 125 #define ENE_HW_VER_MINOR        0xFF1F
 126 #define ENE_HW_VER_OLD          0xFD00
 127
 128 #define same_sign(a, b) ((((a) > 0) && (b) > 0) || ((a) < 0 && (b) < 0))
 129
 130 #define ENE_DRIVER_NAME         "enecir"
 131 #define ENE_MAXGAP              250000   /* this is amount of time we wait
 132                                          before turning the sampler, chosen
 133                                          arbitry */
 134
 135 #define space(len)             (-(len))  /* add a space */
 136
 137 /* software defines */
 138 #define ENE_IRQ_RX              1
 139 #define ENE_IRQ_TX              2
 140
 141 #define  ENE_HW_B               1       /* 3926B */
 142 #define  ENE_HW_C               2       /* 3926C */
 143 #define  ENE_HW_D               3       /* 3926D */
 144
 145 #define ene_printk(level, text, ...) \
 146         printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__)
 147
 148 struct ene_device {
 149         struct pnp_dev *pnp_dev;
 150         struct lirc_driver *lirc_driver;
 151
 152         /* hw settings */
 153         unsigned long hw_io;
 154         int irq;
 155
 156         int hw_revision;                        /* hardware revision */
 157         int hw_learning_and_tx_capable;         /* learning capable */
 158         int hw_gpio40_learning;                 /* gpio40 is learning */
 159         int hw_fan_as_normal_input;     /* fan input is used as regular input */
 160
 161         /* device data */
 162         int idle;
 163         int fan_input_inuse;
 164
 165         int sample;
 166         int in_use;
 167
 168         struct timeval gap_start;
 169 };