arch/mips/alchemy/common/power.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Au1xx0 Power Management routines.
   4  *
   5  * Copyright 2001, 2008 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc. <source@mvista.com>
   7  *
   8  *  Some of the routines are right out of init/main.c, whose
   9  *  copyrights apply here.
  10  *
  11  *  This program is free software; you can redistribute  it and/or modify it
  12  *  under  the terms of  the GNU General  Public License as published by the
  13  *  Free Software Foundation;  either version 2 of the  License, or (at your
  14  *  option) any later version.
  15  *
  16  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  17  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  19  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  22  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  24  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  *  You should have received a copy of the  GNU General Public License along
  28  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  29  *  675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/pm.h>
  34 #include <linux/sysctl.h>
  35 #include <linux/jiffies.h>
  36
  37 #include <asm/uaccess.h>
  38 #include <asm/mach-au1x00/au1000.h>
  39
  40 #ifdef CONFIG_PM
  41
  42 /*
  43  * We need to save/restore a bunch of core registers that are
  44  * either volatile or reset to some state across a processor sleep.
  45  * If reading a register doesn't provide a proper result for a
  46  * later restore, we have to provide a function for loading that
  47  * register and save a copy.
  48  *
  49  * We only have to save/restore registers that aren't otherwise
  50  * done as part of a driver pm_* function.
  51  */
  52 static unsigned int sleep_usb[2];
  53 static unsigned int sleep_sys_clocks[5];
  54 static unsigned int sleep_sys_pinfunc;
  55 static unsigned int sleep_static_memctlr[4][3];
  56
  57
  58 static void save_core_regs(void)
  59 {
  60 #ifndef CONFIG_SOC_AU1200
  61         /* Shutdown USB host/device. */
  62         sleep_usb[0] = au_readl(USB_HOST_CONFIG);
  63
  64         /* There appears to be some undocumented reset register.... */
  65         au_writel(0, 0xb0100004);
  66         au_sync();
  67         au_writel(0, USB_HOST_CONFIG);
  68         au_sync();
  69
  70         sleep_usb[1] = au_readl(USBD_ENABLE);
  71         au_writel(0, USBD_ENABLE);
  72         au_sync();
  73
  74 #else   /* AU1200 */
  75
  76         /* enable access to OTG mmio so we can save OTG CAP/MUX.
  77          * FIXME: write an OTG driver and move this stuff there!
  78          */
  79         au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
  80         au_sync();
  81         sleep_usb[0] = au_readl(0xb4020020);    /* OTG_CAP */
  82         sleep_usb[1] = au_readl(0xb4020024);    /* OTG_MUX */
  83 #endif
  84
  85         /* Clocks and PLLs. */
  86         sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
  87         sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
  88         sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
  89         sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
  90         sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
  91
  92         /* pin mux config */
  93         sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
  94
  95         /* Save the static memory controller configuration. */
  96         sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
  97         sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
  98         sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
  99         sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
 100         sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
 101         sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
 102         sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
 103         sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
 104         sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
 105         sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
 106         sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
 107         sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
 108 }
 109
 110 static void restore_core_regs(void)
 111 {
 112         /* restore clock configuration.  Writing CPUPLL last will
 113          * stall a bit and stabilize other clocks (unless this is
 114          * one of those Au1000 with a write-only PLL, where we dont
 115          * have a valid value)
 116          */
 117         au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
 118         au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
 119         au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
 120         au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
 121         if (!au1xxx_cpu_has_pll_wo())
 122                 au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
 123         au_sync();
 124
 125         au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
 126         au_sync();
 127
 128 #ifndef CONFIG_SOC_AU1200
 129         au_writel(sleep_usb[0], USB_HOST_CONFIG);
 130         au_writel(sleep_usb[1], USBD_ENABLE);
 131         au_sync();
 132 #else
 133         /* enable access to OTG memory */
 134         au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
 135         au_sync();
 136
 137         /* restore OTG caps and port mux. */
 138         au_writel(sleep_usb[0], 0xb4020020 + 0);        /* OTG_CAP */
 139         au_sync();
 140         au_writel(sleep_usb[1], 0xb4020020 + 4);        /* OTG_MUX */
 141         au_sync();
 142 #endif
 143
 144         /* Restore the static memory controller configuration. */
 145         au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
 146         au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
 147         au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
 148         au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
 149         au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
 150         au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
 151         au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
 152         au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
 153         au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
 154         au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
 155         au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
 156         au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
 157 }
 158
 159 void au_sleep(void)
 160 {
 161         save_core_regs();
 162
 163         switch (alchemy_get_cputype()) {
 164         case ALCHEMY_CPU_AU1000:
 165         case ALCHEMY_CPU_AU1500:
 166         case ALCHEMY_CPU_AU1100:
 167                 alchemy_sleep_au1000();
 168                 break;
 169         case ALCHEMY_CPU_AU1550:
 170         case ALCHEMY_CPU_AU1200:
 171                 alchemy_sleep_au1550();
 172                 break;
 173         }
 174
 175         restore_core_regs();
 176 }
 177
 178 #endif  /* CONFIG_PM */