drivers/staging/brcm80211/brcmsmac/aiutils.h

   1 /*
   2  * Copyright (c) 2011 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _BRCM_AIUTILS_H_
  18 #define _BRCM_AIUTILS_H_
  19
  20 #include "types.h"
  21
  22 /*
  23  * SOC Interconnect Address Map.
  24  * All regions may not exist on all chips.
  25  */
  26 /* Physical SDRAM */
  27 #define SI_SDRAM_BASE           0x00000000
  28 /* Host Mode sb2pcitranslation0 (64 MB) */
  29 #define SI_PCI_MEM              0x08000000
  30 #define SI_PCI_MEM_SZ           (64 * 1024 * 1024)
  31 /* Host Mode sb2pcitranslation1 (64 MB) */
  32 #define SI_PCI_CFG              0x0c000000
  33 /* Byteswapped Physical SDRAM */
  34 #define SI_SDRAM_SWAPPED        0x10000000
  35 /* Region 2 for sdram (512 MB) */
  36 #define SI_SDRAM_R2             0x80000000
  37
  38 #ifdef SI_ENUM_BASE_VARIABLE
  39 #define SI_ENUM_BASE            (sii->pub.si_enum_base)
  40 #else
  41 #define SI_ENUM_BASE            0x18000000      /* Enumeration space base */
  42 #endif                          /* SI_ENUM_BASE_VARIABLE */
  43
  44 /* Wrapper space base */
  45 #define SI_WRAP_BASE            0x18100000
  46 /* each core gets 4Kbytes for registers */
  47 #define SI_CORE_SIZE            0x1000
  48 /*
  49  * Max cores (this is arbitrary, for software
  50  * convenience and could be changed if we
  51  * make any larger chips
  52  */
  53 #define SI_MAXCORES             16
  54
  55 /* On-chip RAM on chips that also have DDR */
  56 #define SI_FASTRAM              0x19000000
  57 #define SI_FASTRAM_SWAPPED      0x19800000
  58
  59 /* Flash Region 2 (region 1 shadowed here) */
  60 #define SI_FLASH2               0x1c000000
  61 /* Size of Flash Region 2 */
  62 #define SI_FLASH2_SZ            0x02000000
  63 /* ARM Cortex-M3 ROM */
  64 #define SI_ARMCM3_ROM           0x1e000000
  65 /* MIPS Flash Region 1 */
  66 #define SI_FLASH1               0x1fc00000
  67 /* MIPS Size of Flash Region 1 */
  68 #define SI_FLASH1_SZ            0x00400000
  69 /* ARM7TDMI-S ROM */
  70 #define SI_ARM7S_ROM            0x20000000
  71 /* ARM Cortex-M3 SRAM Region 2 */
  72 #define SI_ARMCM3_SRAM2         0x60000000
  73 /* ARM7TDMI-S SRAM Region 2 */
  74 #define SI_ARM7S_SRAM2          0x80000000
  75 /* ARM Flash Region 1 */
  76 #define SI_ARM_FLASH1           0xffff0000
  77 /* ARM Size of Flash Region 1 */
  78 #define SI_ARM_FLASH1_SZ        0x00010000
  79
  80 /* Client Mode sb2pcitranslation2 (1 GB) */
  81 #define SI_PCI_DMA              0x40000000
  82 /* Client Mode sb2pcitranslation2 (1 GB) */
  83 #define SI_PCI_DMA2             0x80000000
  84 /* Client Mode sb2pcitranslation2 size in bytes */
  85 #define SI_PCI_DMA_SZ           0x40000000
  86 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
  87 #define SI_PCIE_DMA_L32         0x00000000
  88 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
  89 #define SI_PCIE_DMA_H32         0x80000000
  90
  91 /* core codes */
  92 #define NODEV_CORE_ID           0x700   /* Invalid coreid */
  93 #define CC_CORE_ID              0x800   /* chipcommon core */
  94 #define ILINE20_CORE_ID         0x801   /* iline20 core */
  95 #define SRAM_CORE_ID            0x802   /* sram core */
  96 #define SDRAM_CORE_ID           0x803   /* sdram core */
  97 #define PCI_CORE_ID             0x804   /* pci core */
  98 #define MIPS_CORE_ID            0x805   /* mips core */
  99 #define ENET_CORE_ID            0x806   /* enet mac core */
 100 #define CODEC_CORE_ID           0x807   /* v90 codec core */
 101 #define USB_CORE_ID             0x808   /* usb 1.1 host/device core */
 102 #define ADSL_CORE_ID            0x809   /* ADSL core */
 103 #define ILINE100_CORE_ID        0x80a   /* iline100 core */
 104 #define IPSEC_CORE_ID           0x80b   /* ipsec core */
 105 #define UTOPIA_CORE_ID          0x80c   /* utopia core */
 106 #define PCMCIA_CORE_ID          0x80d   /* pcmcia core */
 107 #define SOCRAM_CORE_ID          0x80e   /* internal memory core */
 108 #define MEMC_CORE_ID            0x80f   /* memc sdram core */
 109 #define OFDM_CORE_ID            0x810   /* OFDM phy core */
 110 #define EXTIF_CORE_ID           0x811   /* external interface core */
 111 #define D11_CORE_ID             0x812   /* 802.11 MAC core */
 112 #define APHY_CORE_ID            0x813   /* 802.11a phy core */
 113 #define BPHY_CORE_ID            0x814   /* 802.11b phy core */
 114 #define GPHY_CORE_ID            0x815   /* 802.11g phy core */
 115 #define MIPS33_CORE_ID          0x816   /* mips3302 core */
 116 #define USB11H_CORE_ID          0x817   /* usb 1.1 host core */
 117 #define USB11D_CORE_ID          0x818   /* usb 1.1 device core */
 118 #define USB20H_CORE_ID          0x819   /* usb 2.0 host core */
 119 #define USB20D_CORE_ID          0x81a   /* usb 2.0 device core */
 120 #define SDIOH_CORE_ID           0x81b   /* sdio host core */
 121 #define ROBO_CORE_ID            0x81c   /* roboswitch core */
 122 #define ATA100_CORE_ID          0x81d   /* parallel ATA core */
 123 #define SATAXOR_CORE_ID         0x81e   /* serial ATA & XOR DMA core */
 124 #define GIGETH_CORE_ID          0x81f   /* gigabit ethernet core */
 125 #define PCIE_CORE_ID            0x820   /* pci express core */
 126 #define NPHY_CORE_ID            0x821   /* 802.11n 2x2 phy core */
 127 #define SRAMC_CORE_ID           0x822   /* SRAM controller core */
 128 #define MINIMAC_CORE_ID         0x823   /* MINI MAC/phy core */
 129 #define ARM11_CORE_ID           0x824   /* ARM 1176 core */
 130 #define ARM7S_CORE_ID           0x825   /* ARM7tdmi-s core */
 131 #define LPPHY_CORE_ID           0x826   /* 802.11a/b/g phy core */
 132 #define PMU_CORE_ID             0x827   /* PMU core */
 133 #define SSNPHY_CORE_ID          0x828   /* 802.11n single-stream phy core */
 134 #define SDIOD_CORE_ID           0x829   /* SDIO device core */
 135 #define ARMCM3_CORE_ID          0x82a   /* ARM Cortex M3 core */
 136 #define HTPHY_CORE_ID           0x82b   /* 802.11n 4x4 phy core */
 137 #define MIPS74K_CORE_ID         0x82c   /* mips 74k core */
 138 #define GMAC_CORE_ID            0x82d   /* Gigabit MAC core */
 139 #define DMEMC_CORE_ID           0x82e   /* DDR1/2 memory controller core */
 140 #define PCIERC_CORE_ID          0x82f   /* PCIE Root Complex core */
 141 #define OCP_CORE_ID             0x830   /* OCP2OCP bridge core */
 142 #define SC_CORE_ID              0x831   /* shared common core */
 143 #define AHB_CORE_ID             0x832   /* OCP2AHB bridge core */
 144 #define SPIH_CORE_ID            0x833   /* SPI host core */
 145 #define I2S_CORE_ID             0x834   /* I2S core */
 146 #define DMEMS_CORE_ID           0x835   /* SDR/DDR1 memory controller core */
 147 #define DEF_SHIM_COMP           0x837   /* SHIM component in ubus/6362 */
 148 #define OOB_ROUTER_CORE_ID      0x367   /* OOB router core ID */
 149 #define DEF_AI_COMP             0xfff   /* Default component, in ai chips it
 150                                          * maps all unused address ranges
 151                                          */
 152
 153 /* chipcommon being the first core: */
 154 #define SI_CC_IDX               0
 155
 156 /* SOC Interconnect types (aka chip types) */
 157 #define SOCI_AI                 1
 158
 159 /* Common core control flags */
 160 #define SICF_BIST_EN            0x8000
 161 #define SICF_PME_EN             0x4000
 162 #define SICF_CORE_BITS          0x3ffc
 163 #define SICF_FGC                0x0002
 164 #define SICF_CLOCK_EN           0x0001
 165
 166 /* Common core status flags */
 167 #define SISF_BIST_DONE          0x8000
 168 #define SISF_BIST_ERROR         0x4000
 169 #define SISF_GATED_CLK          0x2000
 170 #define SISF_DMA64              0x1000
 171 #define SISF_CORE_BITS          0x0fff
 172
 173 /* A register that is common to all cores to
 174  * communicate w/PMU regarding clock control.
 175  */
 176 #define SI_CLK_CTL_ST           0x1e0   /* clock control and status */
 177
 178 /* clk_ctl_st register */
 179 #define CCS_FORCEALP            0x00000001      /* force ALP request */
 180 #define CCS_FORCEHT             0x00000002      /* force HT request */
 181 #define CCS_FORCEILP            0x00000004      /* force ILP request */
 182 #define CCS_ALPAREQ             0x00000008      /* ALP Avail Request */
 183 #define CCS_HTAREQ              0x00000010      /* HT Avail Request */
 184 #define CCS_FORCEHWREQOFF       0x00000020      /* Force HW Clock Request Off */
 185 #define CCS_ERSRC_REQ_MASK      0x00000700      /* external resource requests */
 186 #define CCS_ERSRC_REQ_SHIFT     8
 187 #define CCS_ALPAVAIL            0x00010000      /* ALP is available */
 188 #define CCS_HTAVAIL             0x00020000      /* HT is available */
 189 #define CCS_BP_ON_APL           0x00040000      /* RO: running on ALP clock */
 190 #define CCS_BP_ON_HT            0x00080000      /* RO: running on HT clock */
 191 #define CCS_ERSRC_STS_MASK      0x07000000      /* external resource status */
 192 #define CCS_ERSRC_STS_SHIFT     24
 193
 194 /* HT avail in chipc and pcmcia on 4328a0 */
 195 #define CCS0_HTAVAIL            0x00010000
 196 /* ALP avail in chipc and pcmcia on 4328a0 */
 197 #define CCS0_ALPAVAIL           0x00020000
 198
 199 /* Not really related to SOC Interconnect, but a couple of software
 200  * conventions for the use the flash space:
 201  */
 202
 203 /* Minumum amount of flash we support */
 204 #define FLASH_MIN               0x00020000      /* Minimum flash size */
 205
 206 /* A boot/binary may have an embedded block that describes its size  */
 207 #define BISZ_OFFSET             0x3e0   /* At this offset into the binary */
 208 #define BISZ_MAGIC              0x4249535a      /* Marked with value: 'BISZ' */
 209 #define BISZ_MAGIC_IDX          0       /* Word 0: magic */
 210 #define BISZ_TXTST_IDX          1       /*      1: text start */
 211 #define BISZ_TXTEND_IDX         2       /*      2: text end */
 212 #define BISZ_DATAST_IDX         3       /*      3: data start */
 213 #define BISZ_DATAEND_IDX        4       /*      4: data end */
 214 #define BISZ_BSSST_IDX          5       /*      5: bss start */
 215 #define BISZ_BSSEND_IDX         6       /*      6: bss end */
 216 #define BISZ_SIZE               7       /* descriptor size in 32-bit integers */
 217
 218 #define CC_SROM_OTP             0x800   /* SROM/OTP address space */
 219
 220 /* gpiotimerval */
 221 #define GPIO_ONTIME_SHIFT       16
 222
 223 /* Fields in clkdiv */
 224 #define CLKD_OTP                0x000f0000
 225 #define CLKD_OTP_SHIFT          16
 226
 227 /* When Srom support present, fields in sromcontrol */
 228 #define SRC_START               0x80000000
 229 #define SRC_BUSY                0x80000000
 230 #define SRC_OPCODE              0x60000000
 231 #define SRC_OP_READ             0x00000000
 232 #define SRC_OP_WRITE            0x20000000
 233 #define SRC_OP_WRDIS            0x40000000
 234 #define SRC_OP_WREN             0x60000000
 235 #define SRC_OTPSEL              0x00000010
 236 #define SRC_LOCK                0x00000008
 237 #define SRC_SIZE_MASK           0x00000006
 238 #define SRC_SIZE_1K             0x00000000
 239 #define SRC_SIZE_4K             0x00000002
 240 #define SRC_SIZE_16K            0x00000004
 241 #define SRC_SIZE_SHIFT          1
 242 #define SRC_PRESENT             0x00000001
 243
 244 /* 4330 chip-specific ChipStatus register bits */
 245 #define CST4330_CHIPMODE_SDIOD(cs)      (((cs) & 0x7) < 6)      /* SDIO || gSPI */
 246 #define CST4330_CHIPMODE_USB20D(cs)     (((cs) & 0x7) >= 6)     /* USB || USBDA */
 247 #define CST4330_CHIPMODE_SDIO(cs)       (((cs) & 0x4) == 0)     /* SDIO */
 248 #define CST4330_CHIPMODE_GSPI(cs)       (((cs) & 0x6) == 4)     /* gSPI */
 249 #define CST4330_CHIPMODE_USB(cs)        (((cs) & 0x7) == 6)     /* USB packet-oriented */
 250 #define CST4330_CHIPMODE_USBDA(cs)      (((cs) & 0x7) == 7)     /* USB Direct Access */
 251 #define CST4330_OTP_PRESENT             0x00000010
 252 #define CST4330_LPO_AUTODET_EN          0x00000020
 253 #define CST4330_ARMREMAP_0              0x00000040
 254 #define CST4330_SPROM_PRESENT           0x00000080      /* takes priority over OTP if both set */
 255 #define CST4330_ILPDIV_EN               0x00000100
 256 #define CST4330_LPO_SEL                 0x00000200
 257 #define CST4330_RES_INIT_MODE_SHIFT     10
 258 #define CST4330_RES_INIT_MODE_MASK      0x00000c00
 259 #define CST4330_CBUCK_MODE_SHIFT        12
 260 #define CST4330_CBUCK_MODE_MASK         0x00003000
 261 #define CST4330_CBUCK_POWER_OK          0x00004000
 262 #define CST4330_BB_PLL_LOCKED           0x00008000
 263
 264 /* Package IDs */
 265 #define BCM4329_289PIN_PKG_ID   0       /* 4329 289-pin package id */
 266 #define BCM4329_182PIN_PKG_ID   1       /* 4329N 182-pin package id */
 267 #define BCM4717_PKG_ID          9       /* 4717 package id */
 268 #define BCM4718_PKG_ID          10      /* 4718 package id */
 269 #define HDLSIM_PKG_ID           14      /* HDL simulator package id */
 270 #define HWSIM_PKG_ID            15      /* Hardware simulator package id */
 271 #define BCM43224_FAB_SMIC       0xa     /* the chip is manufactured by SMIC */
 272
 273 /* these are router chips */
 274 #define BCM4716_CHIP_ID         0x4716  /* 4716 chipcommon chipid */
 275 #define BCM47162_CHIP_ID        47162   /* 47162 chipcommon chipid */
 276 #define BCM4748_CHIP_ID         0x4748  /* 4716 chipcommon chipid (OTP, RBBU) */
 277 #define BCM5356_CHIP_ID         0x5356  /* 5356 chipcommon chipid */
 278 #define BCM5357_CHIP_ID         0x5357  /* 5357 chipcommon chipid */
 279
 280
 281 #define SI_INFO(sih)    ((struct si_info *)sih)
 282
 283 #define GOODCOREADDR(x, b) \
 284         (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
 285                 IS_ALIGNED((x), SI_CORE_SIZE))
 286 #define GOODREGS(regs) \
 287         ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
 288 #define BADCOREADDR     0
 289 #define GOODIDX(idx)    (((uint)idx) < SI_MAXCORES)
 290 #define NOREV           -1      /* Invalid rev */
 291
 292 /* Newer chips can access PCI/PCIE and CC core without requiring to change
 293  * PCI BAR0 WIN
 294  */
 295 #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
 296                      (((si)->pub.buscoretype == PCI_CORE_ID) && \
 297                       (si)->pub.buscorerev >= 13))
 298
 299 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
 300 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
 301
 302 /*
 303  * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
 304  * before after core switching to avoid invalid register accesss inside ISR.
 305  */
 306 #define INTR_OFF(si, intr_val) \
 307         if ((si)->intrsoff_fn && \
 308             (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
 309                 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg)
 310 #define INTR_RESTORE(si, intr_val) \
 311         if ((si)->intrsrestore_fn && \
 312             (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
 313                 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val)
 314
 315 /* dynamic clock control defines */
 316 #define LPOMINFREQ              25000   /* low power oscillator min */
 317 #define LPOMAXFREQ              43000   /* low power oscillator max */
 318 #define XTALMINFREQ             19800000        /* 20 MHz - 1% */
 319 #define XTALMAXFREQ             20200000        /* 20 MHz + 1% */
 320 #define PCIMINFREQ              25000000        /* 25 MHz */
 321 #define PCIMAXFREQ              34000000        /* 33 MHz + fudge */
 322
 323 #define ILP_DIV_5MHZ            0       /* ILP = 5 MHz */
 324 #define ILP_DIV_1MHZ            4       /* ILP = 1 MHz */
 325
 326 #define PCI(si)         (((si)->pub.bustype == PCI_BUS) &&      \
 327                          ((si)->pub.buscoretype == PCI_CORE_ID))
 328 #define PCIE(si)        (((si)->pub.bustype == PCI_BUS) &&      \
 329                          ((si)->pub.buscoretype == PCIE_CORE_ID))
 330 #define PCI_FORCEHT(si) \
 331         (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
 332
 333 /* GPIO Based LED powersave defines */
 334 #define DEFAULT_GPIO_ONTIME     10      /* Default: 10% on */
 335 #define DEFAULT_GPIO_OFFTIME    90      /* Default: 10% on */
 336
 337 #ifndef DEFAULT_GPIOTIMERVAL
 338 #define DEFAULT_GPIOTIMERVAL \
 339         ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
 340 #endif
 341
 342 /*
 343  * Data structure to export all chip specific common variables
 344  *   public (read-only) portion of aiutils handle returned by si_attach()
 345  */
 346 struct si_pub {
 347         uint bustype;           /* SI_BUS, PCI_BUS */
 348         uint buscoretype;       /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
 349         uint buscorerev;        /* buscore rev */
 350         uint buscoreidx;        /* buscore index */
 351         int ccrev;              /* chip common core rev */
 352         u32 cccaps;             /* chip common capabilities */
 353         u32 cccaps_ext; /* chip common capabilities extension */
 354         int pmurev;             /* pmu core rev */
 355         u32 pmucaps;            /* pmu capabilities */
 356         uint boardtype;         /* board type */
 357         uint boardvendor;       /* board vendor */
 358         uint boardflags;        /* board flags */
 359         uint boardflags2;       /* board flags2 */
 360         uint chip;              /* chip number */
 361         uint chiprev;           /* chip revision */
 362         uint chippkg;           /* chip package option */
 363         u32 chipst;             /* chip status */
 364         bool issim;             /* chip is in simulation or emulation */
 365         uint socirev;           /* SOC interconnect rev */
 366         bool pci_pr32414;
 367
 368 };
 369
 370 /*
 371  * Many of the routines below take an 'sih' handle as their first arg.
 372  * Allocate this by calling si_attach().  Free it by calling si_detach().
 373  * At any one time, the sih is logically focused on one particular si core
 374  * (the "current core").
 375  * Use si_setcore() or si_setcoreidx() to change the association to another core
 376  */
 377
 378 #define BADIDX          (SI_MAXCORES + 1)
 379
 380 /* clkctl xtal what flags */
 381 #define XTAL                    0x1     /* primary crystal oscillator (2050) */
 382 #define PLL                     0x2     /* main chip pll */
 383
 384 /* clkctl clk mode */
 385 #define CLK_FAST                0       /* force fast (pll) clock */
 386 #define CLK_DYNAMIC             2       /* enable dynamic clock control */
 387
 388 /* GPIO usage priorities */
 389 #define GPIO_DRV_PRIORITY       0       /* Driver */
 390 #define GPIO_APP_PRIORITY       1       /* Application */
 391 #define GPIO_HI_PRIORITY        2       /* Highest priority. Ignore GPIO
 392                                          * reservation
 393                                          */
 394
 395 /* GPIO pull up/down */
 396 #define GPIO_PULLUP             0
 397 #define GPIO_PULLDN             1
 398
 399 /* GPIO event regtype */
 400 #define GPIO_REGEVT             0       /* GPIO register event */
 401 #define GPIO_REGEVT_INTMSK      1       /* GPIO register event int mask */
 402 #define GPIO_REGEVT_INTPOL      2       /* GPIO register event int polarity */
 403
 404 /* device path */
 405 #define SI_DEVPATH_BUFSZ        16      /* min buffer size in bytes */
 406
 407 /* SI routine enumeration: to be used by update function with multiple hooks */
 408 #define SI_DOATTACH     1
 409 #define SI_PCIDOWN      2
 410 #define SI_PCIUP        3
 411
 412 /* PMU clock/power control */
 413 #if defined(BCMPMUCTL)
 414 #define PMUCTL_ENAB(sih)        (BCMPMUCTL)
 415 #else
 416 #define PMUCTL_ENAB(sih)        ((sih)->cccaps & CC_CAP_PMU)
 417 #endif
 418
 419 /* chipcommon clock/power control (exclusive with PMU's) */
 420 #if defined(BCMPMUCTL) && BCMPMUCTL
 421 #define CCCTL_ENAB(sih)         (0)
 422 #define CCPLL_ENAB(sih)         (0)
 423 #else
 424 #define CCCTL_ENAB(sih)         ((sih)->cccaps & CC_CAP_PWR_CTL)
 425 #define CCPLL_ENAB(sih)         ((sih)->cccaps & CC_CAP_PLL_MASK)
 426 #endif
 427
 428 typedef void (*gpio_handler_t) (u32 stat, void *arg);
 429
 430 /* External PA enable mask */
 431 #define GPIO_CTRL_EPA_EN_MASK 0x40
 432
 433 #define SI_ERROR(args)
 434
 435 #ifdef BCMDBG
 436 #define SI_MSG(args)    printk args
 437 #else
 438 #define SI_MSG(args)
 439 #endif                          /* BCMDBG */
 440
 441 /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
 442 #define SI_VMSG(args)
 443
 444 #define IS_SIM(chippkg) \
 445         ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
 446
 447 typedef u32(*si_intrsoff_t) (void *intr_arg);
 448 typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
 449 typedef bool(*si_intrsenabled_t) (void *intr_arg);
 450
 451 struct gpioh_item {
 452         void *arg;
 453         bool level;
 454         gpio_handler_t handler;
 455         u32 event;
 456         struct gpioh_item *next;
 457 };
 458
 459 /* misc si info needed by some of the routines */
 460 struct si_info {
 461         struct si_pub pub;      /* back plane public state (must be first) */
 462         void *pbus;             /* handle to bus (pci/sdio/..) */
 463         uint dev_coreid;        /* the core provides driver functions */
 464         void *intr_arg;         /* interrupt callback function arg */
 465         si_intrsoff_t intrsoff_fn;      /* turns chip interrupts off */
 466         si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
 467         si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
 468
 469         void *pch;              /* PCI/E core handle */
 470
 471         char *vars;
 472         uint varsz;
 473
 474         void *curmap;           /* current regs va */
 475         void *regs[SI_MAXCORES];        /* other regs va */
 476
 477         uint curidx;            /* current core index */
 478         uint numcores;          /* # discovered cores */
 479         uint coreid[SI_MAXCORES]; /* id of each core */
 480         u32 coresba[SI_MAXCORES]; /* backplane address of each core */
 481         void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
 482         u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
 483         u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
 484         u32 coresba2_size[SI_MAXCORES]; /* second address space size */
 485
 486         void *curwrap;          /* current wrapper va */
 487         void *wrappers[SI_MAXCORES];    /* other cores wrapper va */
 488         u32 wrapba[SI_MAXCORES];        /* address of controlling wrapper */
 489
 490         u32 cia[SI_MAXCORES];   /* erom cia entry for each core */
 491         u32 cib[SI_MAXCORES];   /* erom cia entry for each core */
 492         u32 oob_router; /* oob router registers for axi */
 493 };
 494
 495 /* AMBA Interconnect exported externs */
 496 extern void ai_scan(struct si_pub *sih, void *regs);
 497
 498 extern uint ai_flag(struct si_pub *sih);
 499 extern void ai_setint(struct si_pub *sih, int siflag);
 500 extern uint ai_coreidx(struct si_pub *sih);
 501 extern uint ai_corevendor(struct si_pub *sih);
 502 extern uint ai_corerev(struct si_pub *sih);
 503 extern bool ai_iscoreup(struct si_pub *sih);
 504 extern void *ai_setcoreidx(struct si_pub *sih, uint coreidx);
 505 extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
 506 extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
 507 extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
 508 extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
 509                        uint val);
 510 extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
 511 extern void ai_core_disable(struct si_pub *sih, u32 bits);
 512 extern int ai_numaddrspaces(struct si_pub *sih);
 513 extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
 514 extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
 515 extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
 516
 517 /* === exported functions === */
 518 extern struct si_pub *ai_attach(void *regs, uint bustype,
 519                        void *sdh, char **vars, uint *varsz);
 520
 521 extern void ai_detach(struct si_pub *sih);
 522 extern bool ai_pci_war16165(struct si_pub *sih);
 523
 524 extern uint ai_coreid(struct si_pub *sih);
 525 extern uint ai_corerev(struct si_pub *sih);
 526 extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
 527                 uint val);
 528 extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
 529 extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
 530 extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
 531 extern bool ai_iscoreup(struct si_pub *sih);
 532 extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
 533 extern void *ai_setcoreidx(struct si_pub *sih, uint coreidx);
 534 extern void *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
 535 extern void *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
 536                             uint *intr_val);
 537 extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
 538 extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
 539 extern void ai_core_disable(struct si_pub *sih, u32 bits);
 540 extern u32 ai_alp_clock(struct si_pub *sih);
 541 extern u32 ai_ilp_clock(struct si_pub *sih);
 542 extern void ai_pci_setup(struct si_pub *sih, uint coremask);
 543 extern void ai_setint(struct si_pub *sih, int siflag);
 544 extern bool ai_backplane64(struct si_pub *sih);
 545 extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
 546                                       void *intrsrestore_fn,
 547                                       void *intrsenabled_fn, void *intr_arg);
 548 extern void ai_deregister_intr_callback(struct si_pub *sih);
 549 extern void ai_clkctl_init(struct si_pub *sih);
 550 extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
 551 extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
 552 extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
 553 extern bool ai_deviceremoved(struct si_pub *sih);
 554 extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
 555                              u8 priority);
 556
 557 /* OTP status */
 558 extern bool ai_is_otp_disabled(struct si_pub *sih);
 559
 560 /* SPROM availability */
 561 extern bool ai_is_sprom_available(struct si_pub *sih);
 562
 563 /*
 564  * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
 565  * The returned path is NULL terminated and has trailing '/'.
 566  * Return 0 on success, nonzero otherwise.
 567  */
 568 extern int ai_devpath(struct si_pub *sih, char *path, int size);
 569 /* Read variable with prepending the devpath to the name */
 570 extern char *ai_getdevpathvar(struct si_pub *sih, const char *name);
 571 extern int ai_getdevpathintvar(struct si_pub *sih, const char *name);
 572
 573 extern void ai_pci_sleep(struct si_pub *sih);
 574 extern void ai_pci_down(struct si_pub *sih);
 575 extern void ai_pci_up(struct si_pub *sih);
 576 extern int ai_pci_fixcfg(struct si_pub *sih);
 577
 578 extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
 579 /* Enable Ex-PA for 4313 */
 580 extern void ai_epa_4313war(struct si_pub *sih);
 581
 582 char *ai_getnvramflvar(struct si_pub *sih, const char *name);
 583
 584 #endif                          /* _BRCM_AIUTILS_H_ */