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sysfs: Remove support for tagged directories with untagged members (again)
[linux-btrfs-devel.git] / drivers / staging / brcm80211 / brcmsmac / dma.c
blobea17671efb63aa0c9556c8e46c842734ba398f86
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include <linux/slab.h>
17 #include <linux/skbuff.h>
18 #include <linux/delay.h>
19 #include <linux/pci.h>
20
21 #if defined(__mips__)
22 #include <asm/addrspace.h>
23 #endif
24
25 #include <brcmu_utils.h>
26 #include <aiutils.h>
27 #include "types.h"
28 #include "dma.h"
29
30 /*
31 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical address.
32 */
33 #define D64RINGALIGN_BITS 13
34 #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
35 #define D64RINGALIGN (1 << D64RINGALIGN_BITS)
36
37 #define D64MAXDD (D64MAXRINGSZ / sizeof(struct dma64desc))
38
39 /* transmit channel control */
40 #define D64_XC_XE 0x00000001 /* transmit enable */
41 #define D64_XC_SE 0x00000002 /* transmit suspend request */
42 #define D64_XC_LE 0x00000004 /* loopback enable */
43 #define D64_XC_FL 0x00000010 /* flush request */
44 #define D64_XC_PD 0x00000800 /* parity check disable */
45 #define D64_XC_AE 0x00030000 /* address extension bits */
46 #define D64_XC_AE_SHIFT 16
47
48 /* transmit descriptor table pointer */
49 #define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
50
51 /* transmit channel status */
52 #define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
53 #define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
54 #define D64_XS0_XS_SHIFT 28
55 #define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
56 #define D64_XS0_XS_ACTIVE 0x10000000 /* active */
57 #define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
58 #define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
59 #define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
60
61 #define D64_XS1_AD_MASK 0x00001fff /* active descriptor */
62 #define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
63 #define D64_XS1_XE_SHIFT 28
64 #define D64_XS1_XE_NOERR 0x00000000 /* no error */
65 #define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
66 #define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
67 #define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
68 #define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
69 #define D64_XS1_XE_COREE 0x50000000 /* core error */
70
71 /* receive channel control */
72 #define D64_RC_RE 0x00000001 /* receive enable */
73 #define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
74 #define D64_RC_RO_SHIFT 1
75 #define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
76 #define D64_RC_SH 0x00000200 /* separate rx header descriptor enable */
77 #define D64_RC_OC 0x00000400 /* overflow continue */
78 #define D64_RC_PD 0x00000800 /* parity check disable */
79 #define D64_RC_AE 0x00030000 /* address extension bits */
80 #define D64_RC_AE_SHIFT 16
81
82 /* flags for dma controller */
83 #define DMA_CTRL_PEN (1 << 0) /* partity enable */
84 #define DMA_CTRL_ROC (1 << 1) /* rx overflow continue */
85 #define DMA_CTRL_RXMULTI (1 << 2) /* allow rx scatter to multiple descriptors */
86 #define DMA_CTRL_UNFRAMED (1 << 3) /* Unframed Rx/Tx data */
87
88 /* receive descriptor table pointer */
89 #define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
90
91 /* receive channel status */
92 #define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
93 #define D64_RS0_RS_MASK 0xf0000000 /* receive state */
94 #define D64_RS0_RS_SHIFT 28
95 #define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
96 #define D64_RS0_RS_ACTIVE 0x10000000 /* active */
97 #define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
98 #define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
99 #define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
100
101 #define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
102 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
103 #define D64_RS1_RE_SHIFT 28
104 #define D64_RS1_RE_NOERR 0x00000000 /* no error */
105 #define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
106 #define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
107 #define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
108 #define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
109 #define D64_RS1_RE_COREE 0x50000000 /* core error */
110
111 /* fifoaddr */
112 #define D64_FA_OFF_MASK 0xffff /* offset */
113 #define D64_FA_SEL_MASK 0xf0000 /* select */
114 #define D64_FA_SEL_SHIFT 16
115 #define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
116 #define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
117 #define D64_FA_SEL_RDD 0x40000 /* receive dma data */
118 #define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
119 #define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
120 #define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
121 #define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
122 #define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
123 #define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
124 #define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
125
126 /* descriptor control flags 1 */
127 #define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */
128 #define D64_CTRL1_EOT ((u32)1 << 28) /* end of descriptor table */
129 #define D64_CTRL1_IOC ((u32)1 << 29) /* interrupt on completion */
130 #define D64_CTRL1_EOF ((u32)1 << 30) /* end of frame */
131 #define D64_CTRL1_SOF ((u32)1 << 31) /* start of frame */
132
133 /* descriptor control flags 2 */
134 #define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */
135 #define D64_CTRL2_AE 0x00030000 /* address extension bits */
136 #define D64_CTRL2_AE_SHIFT 16
137 #define D64_CTRL2_PARITY 0x00040000 /* parity bit */
138
139 /* control flags in the range [27:20] are core-specific and not defined here */
140 #define D64_CTRL_CORE_MASK 0x0ff00000
141
142 #define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */
143 #define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */
144 #define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1 */
145 #define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */
146
147 #define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
148 #define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
149 #define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
150 #define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
151
152 /* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
153 * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
154 * There is a compile time check in wlc.c which ensure that this value is at least as big
155 * as TXOFF. This value is used in dma_rxfill (dma.c).
156 */
157
158 #define BCMEXTRAHDROOM 172
159
160 /* debug/trace */
161 #ifdef BCMDBG
162 #define DMA_ERROR(args) \
163 do { \
164 if (!(*di->msg_level & 1)) \
165 ; \
166 else \
167 printk args; \
168 } while (0)
169 #define DMA_TRACE(args) \
170 do { \
171 if (!(*di->msg_level & 2)) \
172 ; \
173 else \
174 printk args; \
175 } while (0)
176 #else
177 #define DMA_ERROR(args)
178 #define DMA_TRACE(args)
179 #endif /* BCMDBG */
180
181 #define DMA_NONE(args)
182
183 typedef unsigned long dmaaddr_t;
184 #define PHYSADDRHI(_pa) (0)
185 #define PHYSADDRHISET(_pa, _val)
186 #define PHYSADDRLO(_pa) ((_pa))
187 #define PHYSADDRLOSET(_pa, _val) \
188 do { \
189 (_pa) = (_val); \
190 } while (0)
191
192 #define d64txregs dregs.d64_u.txregs_64
193 #define d64rxregs dregs.d64_u.rxregs_64
194 #define txd64 dregs.d64_u.txd_64
195 #define rxd64 dregs.d64_u.rxd_64
196
197 /* default dma message level (if input msg_level pointer is null in dma_attach()) */
198 static uint dma_msg_level;
199
200 #define MAXNAMEL 8 /* 8 char names */
201
202 #define DI_INFO(dmah) ((dma_info_t *)dmah)
203
204 #define R_SM(r) (*(r))
205 #define W_SM(r, v) (*(r) = (v))
206
207 /* One physical DMA segment */
208 struct dma_seg {
209 dmaaddr_t addr;
210 u32 length;
211 };
212
213 struct dma_seg_map {
214 void *oshdmah; /* Opaque handle for OSL to store its information */
215 uint origsize; /* Size of the virtual packet */
216 uint nsegs;
217 struct dma_seg segs[MAX_DMA_SEGS];
218 };
219
220 /*
221 * DMA Descriptor
222 * Descriptors are only read by the hardware, never written back.
223 */
224 struct dma64desc {
225 u32 ctrl1; /* misc control bits & bufcount */
226 u32 ctrl2; /* buffer count and address extension */
227 u32 addrlow; /* memory address of the date buffer, bits 31:0 */
228 u32 addrhigh; /* memory address of the date buffer, bits 63:32 */
229 };
230
231 /* dma engine software state */
232 struct dma_info {
233 struct dma_pub dma; /* exported structure */
234 uint *msg_level; /* message level pointer */
235 char name[MAXNAMEL]; /* callers name for diag msgs */
236
237 void *pbus; /* bus handle */
238
239 bool dma64; /* this dma engine is operating in 64-bit mode */
240 bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
241
242 union {
243 struct {
244 dma64regs_t *txregs_64; /* 64-bit dma tx engine registers */
245 dma64regs_t *rxregs_64; /* 64-bit dma rx engine registers */
246 /* pointer to dma64 tx descriptor ring */
247 struct dma64desc *txd_64;
248 /* pointer to dma64 rx descriptor ring */
249 struct dma64desc *rxd_64;
250 } d64_u;
251 } dregs;
252
253 u16 dmadesc_align; /* alignment requirement for dma descriptors */
254
255 u16 ntxd; /* # tx descriptors tunable */
256 u16 txin; /* index of next descriptor to reclaim */
257 u16 txout; /* index of next descriptor to post */
258 void **txp; /* pointer to parallel array of pointers to packets */
259 struct dma_seg_map *txp_dmah; /* DMA MAP meta-data handle */
260 dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */
261 dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */
262 u16 txdalign; /* #bytes added to alloc'd mem to align txd */
263 u32 txdalloc; /* #bytes allocated for the ring */
264 u32 xmtptrbase; /* When using unaligned descriptors, the ptr register
265 * is not just an index, it needs all 13 bits to be
266 * an offset from the addr register.
267 */
268
269 u16 nrxd; /* # rx descriptors tunable */
270 u16 rxin; /* index of next descriptor to reclaim */
271 u16 rxout; /* index of next descriptor to post */
272 void **rxp; /* pointer to parallel array of pointers to packets */
273 struct dma_seg_map *rxp_dmah; /* DMA MAP meta-data handle */
274 dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */
275 dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */
276 u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */
277 u32 rxdalloc; /* #bytes allocated for the ring */
278 u32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */
279
280 /* tunables */
281 unsigned int rxbufsize; /* rx buffer size in bytes,
282 * not including the extra headroom
283 */
284 uint rxextrahdrroom; /* extra rx headroom, reverseved to assist upper stack
285 * e.g. some rx pkt buffers will be bridged to tx side
286 * without byte copying. The extra headroom needs to be
287 * large enough to fit txheader needs.
288 * Some dongle driver may not need it.
289 */
290 uint nrxpost; /* # rx buffers to keep posted */
291 unsigned int rxoffset; /* rxcontrol offset */
292 uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
293 uint ddoffsethigh; /* high 32 bits */
294 uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
295 uint dataoffsethigh; /* high 32 bits */
296 bool aligndesc_4k; /* descriptor base need to be aligned or not */
297 };
298
299 /* DMA Scatter-gather list is supported. Note this is limited to TX direction only */
300 #ifdef BCMDMASGLISTOSL
301 #define DMASGLIST_ENAB true
302 #else
303 #define DMASGLIST_ENAB false
304 #endif /* BCMDMASGLISTOSL */
305
306 /* descriptor bumping macros */
307 #define XXD(x, n) ((x) & ((n) - 1)) /* faster than %, but n must be power of 2 */
308 #define TXD(x) XXD((x), di->ntxd)
309 #define RXD(x) XXD((x), di->nrxd)
310 #define NEXTTXD(i) TXD((i) + 1)
311 #define PREVTXD(i) TXD((i) - 1)
312 #define NEXTRXD(i) RXD((i) + 1)
313 #define PREVRXD(i) RXD((i) - 1)
314
315 #define NTXDACTIVE(h, t) TXD((t) - (h))
316 #define NRXDACTIVE(h, t) RXD((t) - (h))
317
318 /* macros to convert between byte offsets and indexes */
319 #define B2I(bytes, type) ((bytes) / sizeof(type))
320 #define I2B(index, type) ((index) * sizeof(type))
321
322 #define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
323 #define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
324
325 #define PCI64ADDR_HIGH 0x80000000 /* address[63] */
326 #define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
327
328 /* Common prototypes */
329 static bool _dma_isaddrext(struct dma_info *di);
330 static bool _dma_descriptor_align(struct dma_info *di);
331 static bool _dma_alloc(struct dma_info *di, uint direction);
332 static void _dma_detach(struct dma_info *di);
333 static void _dma_ddtable_init(struct dma_info *di, uint direction,
334 dmaaddr_t pa);
335 static void _dma_rxinit(struct dma_info *di);
336 static void *_dma_rx(struct dma_info *di);
337 static bool _dma_rxfill(struct dma_info *di);
338 static void _dma_rxreclaim(struct dma_info *di);
339 static void _dma_rxenable(struct dma_info *di);
340 static void *_dma_getnextrxp(struct dma_info *di, bool forceall);
341 static void _dma_rx_param_get(struct dma_info *di, u16 *rxoffset,
342 u16 *rxbufsize);
343
344 static void _dma_txblock(struct dma_info *di);
345 static void _dma_txunblock(struct dma_info *di);
346 static uint _dma_txactive(struct dma_info *di);
347 static uint _dma_rxactive(struct dma_info *di);
348 static uint _dma_txpending(struct dma_info *di);
349 static uint _dma_txcommitted(struct dma_info *di);
350
351 static void *_dma_peeknexttxp(struct dma_info *di);
352 static void *_dma_peeknextrxp(struct dma_info *di);
353 static unsigned long _dma_getvar(struct dma_info *di, const char *name);
354 static void _dma_counterreset(struct dma_info *di);
355 static void _dma_fifoloopbackenable(struct dma_info *di);
356 static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags);
357 static u8 dma_align_sizetobits(uint size);
358 static void *dma_ringalloc(struct dma_info *di, u32 boundary, uint size,
359 u16 *alignbits, uint *alloced,
360 dmaaddr_t *descpa);
361
362 /* Prototypes for 64-bit routines */
363 static bool dma64_alloc(struct dma_info *di, uint direction);
364 static bool dma64_txreset(struct dma_info *di);
365 static bool dma64_rxreset(struct dma_info *di);
366 static bool dma64_txsuspendedidle(struct dma_info *di);
367 static int dma64_txfast(struct dma_info *di, struct sk_buff *p0, bool commit);
368 static int dma64_txunframed(struct dma_info *di, void *p0, uint len,
369 bool commit);
370 static void *dma64_getpos(struct dma_info *di, bool direction);
371 static void *dma64_getnexttxp(struct dma_info *di, enum txd_range range);
372 static void *dma64_getnextrxp(struct dma_info *di, bool forceall);
373 static void dma64_txrotate(struct dma_info *di);
374
375 static bool dma64_rxidle(struct dma_info *di);
376 static void dma64_txinit(struct dma_info *di);
377 static bool dma64_txenabled(struct dma_info *di);
378 static void dma64_txsuspend(struct dma_info *di);
379 static void dma64_txresume(struct dma_info *di);
380 static bool dma64_txsuspended(struct dma_info *di);
381 static void dma64_txreclaim(struct dma_info *di, enum txd_range range);
382 static bool dma64_txstopped(struct dma_info *di);
383 static bool dma64_rxstopped(struct dma_info *di);
384 static bool dma64_rxenabled(struct dma_info *di);
385 static bool _dma64_addrext(dma64regs_t *dma64regs);
386
387 static inline u32 parity32(u32 data);
388
389 const struct di_fcn_s dma64proc = {
390 (di_detach_t) _dma_detach,
391 (di_txinit_t) dma64_txinit,
392 (di_txreset_t) dma64_txreset,
393 (di_txenabled_t) dma64_txenabled,
394 (di_txsuspend_t) dma64_txsuspend,
395 (di_txresume_t) dma64_txresume,
396 (di_txsuspended_t) dma64_txsuspended,
397 (di_txsuspendedidle_t) dma64_txsuspendedidle,
398 (di_txfast_t) dma64_txfast,
399 (di_txunframed_t) dma64_txunframed,
400 (di_getpos_t) dma64_getpos,
401 (di_txstopped_t) dma64_txstopped,
402 (di_txreclaim_t) dma64_txreclaim,
403 (di_getnexttxp_t) dma64_getnexttxp,
404 (di_peeknexttxp_t) _dma_peeknexttxp,
405 (di_txblock_t) _dma_txblock,
406 (di_txunblock_t) _dma_txunblock,
407 (di_txactive_t) _dma_txactive,
408 (di_txrotate_t) dma64_txrotate,
409
410 (di_rxinit_t) _dma_rxinit,
411 (di_rxreset_t) dma64_rxreset,
412 (di_rxidle_t) dma64_rxidle,
413 (di_rxstopped_t) dma64_rxstopped,
414 (di_rxenable_t) _dma_rxenable,
415 (di_rxenabled_t) dma64_rxenabled,
416 (di_rx_t) _dma_rx,
417 (di_rxfill_t) _dma_rxfill,
418 (di_rxreclaim_t) _dma_rxreclaim,
419 (di_getnextrxp_t) _dma_getnextrxp,
420 (di_peeknextrxp_t) _dma_peeknextrxp,
421 (di_rxparam_get_t) _dma_rx_param_get,
422
423 (di_fifoloopbackenable_t) _dma_fifoloopbackenable,
424 (di_getvar_t) _dma_getvar,
425 (di_counterreset_t) _dma_counterreset,
426 (di_ctrlflags_t) _dma_ctrlflags,
427 NULL,
428 NULL,
429 NULL,
430 (di_rxactive_t) _dma_rxactive,
431 (di_txpending_t) _dma_txpending,
432 (di_txcommitted_t) _dma_txcommitted,
433 39
434 };
435
436 struct dma_pub *dma_attach(char *name, struct si_pub *sih,
437 void *dmaregstx, void *dmaregsrx, uint ntxd,
438 uint nrxd, uint rxbufsize, int rxextheadroom,
439 uint nrxpost, uint rxoffset, uint *msg_level)
440 {
441 struct dma_info *di;
442 uint size;
443
444 /* allocate private info structure */
445 di = kzalloc(sizeof(struct dma_info), GFP_ATOMIC);
446 if (di == NULL) {
447 #ifdef BCMDBG
448 printk(KERN_ERR "dma_attach: out of memory\n");
449 #endif
450 return NULL;
451 }
452
453 di->msg_level = msg_level ? msg_level : &dma_msg_level;
454
455
456 di->dma64 = ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
457
458 /* init dma reg pointer */
459 di->d64txregs = (dma64regs_t *) dmaregstx;
460 di->d64rxregs = (dma64regs_t *) dmaregsrx;
461 di->dma.di_fn = (const struct di_fcn_s *)&dma64proc;
462
463 /* Default flags (which can be changed by the driver calling dma_ctrlflags
464 * before enable): For backwards compatibility both Rx Overflow Continue
465 * and Parity are DISABLED.
466 * supports it.
467 */
468 di->dma.di_fn->ctrlflags(&di->dma, DMA_CTRL_ROC | DMA_CTRL_PEN,
469 0);
470
471 DMA_TRACE(("%s: dma_attach: %s flags 0x%x ntxd %d nrxd %d "
472 "rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
473 "dmaregstx %p dmaregsrx %p\n", name, "DMA64",
474 di->dma.dmactrlflags, ntxd, nrxd, rxbufsize,
475 rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx));
476
477 /* make a private copy of our callers name */
478 strncpy(di->name, name, MAXNAMEL);
479 di->name[MAXNAMEL - 1] = '\0';
480
481 di->pbus = ((struct si_info *)sih)->pbus;
482
483 /* save tunables */
484 di->ntxd = (u16) ntxd;
485 di->nrxd = (u16) nrxd;
486
487 /* the actual dma size doesn't include the extra headroom */
488 di->rxextrahdrroom =
489 (rxextheadroom == -1) ? BCMEXTRAHDROOM : rxextheadroom;
490 if (rxbufsize > BCMEXTRAHDROOM)
491 di->rxbufsize = (u16) (rxbufsize - di->rxextrahdrroom);
492 else
493 di->rxbufsize = (u16) rxbufsize;
494
495 di->nrxpost = (u16) nrxpost;
496 di->rxoffset = (u8) rxoffset;
497
498 /*
499 * figure out the DMA physical address offset for dd and data
500 * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
501 * Other bus: use zero
502 * SI_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
503 */
504 di->ddoffsetlow = 0;
505 di->dataoffsetlow = 0;
506 /* for pci bus, add offset */
507 if (sih->bustype == PCI_BUS) {
508 /* pcie with DMA64 */
509 di->ddoffsetlow = 0;
510 di->ddoffsethigh = SI_PCIE_DMA_H32;
511 di->dataoffsetlow = di->ddoffsetlow;
512 di->dataoffsethigh = di->ddoffsethigh;
513 }
514 #if defined(__mips__) && defined(IL_BIGENDIAN)
515 di->dataoffsetlow = di->dataoffsetlow + SI_SDRAM_SWAPPED;
516 #endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
517 /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
518 if ((ai_coreid(sih) == SDIOD_CORE_ID)
519 && ((ai_corerev(sih) > 0) && (ai_corerev(sih) <= 2)))
520 di->addrext = 0;
521 else if ((ai_coreid(sih) == I2S_CORE_ID) &&
522 ((ai_corerev(sih) == 0) || (ai_corerev(sih) == 1)))
523 di->addrext = 0;
524 else
525 di->addrext = _dma_isaddrext(di);
526
527 /* does the descriptors need to be aligned and if yes, on 4K/8K or not */
528 di->aligndesc_4k = _dma_descriptor_align(di);
529 if (di->aligndesc_4k) {
530 di->dmadesc_align = D64RINGALIGN_BITS;
531 if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
532 /* for smaller dd table, HW relax alignment reqmnt */
533 di->dmadesc_align = D64RINGALIGN_BITS - 1;
534 }
535 } else
536 di->dmadesc_align = 4; /* 16 byte alignment */
537
538 DMA_NONE(("DMA descriptor align_needed %d, align %d\n",
539 di->aligndesc_4k, di->dmadesc_align));
540
541 /* allocate tx packet pointer vector */
542 if (ntxd) {
543 size = ntxd * sizeof(void *);
544 di->txp = kzalloc(size, GFP_ATOMIC);
545 if (di->txp == NULL) {
546 DMA_ERROR(("%s: dma_attach: out of tx memory\n", di->name));
547 goto fail;
548 }
549 }
550
551 /* allocate rx packet pointer vector */
552 if (nrxd) {
553 size = nrxd * sizeof(void *);
554 di->rxp = kzalloc(size, GFP_ATOMIC);
555 if (di->rxp == NULL) {
556 DMA_ERROR(("%s: dma_attach: out of rx memory\n", di->name));
557 goto fail;
558 }
559 }
560
561 /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
562 if (ntxd) {
563 if (!_dma_alloc(di, DMA_TX))
564 goto fail;
565 }
566
567 /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
568 if (nrxd) {
569 if (!_dma_alloc(di, DMA_RX))
570 goto fail;
571 }
572
573 if ((di->ddoffsetlow != 0) && !di->addrext) {
574 if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) {
575 DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->txdpa)));
576 goto fail;
577 }
578 if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) {
579 DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->rxdpa)));
580 goto fail;
581 }
582 }
583
584 DMA_TRACE(("ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x dataoffsethigh " "0x%x addrext %d\n", di->ddoffsetlow, di->ddoffsethigh, di->dataoffsetlow, di->dataoffsethigh, di->addrext));
585
586 /* allocate DMA mapping vectors */
587 if (DMASGLIST_ENAB) {
588 if (ntxd) {
589 size = ntxd * sizeof(struct dma_seg_map);
590 di->txp_dmah = kzalloc(size, GFP_ATOMIC);
591 if (di->txp_dmah == NULL)
592 goto fail;
593 }
594
595 if (nrxd) {
596 size = nrxd * sizeof(struct dma_seg_map);
597 di->rxp_dmah = kzalloc(size, GFP_ATOMIC);
598 if (di->rxp_dmah == NULL)
599 goto fail;
600 }
601 }
602
603 return (struct dma_pub *) di;
604
605 fail:
606 _dma_detach(di);
607 return NULL;
608 }
609
610 /* Check for odd number of 1's */
611 static inline u32 parity32(u32 data)
612 {
613 data ^= data >> 16;
614 data ^= data >> 8;
615 data ^= data >> 4;
616 data ^= data >> 2;
617 data ^= data >> 1;
618
619 return data & 1;
620 }
621
622 #define DMA64_DD_PARITY(dd) parity32((dd)->addrlow ^ (dd)->addrhigh ^ (dd)->ctrl1 ^ (dd)->ctrl2)
623
624 static inline void
625 dma64_dd_upd(struct dma_info *di, struct dma64desc *ddring,
626 dmaaddr_t pa, uint outidx, u32 *flags, u32 bufcount)
627 {
628 u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
629
630 /* PCI bus with big(>1G) physical address, use address extension */
631 #if defined(__mips__) && defined(IL_BIGENDIAN)
632 if ((di->dataoffsetlow == SI_SDRAM_SWAPPED)
633 || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
634 #else
635 if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
636 #endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
637
638 W_SM(&ddring[outidx].addrlow,
639 BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
640 W_SM(&ddring[outidx].addrhigh,
641 BUS_SWAP32(PHYSADDRHI(pa) + di->dataoffsethigh));
642 W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
643 W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
644 } else {
645 /* address extension for 32-bit PCI */
646 u32 ae;
647
648 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
649 PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
650
651 ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
652 W_SM(&ddring[outidx].addrlow,
653 BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
654 W_SM(&ddring[outidx].addrhigh,
655 BUS_SWAP32(0 + di->dataoffsethigh));
656 W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
657 W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
658 }
659 if (di->dma.dmactrlflags & DMA_CTRL_PEN) {
660 if (DMA64_DD_PARITY(&ddring[outidx])) {
661 W_SM(&ddring[outidx].ctrl2,
662 BUS_SWAP32(ctrl2 | D64_CTRL2_PARITY));
663 }
664 }
665 }
666
667 static bool _dma_alloc(struct dma_info *di, uint direction)
668 {
669 return dma64_alloc(di, direction);
670 }
671
672 void *dma_alloc_consistent(struct pci_dev *pdev, uint size, u16 align_bits,
673 uint *alloced, unsigned long *pap)
674 {
675 if (align_bits) {
676 u16 align = (1 << align_bits);
677 if (!IS_ALIGNED(PAGE_SIZE, align))
678 size += align;
679 *alloced = size;
680 }
681 return pci_alloc_consistent(pdev, size, (dma_addr_t *) pap);
682 }
683
684 /* !! may be called with core in reset */
685 static void _dma_detach(struct dma_info *di)
686 {
687
688 DMA_TRACE(("%s: dma_detach\n", di->name));
689
690 /* free dma descriptor rings */
691 if (di->txd64)
692 pci_free_consistent(di->pbus, di->txdalloc,
693 ((s8 *)di->txd64 - di->txdalign),
694 (di->txdpaorig));
695 if (di->rxd64)
696 pci_free_consistent(di->pbus, di->rxdalloc,
697 ((s8 *)di->rxd64 - di->rxdalign),
698 (di->rxdpaorig));
699
700 /* free packet pointer vectors */
701 kfree(di->txp);
702 kfree(di->rxp);
703
704 /* free tx packet DMA handles */
705 kfree(di->txp_dmah);
706
707 /* free rx packet DMA handles */
708 kfree(di->rxp_dmah);
709
710 /* free our private info structure */
711 kfree(di);
712
713 }
714
715 static bool _dma_descriptor_align(struct dma_info *di)
716 {
717 u32 addrl;
718
719 /* Check to see if the descriptors need to be aligned on 4K/8K or not */
720 if (di->d64txregs != NULL) {
721 W_REG(&di->d64txregs->addrlow, 0xff0);
722 addrl = R_REG(&di->d64txregs->addrlow);
723 if (addrl != 0)
724 return false;
725 } else if (di->d64rxregs != NULL) {
726 W_REG(&di->d64rxregs->addrlow, 0xff0);
727 addrl = R_REG(&di->d64rxregs->addrlow);
728 if (addrl != 0)
729 return false;
730 }
731 return true;
732 }
733
734 /* return true if this dma engine supports DmaExtendedAddrChanges, otherwise false */
735 static bool _dma_isaddrext(struct dma_info *di)
736 {
737 /* DMA64 supports full 32- or 64-bit operation. AE is always valid */
738
739 /* not all tx or rx channel are available */
740 if (di->d64txregs != NULL) {
741 if (!_dma64_addrext(di->d64txregs)) {
742 DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
743 "AE set\n", di->name));
744 }
745 return true;
746 } else if (di->d64rxregs != NULL) {
747 if (!_dma64_addrext(di->d64rxregs)) {
748 DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
749 "AE set\n", di->name));
750 }
751 return true;
752 }
753 return false;
754 }
755
756 /* initialize descriptor table base address */
757 static void _dma_ddtable_init(struct dma_info *di, uint direction, dmaaddr_t pa)
758 {
759 if (!di->aligndesc_4k) {
760 if (direction == DMA_TX)
761 di->xmtptrbase = PHYSADDRLO(pa);
762 else
763 di->rcvptrbase = PHYSADDRLO(pa);
764 }
765
766 if ((di->ddoffsetlow == 0)
767 || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
768 if (direction == DMA_TX) {
769 W_REG(&di->d64txregs->addrlow,
770 (PHYSADDRLO(pa) + di->ddoffsetlow));
771 W_REG(&di->d64txregs->addrhigh,
772 (PHYSADDRHI(pa) + di->ddoffsethigh));
773 } else {
774 W_REG(&di->d64rxregs->addrlow,
775 (PHYSADDRLO(pa) + di->ddoffsetlow));
776 W_REG(&di->d64rxregs->addrhigh,
777 (PHYSADDRHI(pa) + di->ddoffsethigh));
778 }
779 } else {
780 /* DMA64 32bits address extension */
781 u32 ae;
782
783 /* shift the high bit(s) from pa to ae */
784 ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
785 PCI32ADDR_HIGH_SHIFT;
786 PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
787
788 if (direction == DMA_TX) {
789 W_REG(&di->d64txregs->addrlow,
790 (PHYSADDRLO(pa) + di->ddoffsetlow));
791 W_REG(&di->d64txregs->addrhigh,
792 di->ddoffsethigh);
793 SET_REG(&di->d64txregs->control,
794 D64_XC_AE, (ae << D64_XC_AE_SHIFT));
795 } else {
796 W_REG(&di->d64rxregs->addrlow,
797 (PHYSADDRLO(pa) + di->ddoffsetlow));
798 W_REG(&di->d64rxregs->addrhigh,
799 di->ddoffsethigh);
800 SET_REG(&di->d64rxregs->control,
801 D64_RC_AE, (ae << D64_RC_AE_SHIFT));
802 }
803 }
804 }
805
806 static void _dma_fifoloopbackenable(struct dma_info *di)
807 {
808 DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
809
810 OR_REG(&di->d64txregs->control, D64_XC_LE);
811 }
812
813 static void _dma_rxinit(struct dma_info *di)
814 {
815 DMA_TRACE(("%s: dma_rxinit\n", di->name));
816
817 if (di->nrxd == 0)
818 return;
819
820 di->rxin = di->rxout = 0;
821
822 /* clear rx descriptor ring */
823 memset((void *)di->rxd64, '\0',
824 (di->nrxd * sizeof(struct dma64desc)));
825
826 /* DMA engine with out alignment requirement requires table to be inited
827 * before enabling the engine
828 */
829 if (!di->aligndesc_4k)
830 _dma_ddtable_init(di, DMA_RX, di->rxdpa);
831
832 _dma_rxenable(di);
833
834 if (di->aligndesc_4k)
835 _dma_ddtable_init(di, DMA_RX, di->rxdpa);
836 }
837
838 static void _dma_rxenable(struct dma_info *di)
839 {
840 uint dmactrlflags = di->dma.dmactrlflags;
841 u32 control;
842
843 DMA_TRACE(("%s: dma_rxenable\n", di->name));
844
845 control =
846 (R_REG(&di->d64rxregs->control) & D64_RC_AE) |
847 D64_RC_RE;
848
849 if ((dmactrlflags & DMA_CTRL_PEN) == 0)
850 control |= D64_RC_PD;
851
852 if (dmactrlflags & DMA_CTRL_ROC)
853 control |= D64_RC_OC;
854
855 W_REG(&di->d64rxregs->control,
856 ((di->rxoffset << D64_RC_RO_SHIFT) | control));
857 }
858
859 static void
860 _dma_rx_param_get(struct dma_info *di, u16 *rxoffset, u16 *rxbufsize)
861 {
862 /* the normal values fit into 16 bits */
863 *rxoffset = (u16) di->rxoffset;
864 *rxbufsize = (u16) di->rxbufsize;
865 }
866
867 /* !! rx entry routine
868 * returns a pointer to the next frame received, or NULL if there are no more
869 * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is supported
870 * with pkts chain
871 * otherwise, it's treated as giant pkt and will be tossed.
872 * The DMA scattering starts with normal DMA header, followed by first buffer data.
873 * After it reaches the max size of buffer, the data continues in next DMA descriptor
874 * buffer WITHOUT DMA header
875 */
876 static void *_dma_rx(struct dma_info *di)
877 {
878 struct sk_buff *p, *head, *tail;
879 uint len;
880 uint pkt_len;
881 int resid = 0;
882
883 next_frame:
884 head = _dma_getnextrxp(di, false);
885 if (head == NULL)
886 return NULL;
887
888 len = le16_to_cpu(*(u16 *) (head->data));
889 DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
890 dma_spin_for_len(len, head);
891
892 /* set actual length */
893 pkt_len = min((di->rxoffset + len), di->rxbufsize);
894 __skb_trim(head, pkt_len);
895 resid = len - (di->rxbufsize - di->rxoffset);
896
897 /* check for single or multi-buffer rx */
898 if (resid > 0) {
899 tail = head;
900 while ((resid > 0) && (p = _dma_getnextrxp(di, false))) {
901 tail->next = p;
902 pkt_len = min(resid, (int)di->rxbufsize);
903 __skb_trim(p, pkt_len);
904
905 tail = p;
906 resid -= di->rxbufsize;
907 }
908
909 #ifdef BCMDBG
910 if (resid > 0) {
911 uint cur;
912 cur =
913 B2I(((R_REG(&di->d64rxregs->status0) &
914 D64_RS0_CD_MASK) -
915 di->rcvptrbase) & D64_RS0_CD_MASK,
916 struct dma64desc);
917 DMA_ERROR(("_dma_rx, rxin %d rxout %d, hw_curr %d\n",
918 di->rxin, di->rxout, cur));
919 }
920 #endif /* BCMDBG */
921
922 if ((di->dma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
923 DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n",
924 di->name, len));
925 brcmu_pkt_buf_free_skb(head);
926 di->dma.rxgiants++;
927 goto next_frame;
928 }
929 }
930
931 return head;
932 }
933
934 /* post receive buffers
935 * return false is refill failed completely and ring is empty
936 * this will stall the rx dma and user might want to call rxfill again asap
937 * This unlikely happens on memory-rich NIC, but often on memory-constrained dongle
938 */
939 static bool _dma_rxfill(struct dma_info *di)
940 {
941 struct sk_buff *p;
942 u16 rxin, rxout;
943 u32 flags = 0;
944 uint n;
945 uint i;
946 dmaaddr_t pa;
947 uint extra_offset = 0;
948 bool ring_empty;
949
950 ring_empty = false;
951
952 /*
953 * Determine how many receive buffers we're lacking
954 * from the full complement, allocate, initialize,
955 * and post them, then update the chip rx lastdscr.
956 */
957
958 rxin = di->rxin;
959 rxout = di->rxout;
960
961 n = di->nrxpost - NRXDACTIVE(rxin, rxout);
962
963 DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
964
965 if (di->rxbufsize > BCMEXTRAHDROOM)
966 extra_offset = di->rxextrahdrroom;
967
968 for (i = 0; i < n; i++) {
969 /* the di->rxbufsize doesn't include the extra headroom, we need to add it to the
970 size to be allocated
971 */
972
973 p = brcmu_pkt_buf_get_skb(di->rxbufsize + extra_offset);
974
975 if (p == NULL) {
976 DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n",
977 di->name));
978 if (i == 0 && dma64_rxidle(di)) {
979 DMA_ERROR(("%s: rxfill64: ring is empty !\n",
980 di->name));
981 ring_empty = true;
982 }
983 di->dma.rxnobuf++;
984 break;
985 }
986 /* reserve an extra headroom, if applicable */
987 if (extra_offset)
988 skb_pull(p, extra_offset);
989
990 /* Do a cached write instead of uncached write since DMA_MAP
991 * will flush the cache.
992 */
993 *(u32 *) (p->data) = 0;
994
995 if (DMASGLIST_ENAB)
996 memset(&di->rxp_dmah[rxout], 0,
997 sizeof(struct dma_seg_map));
998
999 pa = pci_map_single(di->pbus, p->data,
1000 di->rxbufsize, PCI_DMA_FROMDEVICE);
1001
1002 /* save the free packet pointer */
1003 di->rxp[rxout] = p;
1004
1005 /* reset flags for each descriptor */
1006 flags = 0;
1007 if (rxout == (di->nrxd - 1))
1008 flags = D64_CTRL1_EOT;
1009
1010 dma64_dd_upd(di, di->rxd64, pa, rxout, &flags,
1011 di->rxbufsize);
1012 rxout = NEXTRXD(rxout);
1013 }
1014
1015 di->rxout = rxout;
1016
1017 /* update the chip lastdscr pointer */
1018 W_REG(&di->d64rxregs->ptr,
1019 di->rcvptrbase + I2B(rxout, struct dma64desc));
1020
1021 return ring_empty;
1022 }
1023
1024 /* like getnexttxp but no reclaim */
1025 static void *_dma_peeknexttxp(struct dma_info *di)
1026 {
1027 uint end, i;
1028
1029 if (di->ntxd == 0)
1030 return NULL;
1031
1032 end =
1033 B2I(((R_REG(&di->d64txregs->status0) &
1034 D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
1035 struct dma64desc);
1036
1037 for (i = di->txin; i != end; i = NEXTTXD(i))
1038 if (di->txp[i])
1039 return di->txp[i];
1040
1041 return NULL;
1042 }
1043
1044 /* like getnextrxp but not take off the ring */
1045 static void *_dma_peeknextrxp(struct dma_info *di)
1046 {
1047 uint end, i;
1048
1049 if (di->nrxd == 0)
1050 return NULL;
1051
1052 end =
1053 B2I(((R_REG(&di->d64rxregs->status0) &
1054 D64_RS0_CD_MASK) - di->rcvptrbase) & D64_RS0_CD_MASK,
1055 struct dma64desc);
1056
1057 for (i = di->rxin; i != end; i = NEXTRXD(i))
1058 if (di->rxp[i])
1059 return di->rxp[i];
1060
1061 return NULL;
1062 }
1063
1064 static void _dma_rxreclaim(struct dma_info *di)
1065 {
1066 void *p;
1067
1068 DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
1069
1070 while ((p = _dma_getnextrxp(di, true)))
1071 brcmu_pkt_buf_free_skb(p);
1072 }
1073
1074 static void *_dma_getnextrxp(struct dma_info *di, bool forceall)
1075 {
1076 if (di->nrxd == 0)
1077 return NULL;
1078
1079 return dma64_getnextrxp(di, forceall);
1080 }
1081
1082 static void _dma_txblock(struct dma_info *di)
1083 {
1084 di->dma.txavail = 0;
1085 }
1086
1087 static void _dma_txunblock(struct dma_info *di)
1088 {
1089 di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1090 }
1091
1092 static uint _dma_txactive(struct dma_info *di)
1093 {
1094 return NTXDACTIVE(di->txin, di->txout);
1095 }
1096
1097 static uint _dma_txpending(struct dma_info *di)
1098 {
1099 uint curr;
1100
1101 curr =
1102 B2I(((R_REG(&di->d64txregs->status0) &
1103 D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
1104 struct dma64desc);
1105
1106 return NTXDACTIVE(curr, di->txout);
1107 }
1108
1109 static uint _dma_txcommitted(struct dma_info *di)
1110 {
1111 uint ptr;
1112 uint txin = di->txin;
1113
1114 if (txin == di->txout)
1115 return 0;
1116
1117 ptr = B2I(R_REG(&di->d64txregs->ptr), struct dma64desc);
1118
1119 return NTXDACTIVE(di->txin, ptr);
1120 }
1121
1122 static uint _dma_rxactive(struct dma_info *di)
1123 {
1124 return NRXDACTIVE(di->rxin, di->rxout);
1125 }
1126
1127 static void _dma_counterreset(struct dma_info *di)
1128 {
1129 /* reset all software counter */
1130 di->dma.rxgiants = 0;
1131 di->dma.rxnobuf = 0;
1132 di->dma.txnobuf = 0;
1133 }
1134
1135 static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags)
1136 {
1137 uint dmactrlflags = di->dma.dmactrlflags;
1138
1139 if (di == NULL) {
1140 DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
1141 return 0;
1142 }
1143
1144 dmactrlflags &= ~mask;
1145 dmactrlflags |= flags;
1146
1147 /* If trying to enable parity, check if parity is actually supported */
1148 if (dmactrlflags & DMA_CTRL_PEN) {
1149 u32 control;
1150
1151 control = R_REG(&di->d64txregs->control);
1152 W_REG(&di->d64txregs->control,
1153 control | D64_XC_PD);
1154 if (R_REG(&di->d64txregs->control) & D64_XC_PD) {
1155 /* We *can* disable it so it is supported,
1156 * restore control register
1157 */
1158 W_REG(&di->d64txregs->control,
1159 control);
1160 } else {
1161 /* Not supported, don't allow it to be enabled */
1162 dmactrlflags &= ~DMA_CTRL_PEN;
1163 }
1164 }
1165
1166 di->dma.dmactrlflags = dmactrlflags;
1167
1168 return dmactrlflags;
1169 }
1170
1171 /* get the address of the var in order to change later */
1172 static unsigned long _dma_getvar(struct dma_info *di, const char *name)
1173 {
1174 if (!strcmp(name, "&txavail"))
1175 return (unsigned long)&(di->dma.txavail);
1176 return 0;
1177 }
1178
1179 static
1180 u8 dma_align_sizetobits(uint size)
1181 {
1182 u8 bitpos = 0;
1183 while (size >>= 1) {
1184 bitpos++;
1185 }
1186 return bitpos;
1187 }
1188
1189 /* This function ensures that the DMA descriptor ring will not get allocated
1190 * across Page boundary. If the allocation is done across the page boundary
1191 * at the first time, then it is freed and the allocation is done at
1192 * descriptor ring size aligned location. This will ensure that the ring will
1193 * not cross page boundary
1194 */
1195 static void *dma_ringalloc(struct dma_info *di, u32 boundary, uint size,
1196 u16 *alignbits, uint *alloced,
1197 dmaaddr_t *descpa)
1198 {
1199 void *va;
1200 u32 desc_strtaddr;
1201 u32 alignbytes = 1 << *alignbits;
1202
1203 va = dma_alloc_consistent(di->pbus, size, *alignbits, alloced, descpa);
1204
1205 if (NULL == va)
1206 return NULL;
1207
1208 desc_strtaddr = (u32) roundup((unsigned long)va, alignbytes);
1209 if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
1210 & boundary)) {
1211 *alignbits = dma_align_sizetobits(size);
1212 pci_free_consistent(di->pbus, size, va, *descpa);
1213 va = dma_alloc_consistent(di->pbus, size, *alignbits,
1214 alloced, descpa);
1215 }
1216 return va;
1217 }
1218
1219 /* 64-bit DMA functions */
1220
1221 static void dma64_txinit(struct dma_info *di)
1222 {
1223 u32 control = D64_XC_XE;
1224
1225 DMA_TRACE(("%s: dma_txinit\n", di->name));
1226
1227 if (di->ntxd == 0)
1228 return;
1229
1230 di->txin = di->txout = 0;
1231 di->dma.txavail = di->ntxd - 1;
1232
1233 /* clear tx descriptor ring */
1234 memset((void *)di->txd64, '\0', (di->ntxd * sizeof(struct dma64desc)));
1235
1236 /* DMA engine with out alignment requirement requires table to be inited
1237 * before enabling the engine
1238 */
1239 if (!di->aligndesc_4k)
1240 _dma_ddtable_init(di, DMA_TX, di->txdpa);
1241
1242 if ((di->dma.dmactrlflags & DMA_CTRL_PEN) == 0)
1243 control |= D64_XC_PD;
1244 OR_REG(&di->d64txregs->control, control);
1245
1246 /* DMA engine with alignment requirement requires table to be inited
1247 * before enabling the engine
1248 */
1249 if (di->aligndesc_4k)
1250 _dma_ddtable_init(di, DMA_TX, di->txdpa);
1251 }
1252
1253 static bool dma64_txenabled(struct dma_info *di)
1254 {
1255 u32 xc;
1256
1257 /* If the chip is dead, it is not enabled :-) */
1258 xc = R_REG(&di->d64txregs->control);
1259 return (xc != 0xffffffff) && (xc & D64_XC_XE);
1260 }
1261
1262 static void dma64_txsuspend(struct dma_info *di)
1263 {
1264 DMA_TRACE(("%s: dma_txsuspend\n", di->name));
1265
1266 if (di->ntxd == 0)
1267 return;
1268
1269 OR_REG(&di->d64txregs->control, D64_XC_SE);
1270 }
1271
1272 static void dma64_txresume(struct dma_info *di)
1273 {
1274 DMA_TRACE(("%s: dma_txresume\n", di->name));
1275
1276 if (di->ntxd == 0)
1277 return;
1278
1279 AND_REG(&di->d64txregs->control, ~D64_XC_SE);
1280 }
1281
1282 static bool dma64_txsuspended(struct dma_info *di)
1283 {
1284 return (di->ntxd == 0) ||
1285 ((R_REG(&di->d64txregs->control) & D64_XC_SE) ==
1286 D64_XC_SE);
1287 }
1288
1289 static void dma64_txreclaim(struct dma_info *di, enum txd_range range)
1290 {
1291 void *p;
1292
1293 DMA_TRACE(("%s: dma_txreclaim %s\n", di->name,
1294 (range == DMA_RANGE_ALL) ? "all" :
1295 ((range ==
1296 DMA_RANGE_TRANSMITTED) ? "transmitted" :
1297 "transferred")));
1298
1299 if (di->txin == di->txout)
1300 return;
1301
1302 while ((p = dma64_getnexttxp(di, range))) {
1303 /* For unframed data, we don't have any packets to free */
1304 if (!(di->dma.dmactrlflags & DMA_CTRL_UNFRAMED))
1305 brcmu_pkt_buf_free_skb(p);
1306 }
1307 }
1308
1309 static bool dma64_txstopped(struct dma_info *di)
1310 {
1311 return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) ==
1312 D64_XS0_XS_STOPPED);
1313 }
1314
1315 static bool dma64_rxstopped(struct dma_info *di)
1316 {
1317 return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) ==
1318 D64_RS0_RS_STOPPED);
1319 }
1320
1321 static bool dma64_alloc(struct dma_info *di, uint direction)
1322 {
1323 u16 size;
1324 uint ddlen;
1325 void *va;
1326 uint alloced = 0;
1327 u16 align;
1328 u16 align_bits;
1329
1330 ddlen = sizeof(struct dma64desc);
1331
1332 size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
1333 align_bits = di->dmadesc_align;
1334 align = (1 << align_bits);
1335
1336 if (direction == DMA_TX) {
1337 va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
1338 &alloced, &di->txdpaorig);
1339 if (va == NULL) {
1340 DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
1341 return false;
1342 }
1343 align = (1 << align_bits);
1344 di->txd64 = (struct dma64desc *)
1345 roundup((unsigned long)va, align);
1346 di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
1347 PHYSADDRLOSET(di->txdpa,
1348 PHYSADDRLO(di->txdpaorig) + di->txdalign);
1349 PHYSADDRHISET(di->txdpa, PHYSADDRHI(di->txdpaorig));
1350 di->txdalloc = alloced;
1351 } else {
1352 va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
1353 &alloced, &di->rxdpaorig);
1354 if (va == NULL) {
1355 DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
1356 return false;
1357 }
1358 align = (1 << align_bits);
1359 di->rxd64 = (struct dma64desc *)
1360 roundup((unsigned long)va, align);
1361 di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
1362 PHYSADDRLOSET(di->rxdpa,
1363 PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
1364 PHYSADDRHISET(di->rxdpa, PHYSADDRHI(di->rxdpaorig));
1365 di->rxdalloc = alloced;
1366 }
1367
1368 return true;
1369 }
1370
1371 static bool dma64_txreset(struct dma_info *di)
1372 {
1373 u32 status;
1374
1375 if (di->ntxd == 0)
1376 return true;
1377
1378 /* suspend tx DMA first */
1379 W_REG(&di->d64txregs->control, D64_XC_SE);
1380 SPINWAIT(((status =
1381 (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
1382 != D64_XS0_XS_DISABLED) && (status != D64_XS0_XS_IDLE)
1383 && (status != D64_XS0_XS_STOPPED), 10000);
1384
1385 W_REG(&di->d64txregs->control, 0);
1386 SPINWAIT(((status =
1387 (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
1388 != D64_XS0_XS_DISABLED), 10000);
1389
1390 /* wait for the last transaction to complete */
1391 udelay(300);
1392
1393 return status == D64_XS0_XS_DISABLED;
1394 }
1395
1396 static bool dma64_rxidle(struct dma_info *di)
1397 {
1398 DMA_TRACE(("%s: dma_rxidle\n", di->name));
1399
1400 if (di->nrxd == 0)
1401 return true;
1402
1403 return ((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
1404 (R_REG(&di->d64rxregs->ptr) & D64_RS0_CD_MASK));
1405 }
1406
1407 static bool dma64_rxreset(struct dma_info *di)
1408 {
1409 u32 status;
1410
1411 if (di->nrxd == 0)
1412 return true;
1413
1414 W_REG(&di->d64rxregs->control, 0);
1415 SPINWAIT(((status =
1416 (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK))
1417 != D64_RS0_RS_DISABLED), 10000);
1418
1419 return status == D64_RS0_RS_DISABLED;
1420 }
1421
1422 static bool dma64_rxenabled(struct dma_info *di)
1423 {
1424 u32 rc;
1425
1426 rc = R_REG(&di->d64rxregs->control);
1427 return (rc != 0xffffffff) && (rc & D64_RC_RE);
1428 }
1429
1430 static bool dma64_txsuspendedidle(struct dma_info *di)
1431 {
1432
1433 if (di->ntxd == 0)
1434 return true;
1435
1436 if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
1437 return 0;
1438
1439 if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) ==
1440 D64_XS0_XS_IDLE)
1441 return 1;
1442
1443 return 0;
1444 }
1445
1446 /* Useful when sending unframed data. This allows us to get a progress report from the DMA.
1447 * We return a pointer to the beginning of the DATA buffer of the current descriptor.
1448 * If DMA is idle, we return NULL.
1449 */
1450 static void *dma64_getpos(struct dma_info *di, bool direction)
1451 {
1452 void *va;
1453 bool idle;
1454 u32 cd_offset;
1455
1456 if (direction == DMA_TX) {
1457 cd_offset =
1458 R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK;
1459 idle = !NTXDACTIVE(di->txin, di->txout);
1460 va = di->txp[B2I(cd_offset, struct dma64desc)];
1461 } else {
1462 cd_offset =
1463 R_REG(&di->d64rxregs->status0) & D64_XS0_CD_MASK;
1464 idle = !NRXDACTIVE(di->rxin, di->rxout);
1465 va = di->rxp[B2I(cd_offset, struct dma64desc)];
1466 }
1467
1468 /* If DMA is IDLE, return NULL */
1469 if (idle) {
1470 DMA_TRACE(("%s: DMA idle, return NULL\n", __func__));
1471 va = NULL;
1472 }
1473
1474 return va;
1475 }
1476
1477 /* TX of unframed data
1478 *
1479 * Adds a DMA ring descriptor for the data pointed to by "buf".
1480 * This is for DMA of a buffer of data and is unlike other dma TX functions
1481 * that take a pointer to a "packet"
1482 * Each call to this is results in a single descriptor being added for "len" bytes of
1483 * data starting at "buf", it doesn't handle chained buffers.
1484 */
1485 static int
1486 dma64_txunframed(struct dma_info *di, void *buf, uint len, bool commit)
1487 {
1488 u16 txout;
1489 u32 flags = 0;
1490 dmaaddr_t pa; /* phys addr */
1491
1492 txout = di->txout;
1493
1494 /* return nonzero if out of tx descriptors */
1495 if (NEXTTXD(txout) == di->txin)
1496 goto outoftxd;
1497
1498 if (len == 0)
1499 return 0;
1500
1501 pa = pci_map_single(di->pbus, buf, len, PCI_DMA_TODEVICE);
1502
1503 flags = (D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF);
1504
1505 if (txout == (di->ntxd - 1))
1506 flags |= D64_CTRL1_EOT;
1507
1508 dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
1509
1510 /* save the buffer pointer - used by dma_getpos */
1511 di->txp[txout] = buf;
1512
1513 txout = NEXTTXD(txout);
1514 /* bump the tx descriptor index */
1515 di->txout = txout;
1516
1517 /* kick the chip */
1518 if (commit) {
1519 W_REG(&di->d64txregs->ptr,
1520 di->xmtptrbase + I2B(txout, struct dma64desc));
1521 }
1522
1523 /* tx flow control */
1524 di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1525
1526 return 0;
1527
1528 outoftxd:
1529 DMA_ERROR(("%s: %s: out of txds !!!\n", di->name, __func__));
1530 di->dma.txavail = 0;
1531 di->dma.txnobuf++;
1532 return -1;
1533 }
1534
1535 /* !! tx entry routine
1536 * WARNING: call must check the return value for error.
1537 * the error(toss frames) could be fatal and cause many subsequent hard to debug problems
1538 */
1539 static int dma64_txfast(struct dma_info *di, struct sk_buff *p0,
1540 bool commit)
1541 {
1542 struct sk_buff *p, *next;
1543 unsigned char *data;
1544 uint len;
1545 u16 txout;
1546 u32 flags = 0;
1547 dmaaddr_t pa;
1548
1549 DMA_TRACE(("%s: dma_txfast\n", di->name));
1550
1551 txout = di->txout;
1552
1553 /*
1554 * Walk the chain of packet buffers
1555 * allocating and initializing transmit descriptor entries.
1556 */
1557 for (p = p0; p; p = next) {
1558 uint nsegs, j;
1559 struct dma_seg_map *map;
1560
1561 data = p->data;
1562 len = p->len;
1563 next = p->next;
1564
1565 /* return nonzero if out of tx descriptors */
1566 if (NEXTTXD(txout) == di->txin)
1567 goto outoftxd;
1568
1569 if (len == 0)
1570 continue;
1571
1572 /* get physical address of buffer start */
1573 if (DMASGLIST_ENAB)
1574 memset(&di->txp_dmah[txout], 0,
1575 sizeof(struct dma_seg_map));
1576
1577 pa = pci_map_single(di->pbus, data, len, PCI_DMA_TODEVICE);
1578
1579 if (DMASGLIST_ENAB) {
1580 map = &di->txp_dmah[txout];
1581
1582 /* See if all the segments can be accounted for */
1583 if (map->nsegs >
1584 (uint) (di->ntxd - NTXDACTIVE(di->txin, di->txout) -
1585 1))
1586 goto outoftxd;
1587
1588 nsegs = map->nsegs;
1589 } else
1590 nsegs = 1;
1591
1592 for (j = 1; j <= nsegs; j++) {
1593 flags = 0;
1594 if (p == p0 && j == 1)
1595 flags |= D64_CTRL1_SOF;
1596
1597 /* With a DMA segment list, Descriptor table is filled
1598 * using the segment list instead of looping over
1599 * buffers in multi-chain DMA. Therefore, EOF for SGLIST is when
1600 * end of segment list is reached.
1601 */
1602 if ((!DMASGLIST_ENAB && next == NULL) ||
1603 (DMASGLIST_ENAB && j == nsegs))
1604 flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
1605 if (txout == (di->ntxd - 1))
1606 flags |= D64_CTRL1_EOT;
1607
1608 if (DMASGLIST_ENAB) {
1609 len = map->segs[j - 1].length;
1610 pa = map->segs[j - 1].addr;
1611 }
1612 dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
1613
1614 txout = NEXTTXD(txout);
1615 }
1616
1617 /* See above. No need to loop over individual buffers */
1618 if (DMASGLIST_ENAB)
1619 break;
1620 }
1621
1622 /* if last txd eof not set, fix it */
1623 if (!(flags & D64_CTRL1_EOF))
1624 W_SM(&di->txd64[PREVTXD(txout)].ctrl1,
1625 BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
1626
1627 /* save the packet */
1628 di->txp[PREVTXD(txout)] = p0;
1629
1630 /* bump the tx descriptor index */
1631 di->txout = txout;
1632
1633 /* kick the chip */
1634 if (commit)
1635 W_REG(&di->d64txregs->ptr,
1636 di->xmtptrbase + I2B(txout, struct dma64desc));
1637
1638 /* tx flow control */
1639 di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1640
1641 return 0;
1642
1643 outoftxd:
1644 DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di->name));
1645 brcmu_pkt_buf_free_skb(p0);
1646 di->dma.txavail = 0;
1647 di->dma.txnobuf++;
1648 return -1;
1649 }
1650
1651 /*
1652 * Reclaim next completed txd (txds if using chained buffers) in the range
1653 * specified and return associated packet.
1654 * If range is DMA_RANGE_TRANSMITTED, reclaim descriptors that have be
1655 * transmitted as noted by the hardware "CurrDescr" pointer.
1656 * If range is DMA_RANGE_TRANSFERED, reclaim descriptors that have be
1657 * transferred by the DMA as noted by the hardware "ActiveDescr" pointer.
1658 * If range is DMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
1659 * return associated packet regardless of the value of hardware pointers.
1660 */
1661 static void *dma64_getnexttxp(struct dma_info *di, enum txd_range range)
1662 {
1663 u16 start, end, i;
1664 u16 active_desc;
1665 void *txp;
1666
1667 DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name,
1668 (range == DMA_RANGE_ALL) ? "all" :
1669 ((range ==
1670 DMA_RANGE_TRANSMITTED) ? "transmitted" :
1671 "transferred")));
1672
1673 if (di->ntxd == 0)
1674 return NULL;
1675
1676 txp = NULL;
1677
1678 start = di->txin;
1679 if (range == DMA_RANGE_ALL)
1680 end = di->txout;
1681 else {
1682 dma64regs_t *dregs = di->d64txregs;
1683
1684 end = (u16) (B2I(((R_REG(&dregs->status0) &
1685 D64_XS0_CD_MASK) -
1686 di->xmtptrbase) & D64_XS0_CD_MASK,
1687 struct dma64desc));
1688
1689 if (range == DMA_RANGE_TRANSFERED) {
1690 active_desc =
1691 (u16) (R_REG(&dregs->status1) &
1692 D64_XS1_AD_MASK);
1693 active_desc =
1694 (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK;
1695 active_desc = B2I(active_desc, struct dma64desc);
1696 if (end != active_desc)
1697 end = PREVTXD(active_desc);
1698 }
1699 }
1700
1701 if ((start == 0) && (end > di->txout))
1702 goto bogus;
1703
1704 for (i = start; i != end && !txp; i = NEXTTXD(i)) {
1705 dmaaddr_t pa;
1706 struct dma_seg_map *map = NULL;
1707 uint size, j, nsegs;
1708
1709 PHYSADDRLOSET(pa,
1710 (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) -
1711 di->dataoffsetlow));
1712 PHYSADDRHISET(pa,
1713 (BUS_SWAP32(R_SM(&di->txd64[i].addrhigh)) -
1714 di->dataoffsethigh));
1715
1716 if (DMASGLIST_ENAB) {
1717 map = &di->txp_dmah[i];
1718 size = map->origsize;
1719 nsegs = map->nsegs;
1720 } else {
1721 size =
1722 (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) &
1723 D64_CTRL2_BC_MASK);
1724 nsegs = 1;
1725 }
1726
1727 for (j = nsegs; j > 0; j--) {
1728 W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
1729 W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
1730
1731 txp = di->txp[i];
1732 di->txp[i] = NULL;
1733 if (j > 1)
1734 i = NEXTTXD(i);
1735 }
1736
1737 pci_unmap_single(di->pbus, pa, size, PCI_DMA_TODEVICE);
1738 }
1739
1740 di->txin = i;
1741
1742 /* tx flow control */
1743 di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1744
1745 return txp;
1746
1747 bogus:
1748 DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall));
1749 return NULL;
1750 }
1751
1752 static void *dma64_getnextrxp(struct dma_info *di, bool forceall)
1753 {
1754 uint i, curr;
1755 void *rxp;
1756 dmaaddr_t pa;
1757
1758 i = di->rxin;
1759
1760 /* return if no packets posted */
1761 if (i == di->rxout)
1762 return NULL;
1763
1764 curr =
1765 B2I(((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) -
1766 di->rcvptrbase) & D64_RS0_CD_MASK, struct dma64desc);
1767
1768 /* ignore curr if forceall */
1769 if (!forceall && (i == curr))
1770 return NULL;
1771
1772 /* get the packet pointer that corresponds to the rx descriptor */
1773 rxp = di->rxp[i];
1774 di->rxp[i] = NULL;
1775
1776 PHYSADDRLOSET(pa,
1777 (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) -
1778 di->dataoffsetlow));
1779 PHYSADDRHISET(pa,
1780 (BUS_SWAP32(R_SM(&di->rxd64[i].addrhigh)) -
1781 di->dataoffsethigh));
1782
1783 /* clear this packet from the descriptor ring */
1784 pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE);
1785
1786 W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
1787 W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
1788
1789 di->rxin = NEXTRXD(i);
1790
1791 return rxp;
1792 }
1793
1794 static bool _dma64_addrext(dma64regs_t *dma64regs)
1795 {
1796 u32 w;
1797 OR_REG(&dma64regs->control, D64_XC_AE);
1798 w = R_REG(&dma64regs->control);
1799 AND_REG(&dma64regs->control, ~D64_XC_AE);
1800 return (w & D64_XC_AE) == D64_XC_AE;
1801 }
1802
1803 /*
1804 * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
1805 */
1806 static void dma64_txrotate(struct dma_info *di)
1807 {
1808 u16 ad;
1809 uint nactive;
1810 uint rot;
1811 u16 old, new;
1812 u32 w;
1813 u16 first, last;
1814
1815 nactive = _dma_txactive(di);
1816 ad = (u16) (B2I((((R_REG(&di->d64txregs->status1) &
1817 D64_XS1_AD_MASK) - di->xmtptrbase) &
1818 D64_XS1_AD_MASK), struct dma64desc));
1819 rot = TXD(ad - di->txin);
1820
1821 /* full-ring case is a lot harder - don't worry about this */
1822 if (rot >= (di->ntxd - nactive)) {
1823 DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
1824 return;
1825 }
1826
1827 first = di->txin;
1828 last = PREVTXD(di->txout);
1829
1830 /* move entries starting at last and moving backwards to first */
1831 for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
1832 new = TXD(old + rot);
1833
1834 /*
1835 * Move the tx dma descriptor.
1836 * EOT is set only in the last entry in the ring.
1837 */
1838 w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl1)) & ~D64_CTRL1_EOT;
1839 if (new == (di->ntxd - 1))
1840 w |= D64_CTRL1_EOT;
1841 W_SM(&di->txd64[new].ctrl1, BUS_SWAP32(w));
1842
1843 w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl2));
1844 W_SM(&di->txd64[new].ctrl2, BUS_SWAP32(w));
1845
1846 W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
1847 W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
1848
1849 /* zap the old tx dma descriptor address field */
1850 W_SM(&di->txd64[old].addrlow, BUS_SWAP32(0xdeadbeef));
1851 W_SM(&di->txd64[old].addrhigh, BUS_SWAP32(0xdeadbeef));
1852
1853 /* move the corresponding txp[] entry */
1854 di->txp[new] = di->txp[old];
1855
1856 /* Move the map */
1857 if (DMASGLIST_ENAB) {
1858 memcpy(&di->txp_dmah[new], &di->txp_dmah[old],
1859 sizeof(struct dma_seg_map));
1860 memset(&di->txp_dmah[old], 0,
1861 sizeof(struct dma_seg_map));
1862 }
1863
1864 di->txp[old] = NULL;
1865 }
1866
1867 /* update txin and txout */
1868 di->txin = ad;
1869 di->txout = TXD(di->txout + rot);
1870 di->dma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
1871
1872 /* kick the chip */
1873 W_REG(&di->d64txregs->ptr,
1874 di->xmtptrbase + I2B(di->txout, struct dma64desc));
1875 }
1876
1877 uint dma_addrwidth(struct si_pub *sih, void *dmaregs)
1878 {
1879 /* Perform 64-bit checks only if we want to advertise 64-bit (> 32bit) capability) */
1880 /* DMA engine is 64-bit capable */
1881 if ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64) {
1882 /* backplane are 64-bit capable */
1883 if (ai_backplane64(sih))
1884 /* If bus is System Backplane or PCIE then we can access 64-bits */
1885 if ((sih->bustype == SI_BUS) ||
1886 ((sih->bustype == PCI_BUS) &&
1887 (sih->buscoretype == PCIE_CORE_ID)))
1888 return DMADDRWIDTH_64;
1889 }
1890 /* DMA hardware not supported by this driver*/
1891 return DMADDRWIDTH_64;
1892 }
1893
1894 /*
1895 * Mac80211 initiated actions sometimes require packets in the DMA queue to be
1896 * modified. The modified portion of the packet is not under control of the DMA
1897 * engine. This function calls a caller-supplied function for each packet in
1898 * the caller specified dma chain.
1899 */
1900 void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
1901 (void *pkt, void *arg_a), void *arg_a)
1902 {
1903 struct dma_info *di = (struct dma_info *) dmah;
1904 uint i = di->txin;
1905 uint end = di->txout;
1906 struct sk_buff *skb;
1907 struct ieee80211_tx_info *tx_info;
1908
1909 while (i != end) {
1910 skb = (struct sk_buff *)di->txp[i];
1911 if (skb != NULL) {
1912 tx_info = (struct ieee80211_tx_info *)skb->cb;
1913 (callback_fnc)(tx_info, arg_a);
1914 }
1915 i = NEXTTXD(i);
1916 }
1917 }
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