drivers/staging/et131x/et1310_phy.h

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
  12  *                PHY.
  13  *
  14  *------------------------------------------------------------------------------
  15  *
  16  * SOFTWARE LICENSE
  17  *
  18  * This software is provided subject to the following terms and conditions,
  19  * which you should read carefully before using the software.  Using this
  20  * software indicates your acceptance of these terms and conditions.  If you do
  21  * not agree with these terms and conditions, do not use the software.
  22  *
  23  * Copyright © 2005 Agere Systems Inc.
  24  * All rights reserved.
  25  *
  26  * Redistribution and use in source or binary forms, with or without
  27  * modifications, are permitted provided that the following conditions are met:
  28  *
  29  * . Redistributions of source code must retain the above copyright notice, this
  30  *    list of conditions and the following Disclaimer as comments in the code as
  31  *    well as in the documentation and/or other materials provided with the
  32  *    distribution.
  33  *
  34  * . Redistributions in binary form must reproduce the above copyright notice,
  35  *    this list of conditions and the following Disclaimer in the documentation
  36  *    and/or other materials provided with the distribution.
  37  *
  38  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  39  *    may be used to endorse or promote products derived from this software
  40  *    without specific prior written permission.
  41  *
  42  * Disclaimer
  43  *
  44  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  45  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  46  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  47  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  48  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  49  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  50  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  51  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  52  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  53  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  54  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  55  * DAMAGE.
  56  *
  57  */
  58
  59 #ifndef _ET1310_PHY_H_
  60 #define _ET1310_PHY_H_
  61
  62 #include "et1310_address_map.h"
  63
  64 /* MI Register Addresses */
  65 #define MI_CONTROL_REG                      0
  66 #define MI_STATUS_REG                       1
  67 #define MI_PHY_IDENTIFIER_1_REG             2
  68 #define MI_PHY_IDENTIFIER_2_REG             3
  69 #define MI_AUTONEG_ADVERTISEMENT_REG        4
  70 #define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
  71 #define MI_AUTONEG_EXPANSION_REG            6
  72 #define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG   7
  73 #define MI_LINK_PARTNER_NEXT_PAGE_REG       8
  74 #define MI_1000BASET_CONTROL_REG            9
  75 #define MI_1000BASET_STATUS_REG             10
  76 #define MI_RESERVED11_REG                   11
  77 #define MI_RESERVED12_REG                   12
  78 #define MI_RESERVED13_REG                   13
  79 #define MI_RESERVED14_REG                   14
  80 #define MI_EXTENDED_STATUS_REG              15
  81
  82 /* VMI Register Addresses */
  83 #define VMI_RESERVED16_REG                  16
  84 #define VMI_RESERVED17_REG                  17
  85 #define VMI_RESERVED18_REG                  18
  86 #define VMI_LOOPBACK_CONTROL_REG            19
  87 #define VMI_RESERVED20_REG                  20
  88 #define VMI_MI_CONTROL_REG                  21
  89 #define VMI_PHY_CONFIGURATION_REG           22
  90 #define VMI_PHY_CONTROL_REG                 23
  91 #define VMI_INTERRUPT_MASK_REG              24
  92 #define VMI_INTERRUPT_STATUS_REG            25
  93 #define VMI_PHY_STATUS_REG                  26
  94 #define VMI_LED_CONTROL_1_REG               27
  95 #define VMI_LED_CONTROL_2_REG               28
  96 #define VMI_RESERVED29_REG                  29
  97 #define VMI_RESERVED30_REG                  30
  98 #define VMI_RESERVED31_REG                  31
  99
 100 /* PHY Register Mapping(MI) Management Interface Regs */
 101 struct mi_regs {
 102         u8 bmcr;        /* Basic mode control reg(Reg 0x00) */
 103         u8 bmsr;        /* Basic mode status reg(Reg 0x01) */
 104         u8 idr1;        /* Phy identifier reg 1(Reg 0x02) */
 105         u8 idr2;        /* Phy identifier reg 2(Reg 0x03) */
 106         u8 anar;        /* Auto-Negotiation advertisement(Reg 0x04) */
 107         u8 anlpar;      /* Auto-Negotiation link Partner Ability(Reg 0x05) */
 108         u8 aner;        /* Auto-Negotiation expansion reg(Reg 0x06) */
 109         u8 annptr;      /* Auto-Negotiation next page transmit reg(Reg 0x07) */
 110         u8 lpnpr;       /* link partner next page reg(Reg 0x08) */
 111         u8 gcr;         /* Gigabit basic mode control reg(Reg 0x09) */
 112         u8 gsr;         /* Gigabit basic mode status reg(Reg 0x0A) */
 113         u8 mi_res1[4];  /* Future use by MI working group(Reg 0x0B - 0x0E) */
 114         u8 esr;         /* Extended status reg(Reg 0x0F) */
 115         u8 mi_res2[3];  /* Future use by MI working group(Reg 0x10 - 0x12) */
 116         u8 loop_ctl;    /* Loopback Control Reg(Reg 0x13) */
 117         u8 mi_res3;     /* Future use by MI working group(Reg 0x14) */
 118         u8 mcr;         /* MI Control Reg(Reg 0x15) */
 119         u8 pcr;         /* Configuration Reg(Reg 0x16) */
 120         u8 phy_ctl;     /* PHY Control Reg(Reg 0x17) */
 121         u8 imr;         /* Interrupt Mask Reg(Reg 0x18) */
 122         u8 isr;         /* Interrupt Status Reg(Reg 0x19) */
 123         u8 psr;         /* PHY Status Reg(Reg 0x1A) */
 124         u8 lcr1;                /* LED Control 1 Reg(Reg 0x1B) */
 125         u8 lcr2;                /* LED Control 2 Reg(Reg 0x1C) */
 126         u8 mi_res4[3];  /* Future use by MI working group(Reg 0x1D - 0x1F) */
 127 };
 128
 129 /*
 130  * MI Register 0: Basic mode control register
 131  *      15:     reset
 132  *      14:     loopback
 133  *      13:     speed_sel
 134  *      12:     enable_autoneg
 135  *      11:     power_down
 136  *      10:     isolate
 137  *      9:      restart_autoneg
 138  *      8:      duplex_mode
 139  *      7:      col_test
 140  *      6:      speed_1000_sel
 141  *      5-0:    res1
 142  */
 143
 144 /*
 145  * MI Register 1:  Basic mode status register
 146  *      15:     link_100T4
 147  *      14:     link_100fdx
 148  *      13:     link_100hdx
 149  *      12:     link_10fdx
 150  *      11:     link_10hdx
 151  *      10:     link_100T2fdx
 152  *      9:      link_100T2hdx
 153  *      8:      extend_status
 154  *      7:      res1
 155  *      6:      preamble_supress
 156  *      5:      auto_neg_complete
 157  *      4:      remote_fault
 158  *      3:      auto_neg_able
 159  *      2:      link_status
 160  *      1:      jabber_detect
 161  *      0:      ext_cap
 162  */
 163
 164 #define MI_BMSR_LINK_STATUS       0x04
 165 #define MI_BMSR_AUTO_NEG_COMPLETE 0x20
 166
 167 /*
 168  * MI Register 4: Auto-negotiation advertisement register
 169  *
 170  *      15:     np_indication
 171  *      14:     res2
 172  *      13:     remote_fault
 173  *      12:     res1
 174  *      11:     cap_asmpause
 175  *      10:     cap_pause
 176  *      9:      cap_100T4
 177  *      8:      cap_100fdx
 178  *      7:      cap_100hdx
 179  *      6:      cap_10fdx
 180  *      5:      cap_10hdx
 181  *      4-0:    selector
 182  */
 183
 184 /* MI Register 5: Auto-negotiation link partner advertisement register
 185  *      15:     np_indication
 186  *      14:     acknowledge
 187  *      13:     remote_fault
 188  *      12:     res1
 189  *      11:     cap_asmpause
 190  *      10:     cap_pause
 191  *      9:      cap_100T4
 192  *      8:      cap_100fdx
 193  *      7:      cap_100hdx
 194  *      6:      cap_10fdx
 195  *      5:      cap_10hdx
 196  *      4-0:    selector
 197  */
 198
 199 /* MI Register 6: Auto-negotiation expansion register
 200  *      15-5:   reserved
 201  *      4:      pdf
 202  *      3:      lp_np_able
 203  *      2:      np_able
 204  *      1:      page_rx
 205  *      0:      lp_an_able
 206  */
 207
 208 /* MI Register 7: Auto-negotiation next page transmit reg(0x07)
 209  *      15:     np
 210  *      14:     reserved
 211  *      13:     msg_page
 212  *      12:     ack2
 213  *      11:     toggle
 214  *      10-0    msg
 215  */
 216
 217 /* MI Register 8: Link Partner Next Page Reg(0x08)
 218  *      15:     np
 219  *      14:     ack
 220  *      13:     msg_page
 221  *      12:     ack2
 222  *      11:     toggle
 223  *      10-0:   msg
 224  */
 225
 226 /* MI Register 9: 1000BaseT Control Reg(0x09)
 227  *      15-13:  test_mode
 228  *      12:     ms_config_en
 229  *      11:     ms_value
 230  *      10:     port_type
 231  *      9:      link_1000fdx
 232  *      8:      link_1000hdx
 233  *      7-0:    reserved
 234  */
 235
 236 /* MI Register 10: 1000BaseT Status Reg(0x0A)
 237  *      15:     ms_config_fault
 238  *      14:     ms_resolve
 239  *      13:     local_rx_status
 240  *      12:     remote_rx_status
 241  *      11:     link_1000fdx
 242  *      10:     link_1000hdx
 243  *      9-8:    reserved
 244  *      7-0:    idle_err_cnt
 245  */
 246
 247 /* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
 248
 249 /* MI Register 15: Extended status Reg(0x0F)
 250  *      15:     link_1000Xfdx
 251  *      14:     link_1000Xhdx
 252  *      13:     link_1000fdx
 253  *      12:     link_1000hdx
 254  *      11-0:   reserved
 255  */
 256
 257 /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
 258
 259 /* MI Register 19: Loopback Control Reg(0x13)
 260  *      15:     mii_en
 261  *      14:     pcs_en
 262  *      13:     pmd_en
 263  *      12:     all_digital_en
 264  *      11:     replica_en
 265  *      10:     line_driver_en
 266  *      9-0:    reserved
 267  */
 268
 269 /* MI Register 20: Reserved Reg(0x14) */
 270
 271 /* MI Register 21: Management Interface Control Reg(0x15)
 272  *      15-11:  reserved
 273  *      10-4:   mi_error_count
 274  *      3:      reserved
 275  *      2:      ignore_10g_fr
 276  *      1:      reserved
 277  *      0:      preamble_supress_en
 278  */
 279
 280 /* MI Register 22: PHY Configuration Reg(0x16)
 281  *      15:     crs_tx_en
 282  *      14:     reserved
 283  *      13-12:  tx_fifo_depth
 284  *      11-10:  speed_downshift
 285  *      9:      pbi_detect
 286  *      8:      tbi_rate
 287  *      7:      alternate_np
 288  *      6:      group_mdio_en
 289  *      5:      tx_clock_en
 290  *      4:      sys_clock_en
 291  *      3:      reserved
 292  *      2-0:    mac_if_mode
 293  */
 294
 295 /* MI Register 23: PHY CONTROL Reg(0x17)
 296  *      15:     reserved
 297  *      14:     tdr_en
 298  *      13:     reserved
 299  *      12-11:  downshift_attempts
 300  *      10-6:   reserved
 301  *      5:      jabber_10baseT
 302  *      4:      sqe_10baseT
 303  *      3:      tp_loopback_10baseT
 304  *      2:      preamble_gen_en
 305  *      1:      reserved
 306  *      0:      force_int
 307  */
 308
 309 /* MI Register 24: Interrupt Mask Reg(0x18)
 310  *      15-10:  reserved
 311  *      9:      mdio_sync_lost
 312  *      8:      autoneg_status
 313  *      7:      hi_bit_err
 314  *      6:      np_rx
 315  *      5:      err_counter_full
 316  *      4:      fifo_over_underflow
 317  *      3:      rx_status
 318  *      2:      link_status
 319  *      1:      automatic_speed
 320  *      0:      int_en
 321  */
 322
 323
 324 /* MI Register 25: Interrupt Status Reg(0x19)
 325  *      15-10:  reserved
 326  *      9:      mdio_sync_lost
 327  *      8:      autoneg_status
 328  *      7:      hi_bit_err
 329  *      6:      np_rx
 330  *      5:      err_counter_full
 331  *      4:      fifo_over_underflow
 332  *      3:      rx_status
 333  *      2:      link_status
 334  *      1:      automatic_speed
 335  *      0:      int_en
 336  */
 337
 338 /* MI Register 26: PHY Status Reg(0x1A)
 339  *      15:     reserved
 340  *      14-13:  autoneg_fault
 341  *      12:     autoneg_status
 342  *      11:     mdi_x_status
 343  *      10:     polarity_status
 344  *      9-8:    speed_status
 345  *      7:      duplex_status
 346  *      6:      link_status
 347  *      5:      tx_status
 348  *      4:      rx_status
 349  *      3:      collision_status
 350  *      2:      autoneg_en
 351  *      1:      pause_en
 352  *      0:      asymmetric_dir
 353  */
 354
 355 /* MI Register 27: LED Control Reg 1(0x1B)
 356  *      15-14:  reserved
 357  *      13-12:  led_dup_indicate
 358  *      11-10:  led_10baseT
 359  *      9-8:    led_collision
 360  *      7-4:    reserved
 361  *      3-2:    pulse_dur
 362  *      1:      pulse_stretch1
 363  *      0:      pulse_stretch0
 364  */
 365
 366 /* MI Register 28: LED Control Reg 2(0x1C)
 367  *      15-12:  led_link
 368  *      11-8:   led_tx_rx
 369  *      7-4:    led_100BaseTX
 370  *      3-0:    led_1000BaseT
 371  */
 372
 373 /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
 374
 375
 376 /* Prototypes for ET1310_phy.c */
 377 /* Defines for PHY access routines */
 378
 379 /* Define bit operation flags */
 380 #define TRUEPHY_BIT_CLEAR               0
 381 #define TRUEPHY_BIT_SET                 1
 382 #define TRUEPHY_BIT_READ                2
 383
 384 /* Define read/write operation flags */
 385 #ifndef TRUEPHY_READ
 386 #define TRUEPHY_READ                    0
 387 #define TRUEPHY_WRITE                   1
 388 #define TRUEPHY_MASK                    2
 389 #endif
 390
 391 /* Define speeds */
 392 #define TRUEPHY_SPEED_10MBPS            0
 393 #define TRUEPHY_SPEED_100MBPS           1
 394 #define TRUEPHY_SPEED_1000MBPS          2
 395
 396 /* Define duplex modes */
 397 #define TRUEPHY_DUPLEX_HALF             0
 398 #define TRUEPHY_DUPLEX_FULL             1
 399
 400 /* Define master/slave configuration values */
 401 #define TRUEPHY_CFG_SLAVE               0
 402 #define TRUEPHY_CFG_MASTER              1
 403
 404 /* Define MDI/MDI-X settings */
 405 #define TRUEPHY_MDI                     0
 406 #define TRUEPHY_MDIX                    1
 407 #define TRUEPHY_AUTO_MDI_MDIX           2
 408
 409 /* Define 10Base-T link polarities */
 410 #define TRUEPHY_POLARITY_NORMAL         0
 411 #define TRUEPHY_POLARITY_INVERTED       1
 412
 413 /* Define auto-negotiation results */
 414 #define TRUEPHY_ANEG_NOT_COMPLETE       0
 415 #define TRUEPHY_ANEG_COMPLETE           1
 416 #define TRUEPHY_ANEG_DISABLED           2
 417
 418 /* Define duplex advertisement flags */
 419 #define TRUEPHY_ADV_DUPLEX_NONE         0x00
 420 #define TRUEPHY_ADV_DUPLEX_FULL         0x01
 421 #define TRUEPHY_ADV_DUPLEX_HALF         0x02
 422 #define TRUEPHY_ADV_DUPLEX_BOTH     \
 423         (TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
 424
 425 #define PHY_CONTROL                0x00 /* #define TRU_MI_CONTROL_REGISTER                 0 */
 426 #define PHY_STATUS                 0x01 /* #define TRU_MI_STATUS_REGISTER                  1 */
 427 #define PHY_ID_1                   0x02 /* #define TRU_MI_PHY_IDENTIFIER_1_REGISTER        2 */
 428 #define PHY_ID_2                   0x03 /* #define TRU_MI_PHY_IDENTIFIER_2_REGISTER        3 */
 429 #define PHY_AUTO_ADVERTISEMENT     0x04 /* #define TRU_MI_ADVERTISEMENT_REGISTER           4 */
 430 #define PHY_AUTO_LINK_PARTNER      0x05 /* #define TRU_MI_LINK_PARTNER_ABILITY_REGISTER    5 */
 431 #define PHY_AUTO_EXPANSION         0x06 /* #define TRU_MI_EXPANSION_REGISTER               6 */
 432 #define PHY_AUTO_NEXT_PAGE_TX      0x07 /* #define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER      7 */
 433 #define PHY_LINK_PARTNER_NEXT_PAGE 0x08 /* #define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER  8 */
 434 #define PHY_1000_CONTROL           0x09 /* #define TRU_MI_1000BASET_CONTROL_REGISTER       9 */
 435 #define PHY_1000_STATUS            0x0A /* #define TRU_MI_1000BASET_STATUS_REGISTER        10 */
 436
 437 #define PHY_EXTENDED_STATUS        0x0F /* #define TRU_MI_EXTENDED_STATUS_REGISTER         15 */
 438
 439 /* some defines for modem registers that seem to be 'reserved' */
 440 #define PHY_INDEX_REG              0x10
 441 #define PHY_DATA_REG               0x11
 442
 443 #define PHY_MPHY_CONTROL_REG       0x12 /* #define TRU_VMI_MPHY_CONTROL_REGISTER           18 */
 444
 445 #define PHY_LOOPBACK_CONTROL       0x13 /* #define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER     19 */
 446                                         /* #define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER     20 */
 447 #define PHY_REGISTER_MGMT_CONTROL  0x15 /* #define TRU_VMI_MI_SEQ_CONTROL_REGISTER         21 */
 448 #define PHY_CONFIG                 0x16 /* #define TRU_VMI_CONFIGURATION_REGISTER          22 */
 449 #define PHY_PHY_CONTROL            0x17 /* #define TRU_VMI_PHY_CONTROL_REGISTER            23 */
 450 #define PHY_INTERRUPT_MASK         0x18 /* #define TRU_VMI_INTERRUPT_MASK_REGISTER         24 */
 451 #define PHY_INTERRUPT_STATUS       0x19 /* #define TRU_VMI_INTERRUPT_STATUS_REGISTER       25 */
 452 #define PHY_PHY_STATUS             0x1A /* #define TRU_VMI_PHY_STATUS_REGISTER             26 */
 453 #define PHY_LED_1                  0x1B /* #define TRU_VMI_LED_CONTROL_1_REGISTER          27 */
 454 #define PHY_LED_2                  0x1C /* #define TRU_VMI_LED_CONTROL_2_REGISTER          28 */
 455                                         /* #define TRU_VMI_LINK_CONTROL_REGISTER           29 */
 456                                         /* #define TRU_VMI_TIMING_CONTROL_REGISTER */
 457
 458 #endif /* _ET1310_PHY_H_ */