drivers/gpio/gpio-s5pv210.c

   1 /*
   2  * S5PV210 - GPIOlib support
   3  *
   4  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/irq.h>
  14 #include <linux/io.h>
  15 #include <linux/gpio.h>
  16 #include <plat/gpio-core.h>
  17 #include <plat/gpio-cfg.h>
  18 #include <plat/gpio-cfg-helpers.h>
  19 #include <mach/map.h>
  20
  21 static struct s3c_gpio_cfg gpio_cfg = {
  22         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  23         .set_pull       = s3c_gpio_setpull_updown,
  24         .get_pull       = s3c_gpio_getpull_updown,
  25 };
  26
  27 static struct s3c_gpio_cfg gpio_cfg_noint = {
  28         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
  29         .set_pull       = s3c_gpio_setpull_updown,
  30         .get_pull       = s3c_gpio_getpull_updown,
  31 };
  32
  33 /* GPIO bank's base address given the index of the bank in the
  34  * list of all gpio banks.
  35  */
  36 #define S5PV210_BANK_BASE(bank_nr)      (S5P_VA_GPIO + ((bank_nr) * 0x20))
  37
  38 /*
  39  * Following are the gpio banks in v210.
  40  *
  41  * The 'config' member when left to NULL, is initialized to the default
  42  * structure gpio_cfg in the init function below.
  43  *
  44  * The 'base' member is also initialized in the init function below.
  45  * Note: The initialization of 'base' member of s3c_gpio_chip structure
  46  * uses the above macro and depends on the banks being listed in order here.
  47  */
  48 static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
  49         {
  50                 .chip   = {
  51                         .base   = S5PV210_GPA0(0),
  52                         .ngpio  = S5PV210_GPIO_A0_NR,
  53                         .label  = "GPA0",
  54                 },
  55         }, {
  56                 .chip   = {
  57                         .base   = S5PV210_GPA1(0),
  58                         .ngpio  = S5PV210_GPIO_A1_NR,
  59                         .label  = "GPA1",
  60                 },
  61         }, {
  62                 .chip   = {
  63                         .base   = S5PV210_GPB(0),
  64                         .ngpio  = S5PV210_GPIO_B_NR,
  65                         .label  = "GPB",
  66                 },
  67         }, {
  68                 .chip   = {
  69                         .base   = S5PV210_GPC0(0),
  70                         .ngpio  = S5PV210_GPIO_C0_NR,
  71                         .label  = "GPC0",
  72                 },
  73         }, {
  74                 .chip   = {
  75                         .base   = S5PV210_GPC1(0),
  76                         .ngpio  = S5PV210_GPIO_C1_NR,
  77                         .label  = "GPC1",
  78                 },
  79         }, {
  80                 .chip   = {
  81                         .base   = S5PV210_GPD0(0),
  82                         .ngpio  = S5PV210_GPIO_D0_NR,
  83                         .label  = "GPD0",
  84                 },
  85         }, {
  86                 .chip   = {
  87                         .base   = S5PV210_GPD1(0),
  88                         .ngpio  = S5PV210_GPIO_D1_NR,
  89                         .label  = "GPD1",
  90                 },
  91         }, {
  92                 .chip   = {
  93                         .base   = S5PV210_GPE0(0),
  94                         .ngpio  = S5PV210_GPIO_E0_NR,
  95                         .label  = "GPE0",
  96                 },
  97         }, {
  98                 .chip   = {
  99                         .base   = S5PV210_GPE1(0),
 100                         .ngpio  = S5PV210_GPIO_E1_NR,
 101                         .label  = "GPE1",
 102                 },
 103         }, {
 104                 .chip   = {
 105                         .base   = S5PV210_GPF0(0),
 106                         .ngpio  = S5PV210_GPIO_F0_NR,
 107                         .label  = "GPF0",
 108                 },
 109         }, {
 110                 .chip   = {
 111                         .base   = S5PV210_GPF1(0),
 112                         .ngpio  = S5PV210_GPIO_F1_NR,
 113                         .label  = "GPF1",
 114                 },
 115         }, {
 116                 .chip   = {
 117                         .base   = S5PV210_GPF2(0),
 118                         .ngpio  = S5PV210_GPIO_F2_NR,
 119                         .label  = "GPF2",
 120                 },
 121         }, {
 122                 .chip   = {
 123                         .base   = S5PV210_GPF3(0),
 124                         .ngpio  = S5PV210_GPIO_F3_NR,
 125                         .label  = "GPF3",
 126                 },
 127         }, {
 128                 .chip   = {
 129                         .base   = S5PV210_GPG0(0),
 130                         .ngpio  = S5PV210_GPIO_G0_NR,
 131                         .label  = "GPG0",
 132                 },
 133         }, {
 134                 .chip   = {
 135                         .base   = S5PV210_GPG1(0),
 136                         .ngpio  = S5PV210_GPIO_G1_NR,
 137                         .label  = "GPG1",
 138                 },
 139         }, {
 140                 .chip   = {
 141                         .base   = S5PV210_GPG2(0),
 142                         .ngpio  = S5PV210_GPIO_G2_NR,
 143                         .label  = "GPG2",
 144                 },
 145         }, {
 146                 .chip   = {
 147                         .base   = S5PV210_GPG3(0),
 148                         .ngpio  = S5PV210_GPIO_G3_NR,
 149                         .label  = "GPG3",
 150                 },
 151         }, {
 152                 .config = &gpio_cfg_noint,
 153                 .chip   = {
 154                         .base   = S5PV210_GPI(0),
 155                         .ngpio  = S5PV210_GPIO_I_NR,
 156                         .label  = "GPI",
 157                 },
 158         }, {
 159                 .chip   = {
 160                         .base   = S5PV210_GPJ0(0),
 161                         .ngpio  = S5PV210_GPIO_J0_NR,
 162                         .label  = "GPJ0",
 163                 },
 164         }, {
 165                 .chip   = {
 166                         .base   = S5PV210_GPJ1(0),
 167                         .ngpio  = S5PV210_GPIO_J1_NR,
 168                         .label  = "GPJ1",
 169                 },
 170         }, {
 171                 .chip   = {
 172                         .base   = S5PV210_GPJ2(0),
 173                         .ngpio  = S5PV210_GPIO_J2_NR,
 174                         .label  = "GPJ2",
 175                 },
 176         }, {
 177                 .chip   = {
 178                         .base   = S5PV210_GPJ3(0),
 179                         .ngpio  = S5PV210_GPIO_J3_NR,
 180                         .label  = "GPJ3",
 181                 },
 182         }, {
 183                 .chip   = {
 184                         .base   = S5PV210_GPJ4(0),
 185                         .ngpio  = S5PV210_GPIO_J4_NR,
 186                         .label  = "GPJ4",
 187                 },
 188         }, {
 189                 .config = &gpio_cfg_noint,
 190                 .chip   = {
 191                         .base   = S5PV210_MP01(0),
 192                         .ngpio  = S5PV210_GPIO_MP01_NR,
 193                         .label  = "MP01",
 194                 },
 195         }, {
 196                 .config = &gpio_cfg_noint,
 197                 .chip   = {
 198                         .base   = S5PV210_MP02(0),
 199                         .ngpio  = S5PV210_GPIO_MP02_NR,
 200                         .label  = "MP02",
 201                 },
 202         }, {
 203                 .config = &gpio_cfg_noint,
 204                 .chip   = {
 205                         .base   = S5PV210_MP03(0),
 206                         .ngpio  = S5PV210_GPIO_MP03_NR,
 207                         .label  = "MP03",
 208                 },
 209         }, {
 210                 .config = &gpio_cfg_noint,
 211                 .chip   = {
 212                         .base   = S5PV210_MP04(0),
 213                         .ngpio  = S5PV210_GPIO_MP04_NR,
 214                         .label  = "MP04",
 215                 },
 216         }, {
 217                 .config = &gpio_cfg_noint,
 218                 .chip   = {
 219                         .base   = S5PV210_MP05(0),
 220                         .ngpio  = S5PV210_GPIO_MP05_NR,
 221                         .label  = "MP05",
 222                 },
 223         }, {
 224                 .base   = (S5P_VA_GPIO + 0xC00),
 225                 .config = &gpio_cfg_noint,
 226                 .irq_base = IRQ_EINT(0),
 227                 .chip   = {
 228                         .base   = S5PV210_GPH0(0),
 229                         .ngpio  = S5PV210_GPIO_H0_NR,
 230                         .label  = "GPH0",
 231                         .to_irq = samsung_gpiolib_to_irq,
 232                 },
 233         }, {
 234                 .base   = (S5P_VA_GPIO + 0xC20),
 235                 .config = &gpio_cfg_noint,
 236                 .irq_base = IRQ_EINT(8),
 237                 .chip   = {
 238                         .base   = S5PV210_GPH1(0),
 239                         .ngpio  = S5PV210_GPIO_H1_NR,
 240                         .label  = "GPH1",
 241                         .to_irq = samsung_gpiolib_to_irq,
 242                 },
 243         }, {
 244                 .base   = (S5P_VA_GPIO + 0xC40),
 245                 .config = &gpio_cfg_noint,
 246                 .irq_base = IRQ_EINT(16),
 247                 .chip   = {
 248                         .base   = S5PV210_GPH2(0),
 249                         .ngpio  = S5PV210_GPIO_H2_NR,
 250                         .label  = "GPH2",
 251                         .to_irq = samsung_gpiolib_to_irq,
 252                 },
 253         }, {
 254                 .base   = (S5P_VA_GPIO + 0xC60),
 255                 .config = &gpio_cfg_noint,
 256                 .irq_base = IRQ_EINT(24),
 257                 .chip   = {
 258                         .base   = S5PV210_GPH3(0),
 259                         .ngpio  = S5PV210_GPIO_H3_NR,
 260                         .label  = "GPH3",
 261                         .to_irq = samsung_gpiolib_to_irq,
 262                 },
 263         },
 264 };
 265
 266 static __init int s5pv210_gpiolib_init(void)
 267 {
 268         struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
 269         int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
 270         int gpioint_group = 0;
 271         int i = 0;
 272
 273         for (i = 0; i < nr_chips; i++, chip++) {
 274                 if (chip->config == NULL) {
 275                         chip->config = &gpio_cfg;
 276                         chip->group = gpioint_group++;
 277                 }
 278                 if (chip->base == NULL)
 279                         chip->base = S5PV210_BANK_BASE(i);
 280         }
 281
 282         samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
 283         s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
 284
 285         return 0;
 286 }
 287 core_initcall(s5pv210_gpiolib_init);