arch/arm/mach-ux500/board-mop500-sdi.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/gpio.h>
  10 #include <linux/amba/bus.h>
  11 #include <linux/amba/mmci.h>
  12 #include <linux/mmc/host.h>
  13 #include <linux/platform_device.h>
  14
  15 #include <asm/mach-types.h>
  16 #include <plat/ste_dma40.h>
  17 #include <mach/devices.h>
  18 #include <mach/hardware.h>
  19
  20 #include "devices-db8500.h"
  21 #include "board-mop500.h"
  22 #include "ste-dma40-db8500.h"
  23
  24 /*
  25  * SDI 0 (MicroSD slot)
  26  */
  27
  28 /* MMCIPOWER bits */
  29 #define MCI_DATA2DIREN          (1 << 2)
  30 #define MCI_CMDDIREN            (1 << 3)
  31 #define MCI_DATA0DIREN          (1 << 4)
  32 #define MCI_DATA31DIREN         (1 << 5)
  33 #define MCI_FBCLKEN             (1 << 7)
  34
  35 static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
  36                                    unsigned char power_mode)
  37 {
  38         if (power_mode == MMC_POWER_UP)
  39                 gpio_set_value_cansleep(GPIO_SDMMC_EN, 1);
  40         else if (power_mode == MMC_POWER_OFF)
  41                 gpio_set_value_cansleep(GPIO_SDMMC_EN, 0);
  42
  43         return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
  44                MCI_DATA2DIREN | MCI_DATA31DIREN;
  45 }
  46
  47 #ifdef CONFIG_STE_DMA40
  48 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
  49         .mode = STEDMA40_MODE_LOGICAL,
  50         .dir = STEDMA40_PERIPH_TO_MEM,
  51         .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
  52         .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
  53         .src_info.data_width = STEDMA40_WORD_WIDTH,
  54         .dst_info.data_width = STEDMA40_WORD_WIDTH,
  55 };
  56
  57 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
  58         .mode = STEDMA40_MODE_LOGICAL,
  59         .dir = STEDMA40_MEM_TO_PERIPH,
  60         .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
  61         .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
  62         .src_info.data_width = STEDMA40_WORD_WIDTH,
  63         .dst_info.data_width = STEDMA40_WORD_WIDTH,
  64 };
  65 #endif
  66
  67 static struct mmci_platform_data mop500_sdi0_data = {
  68         .vdd_handler    = mop500_sdi0_vdd_handler,
  69         .ocr_mask       = MMC_VDD_29_30,
  70         .f_max          = 100000000,
  71         .capabilities   = MMC_CAP_4_BIT_DATA,
  72         .gpio_wp        = -1,
  73 #ifdef CONFIG_STE_DMA40
  74         .dma_filter     = stedma40_filter,
  75         .dma_rx_param   = &mop500_sdi0_dma_cfg_rx,
  76         .dma_tx_param   = &mop500_sdi0_dma_cfg_tx,
  77 #endif
  78 };
  79
  80 /* GPIO pins used by the sdi0 level shifter */
  81 static int sdi0_en = -1;
  82 static int sdi0_vsel = -1;
  83
  84 static void sdi0_configure(void)
  85 {
  86         int ret;
  87
  88         ret = gpio_request(sdi0_en, "level shifter enable");
  89         if (!ret)
  90                 ret = gpio_request(sdi0_vsel,
  91                                    "level shifter 1v8-3v select");
  92
  93         if (ret) {
  94                 pr_warning("unable to config sdi0 gpios for level shifter.\n");
  95                 return;
  96         }
  97
  98         /* Select the default 2.9V and enable level shifter */
  99         gpio_direction_output(sdi0_vsel, 0);
 100         gpio_direction_output(sdi0_en, 1);
 101
 102         /* Add the device, force v2 to subrevision 1 */
 103         if (cpu_is_u8500v2())
 104                 db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
 105         else
 106                 db8500_add_sdi0(&mop500_sdi0_data, 0);
 107 }
 108
 109 void mop500_sdi_tc35892_init(void)
 110 {
 111         mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
 112         sdi0_en = GPIO_SDMMC_EN;
 113         sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
 114         sdi0_configure();
 115 }
 116
 117 /*
 118  * SDI 2 (POP eMMC, not on DB8500ed)
 119  */
 120
 121 #ifdef CONFIG_STE_DMA40
 122 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
 123         .mode = STEDMA40_MODE_LOGICAL,
 124         .dir = STEDMA40_PERIPH_TO_MEM,
 125         .src_dev_type =  DB8500_DMA_DEV28_SD_MM2_RX,
 126         .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
 127         .src_info.data_width = STEDMA40_WORD_WIDTH,
 128         .dst_info.data_width = STEDMA40_WORD_WIDTH,
 129 };
 130
 131 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 132         .mode = STEDMA40_MODE_LOGICAL,
 133         .dir = STEDMA40_MEM_TO_PERIPH,
 134         .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
 135         .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
 136         .src_info.data_width = STEDMA40_WORD_WIDTH,
 137         .dst_info.data_width = STEDMA40_WORD_WIDTH,
 138 };
 139 #endif
 140
 141 static struct mmci_platform_data mop500_sdi2_data = {
 142         .ocr_mask       = MMC_VDD_165_195,
 143         .f_max          = 100000000,
 144         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 145         .gpio_cd        = -1,
 146         .gpio_wp        = -1,
 147 #ifdef CONFIG_STE_DMA40
 148         .dma_filter     = stedma40_filter,
 149         .dma_rx_param   = &mop500_sdi2_dma_cfg_rx,
 150         .dma_tx_param   = &mop500_sdi2_dma_cfg_tx,
 151 #endif
 152 };
 153
 154 /*
 155  * SDI 4 (on-board eMMC)
 156  */
 157
 158 #ifdef CONFIG_STE_DMA40
 159 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
 160         .mode = STEDMA40_MODE_LOGICAL,
 161         .dir = STEDMA40_PERIPH_TO_MEM,
 162         .src_dev_type =  DB8500_DMA_DEV42_SD_MM4_RX,
 163         .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
 164         .src_info.data_width = STEDMA40_WORD_WIDTH,
 165         .dst_info.data_width = STEDMA40_WORD_WIDTH,
 166 };
 167
 168 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 169         .mode = STEDMA40_MODE_LOGICAL,
 170         .dir = STEDMA40_MEM_TO_PERIPH,
 171         .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
 172         .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
 173         .src_info.data_width = STEDMA40_WORD_WIDTH,
 174         .dst_info.data_width = STEDMA40_WORD_WIDTH,
 175 };
 176 #endif
 177
 178 static struct mmci_platform_data mop500_sdi4_data = {
 179         .ocr_mask       = MMC_VDD_29_30,
 180         .f_max          = 100000000,
 181         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
 182                           MMC_CAP_MMC_HIGHSPEED,
 183         .gpio_cd        = -1,
 184         .gpio_wp        = -1,
 185 #ifdef CONFIG_STE_DMA40
 186         .dma_filter     = stedma40_filter,
 187         .dma_rx_param   = &mop500_sdi4_dma_cfg_rx,
 188         .dma_tx_param   = &mop500_sdi4_dma_cfg_tx,
 189 #endif
 190 };
 191
 192 void __init mop500_sdi_init(void)
 193 {
 194         u32 periphid = 0;
 195
 196         /* v2 has a new version of this block that need to be forced */
 197         if (cpu_is_u8500v2())
 198                 periphid = 0x10480180;
 199         /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
 200         if (!cpu_is_u8500v10())
 201                 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
 202         db8500_add_sdi2(&mop500_sdi2_data, periphid);
 203
 204         /* On-board eMMC */
 205         db8500_add_sdi4(&mop500_sdi4_data, periphid);
 206
 207         if (machine_is_hrefv60()) {
 208                 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
 209                 sdi0_en = HREFV60_SDMMC_EN_GPIO;
 210                 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
 211                 sdi0_configure();
 212         }
 213         /*
 214          * On boards with the TC35892 GPIO expander, sdi0 will finally
 215          * be added when the TC35892 initializes and calls
 216          * mop500_sdi_tc35892_init() above.
 217          */
 218 }