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Input: wacom - revert "Cintiq 21UX2 does not have menu strips"
[linux-btrfs-devel.git] / sound / pci / hda / hda_intel.c
blob486f6deb3eee952ab810750ecee652c23acc2b11
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70 #endif
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
82 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, int, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97 #endif
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102 #endif
103
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
109
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117 #endif
118
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
122 "{Intel, ICH7},"
123 "{Intel, ESB2},"
124 "{Intel, ICH8},"
125 "{Intel, ICH9},"
126 "{Intel, ICH10},"
127 "{Intel, PCH},"
128 "{Intel, CPT},"
129 "{Intel, PPT},"
130 "{Intel, PBG},"
131 "{Intel, SCH},"
132 "{ATI, SB450},"
133 "{ATI, SB600},"
134 "{ATI, RS600},"
135 "{ATI, RS690},"
136 "{ATI, RS780},"
137 "{ATI, R600},"
138 "{ATI, RV630},"
139 "{ATI, RV610},"
140 "{ATI, RV670},"
141 "{ATI, RV635},"
142 "{ATI, RV620},"
143 "{ATI, RV770},"
144 "{VIA, VT8251},"
145 "{VIA, VT8237A},"
146 "{SiS, SIS966},"
147 "{ULI, M5461}}");
148 MODULE_DESCRIPTION("Intel HDA driver");
149
150 #ifdef CONFIG_SND_VERBOSE_PRINTK
151 #define SFX /* nop */
152 #else
153 #define SFX "hda-intel: "
154 #endif
155
156 /*
157 * registers
158 */
159 #define ICH6_REG_GCAP 0x00
160 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
161 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
162 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
163 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
164 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
165 #define ICH6_REG_VMIN 0x02
166 #define ICH6_REG_VMAJ 0x03
167 #define ICH6_REG_OUTPAY 0x04
168 #define ICH6_REG_INPAY 0x06
169 #define ICH6_REG_GCTL 0x08
170 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
171 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
172 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
173 #define ICH6_REG_WAKEEN 0x0c
174 #define ICH6_REG_STATESTS 0x0e
175 #define ICH6_REG_GSTS 0x10
176 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
177 #define ICH6_REG_INTCTL 0x20
178 #define ICH6_REG_INTSTS 0x24
179 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
180 #define ICH6_REG_SYNC 0x34
181 #define ICH6_REG_CORBLBASE 0x40
182 #define ICH6_REG_CORBUBASE 0x44
183 #define ICH6_REG_CORBWP 0x48
184 #define ICH6_REG_CORBRP 0x4a
185 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
186 #define ICH6_REG_CORBCTL 0x4c
187 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
188 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
189 #define ICH6_REG_CORBSTS 0x4d
190 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
191 #define ICH6_REG_CORBSIZE 0x4e
192
193 #define ICH6_REG_RIRBLBASE 0x50
194 #define ICH6_REG_RIRBUBASE 0x54
195 #define ICH6_REG_RIRBWP 0x58
196 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
197 #define ICH6_REG_RINTCNT 0x5a
198 #define ICH6_REG_RIRBCTL 0x5c
199 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
200 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
201 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
202 #define ICH6_REG_RIRBSTS 0x5d
203 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
204 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
205 #define ICH6_REG_RIRBSIZE 0x5e
206
207 #define ICH6_REG_IC 0x60
208 #define ICH6_REG_IR 0x64
209 #define ICH6_REG_IRS 0x68
210 #define ICH6_IRS_VALID (1<<1)
211 #define ICH6_IRS_BUSY (1<<0)
212
213 #define ICH6_REG_DPLBASE 0x70
214 #define ICH6_REG_DPUBASE 0x74
215 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
216
217 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
218 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
219
220 /* stream register offsets from stream base */
221 #define ICH6_REG_SD_CTL 0x00
222 #define ICH6_REG_SD_STS 0x03
223 #define ICH6_REG_SD_LPIB 0x04
224 #define ICH6_REG_SD_CBL 0x08
225 #define ICH6_REG_SD_LVI 0x0c
226 #define ICH6_REG_SD_FIFOW 0x0e
227 #define ICH6_REG_SD_FIFOSIZE 0x10
228 #define ICH6_REG_SD_FORMAT 0x12
229 #define ICH6_REG_SD_BDLPL 0x18
230 #define ICH6_REG_SD_BDLPU 0x1c
231
232 /* PCI space */
233 #define ICH6_PCIREG_TCSEL 0x44
234
235 /*
236 * other constants
237 */
238
239 /* max number of SDs */
240 /* ICH, ATI and VIA have 4 playback and 4 capture */
241 #define ICH6_NUM_CAPTURE 4
242 #define ICH6_NUM_PLAYBACK 4
243
244 /* ULI has 6 playback and 5 capture */
245 #define ULI_NUM_CAPTURE 5
246 #define ULI_NUM_PLAYBACK 6
247
248 /* ATI HDMI has 1 playback and 0 capture */
249 #define ATIHDMI_NUM_CAPTURE 0
250 #define ATIHDMI_NUM_PLAYBACK 1
251
252 /* TERA has 4 playback and 3 capture */
253 #define TERA_NUM_CAPTURE 3
254 #define TERA_NUM_PLAYBACK 4
255
256 /* this number is statically defined for simplicity */
257 #define MAX_AZX_DEV 16
258
259 /* max number of fragments - we may use more if allocating more pages for BDL */
260 #define BDL_SIZE 4096
261 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
262 #define AZX_MAX_FRAG 32
263 /* max buffer size - no h/w limit, you can increase as you like */
264 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
265
266 /* RIRB int mask: overrun[2], response[0] */
267 #define RIRB_INT_RESPONSE 0x01
268 #define RIRB_INT_OVERRUN 0x04
269 #define RIRB_INT_MASK 0x05
270
271 /* STATESTS int mask: S3,SD2,SD1,SD0 */
272 #define AZX_MAX_CODECS 8
273 #define AZX_DEFAULT_CODECS 4
274 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
275
276 /* SD_CTL bits */
277 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
278 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
279 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
280 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
281 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
282 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
283 #define SD_CTL_STREAM_TAG_SHIFT 20
284
285 /* SD_CTL and SD_STS */
286 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
287 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
288 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
289 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
290 SD_INT_COMPLETE)
291
292 /* SD_STS */
293 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
294
295 /* INTCTL and INTSTS */
296 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
297 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
298 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
299
300 /* below are so far hardcoded - should read registers in future */
301 #define ICH6_MAX_CORB_ENTRIES 256
302 #define ICH6_MAX_RIRB_ENTRIES 256
303
304 /* position fix mode */
305 enum {
306 POS_FIX_AUTO,
307 POS_FIX_LPIB,
308 POS_FIX_POSBUF,
309 POS_FIX_VIACOMBO,
310 };
311
312 /* Defines for ATI HD Audio support in SB450 south bridge */
313 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
314 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
315
316 /* Defines for Nvidia HDA support */
317 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
318 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
319 #define NVIDIA_HDA_ISTRM_COH 0x4d
320 #define NVIDIA_HDA_OSTRM_COH 0x4c
321 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
322
323 /* Defines for Intel SCH HDA snoop control */
324 #define INTEL_SCH_HDA_DEVC 0x78
325 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
326
327 /* Define IN stream 0 FIFO size offset in VIA controller */
328 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
329 /* Define VIA HD Audio Device ID*/
330 #define VIA_HDAC_DEVICE_ID 0x3288
331
332 /* HD Audio class code */
333 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
334
335 /*
336 */
337
338 struct azx_dev {
339 struct snd_dma_buffer bdl; /* BDL buffer */
340 u32 *posbuf; /* position buffer pointer */
341
342 unsigned int bufsize; /* size of the play buffer in bytes */
343 unsigned int period_bytes; /* size of the period in bytes */
344 unsigned int frags; /* number for period in the play buffer */
345 unsigned int fifo_size; /* FIFO size */
346 unsigned long start_wallclk; /* start + minimum wallclk */
347 unsigned long period_wallclk; /* wallclk for period */
348
349 void __iomem *sd_addr; /* stream descriptor pointer */
350
351 u32 sd_int_sta_mask; /* stream int status mask */
352
353 /* pcm support */
354 struct snd_pcm_substream *substream; /* assigned substream,
355 * set in PCM open
356 */
357 unsigned int format_val; /* format value to be set in the
358 * controller and the codec
359 */
360 unsigned char stream_tag; /* assigned stream */
361 unsigned char index; /* stream index */
362 int device; /* last device number assigned to */
363
364 unsigned int opened :1;
365 unsigned int running :1;
366 unsigned int irq_pending :1;
367 /*
368 * For VIA:
369 * A flag to ensure DMA position is 0
370 * when link position is not greater than FIFO size
371 */
372 unsigned int insufficient :1;
373 };
374
375 /* CORB/RIRB */
376 struct azx_rb {
377 u32 *buf; /* CORB/RIRB buffer
378 * Each CORB entry is 4byte, RIRB is 8byte
379 */
380 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
381 /* for RIRB */
382 unsigned short rp, wp; /* read/write pointers */
383 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
384 u32 res[AZX_MAX_CODECS]; /* last read value */
385 };
386
387 struct azx {
388 struct snd_card *card;
389 struct pci_dev *pci;
390 int dev_index;
391
392 /* chip type specific */
393 int driver_type;
394 unsigned int driver_caps;
395 int playback_streams;
396 int playback_index_offset;
397 int capture_streams;
398 int capture_index_offset;
399 int num_streams;
400
401 /* pci resources */
402 unsigned long addr;
403 void __iomem *remap_addr;
404 int irq;
405
406 /* locks */
407 spinlock_t reg_lock;
408 struct mutex open_mutex;
409
410 /* streams (x num_streams) */
411 struct azx_dev *azx_dev;
412
413 /* PCM */
414 struct snd_pcm *pcm[HDA_MAX_PCMS];
415
416 /* HD codec */
417 unsigned short codec_mask;
418 int codec_probe_mask; /* copied from probe_mask option */
419 struct hda_bus *bus;
420 unsigned int beep_mode;
421
422 /* CORB/RIRB */
423 struct azx_rb corb;
424 struct azx_rb rirb;
425
426 /* CORB/RIRB and position buffers */
427 struct snd_dma_buffer rb;
428 struct snd_dma_buffer posbuf;
429
430 /* flags */
431 int position_fix[2]; /* for both playback/capture streams */
432 int poll_count;
433 unsigned int running :1;
434 unsigned int initialized :1;
435 unsigned int single_cmd :1;
436 unsigned int polling_mode :1;
437 unsigned int msi :1;
438 unsigned int irq_pending_warned :1;
439 unsigned int probing :1; /* codec probing phase */
440
441 /* for debugging */
442 unsigned int last_cmd[AZX_MAX_CODECS];
443
444 /* for pending irqs */
445 struct work_struct irq_pending_work;
446
447 /* reboot notifier (for mysterious hangup problem at power-down) */
448 struct notifier_block reboot_notifier;
449 };
450
451 /* driver types */
452 enum {
453 AZX_DRIVER_ICH,
454 AZX_DRIVER_PCH,
455 AZX_DRIVER_SCH,
456 AZX_DRIVER_ATI,
457 AZX_DRIVER_ATIHDMI,
458 AZX_DRIVER_VIA,
459 AZX_DRIVER_SIS,
460 AZX_DRIVER_ULI,
461 AZX_DRIVER_NVIDIA,
462 AZX_DRIVER_TERA,
463 AZX_DRIVER_CTX,
464 AZX_DRIVER_GENERIC,
465 AZX_NUM_DRIVERS, /* keep this as last entry */
466 };
467
468 /* driver quirks (capabilities) */
469 /* bits 0-7 are used for indicating driver type */
470 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
471 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
472 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
473 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
474 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
475 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
476 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
477 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
478 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
479 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
480 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
481 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
482
483 /* quirks for ATI SB / AMD Hudson */
484 #define AZX_DCAPS_PRESET_ATI_SB \
485 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
486 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
487
488 /* quirks for ATI/AMD HDMI */
489 #define AZX_DCAPS_PRESET_ATI_HDMI \
490 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
491
492 /* quirks for Nvidia */
493 #define AZX_DCAPS_PRESET_NVIDIA \
494 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
495
496 static char *driver_short_names[] __devinitdata = {
497 [AZX_DRIVER_ICH] = "HDA Intel",
498 [AZX_DRIVER_PCH] = "HDA Intel PCH",
499 [AZX_DRIVER_SCH] = "HDA Intel MID",
500 [AZX_DRIVER_ATI] = "HDA ATI SB",
501 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
502 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
503 [AZX_DRIVER_SIS] = "HDA SIS966",
504 [AZX_DRIVER_ULI] = "HDA ULI M5461",
505 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
506 [AZX_DRIVER_TERA] = "HDA Teradici",
507 [AZX_DRIVER_CTX] = "HDA Creative",
508 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
509 };
510
511 /*
512 * macros for easy use
513 */
514 #define azx_writel(chip,reg,value) \
515 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
516 #define azx_readl(chip,reg) \
517 readl((chip)->remap_addr + ICH6_REG_##reg)
518 #define azx_writew(chip,reg,value) \
519 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
520 #define azx_readw(chip,reg) \
521 readw((chip)->remap_addr + ICH6_REG_##reg)
522 #define azx_writeb(chip,reg,value) \
523 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
524 #define azx_readb(chip,reg) \
525 readb((chip)->remap_addr + ICH6_REG_##reg)
526
527 #define azx_sd_writel(dev,reg,value) \
528 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
529 #define azx_sd_readl(dev,reg) \
530 readl((dev)->sd_addr + ICH6_REG_##reg)
531 #define azx_sd_writew(dev,reg,value) \
532 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
533 #define azx_sd_readw(dev,reg) \
534 readw((dev)->sd_addr + ICH6_REG_##reg)
535 #define azx_sd_writeb(dev,reg,value) \
536 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
537 #define azx_sd_readb(dev,reg) \
538 readb((dev)->sd_addr + ICH6_REG_##reg)
539
540 /* for pcm support */
541 #define get_azx_dev(substream) (substream->runtime->private_data)
542
543 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
544 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
545 /*
546 * Interface for HD codec
547 */
548
549 /*
550 * CORB / RIRB interface
551 */
552 static int azx_alloc_cmd_io(struct azx *chip)
553 {
554 int err;
555
556 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
557 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
558 snd_dma_pci_data(chip->pci),
559 PAGE_SIZE, &chip->rb);
560 if (err < 0) {
561 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
562 return err;
563 }
564 return 0;
565 }
566
567 static void azx_init_cmd_io(struct azx *chip)
568 {
569 spin_lock_irq(&chip->reg_lock);
570 /* CORB set up */
571 chip->corb.addr = chip->rb.addr;
572 chip->corb.buf = (u32 *)chip->rb.area;
573 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
574 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
575
576 /* set the corb size to 256 entries (ULI requires explicitly) */
577 azx_writeb(chip, CORBSIZE, 0x02);
578 /* set the corb write pointer to 0 */
579 azx_writew(chip, CORBWP, 0);
580 /* reset the corb hw read pointer */
581 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
582 /* enable corb dma */
583 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
584
585 /* RIRB set up */
586 chip->rirb.addr = chip->rb.addr + 2048;
587 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
588 chip->rirb.wp = chip->rirb.rp = 0;
589 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
590 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
591 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
592
593 /* set the rirb size to 256 entries (ULI requires explicitly) */
594 azx_writeb(chip, RIRBSIZE, 0x02);
595 /* reset the rirb hw write pointer */
596 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
597 /* set N=1, get RIRB response interrupt for new entry */
598 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
599 azx_writew(chip, RINTCNT, 0xc0);
600 else
601 azx_writew(chip, RINTCNT, 1);
602 /* enable rirb dma and response irq */
603 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
604 spin_unlock_irq(&chip->reg_lock);
605 }
606
607 static void azx_free_cmd_io(struct azx *chip)
608 {
609 spin_lock_irq(&chip->reg_lock);
610 /* disable ringbuffer DMAs */
611 azx_writeb(chip, RIRBCTL, 0);
612 azx_writeb(chip, CORBCTL, 0);
613 spin_unlock_irq(&chip->reg_lock);
614 }
615
616 static unsigned int azx_command_addr(u32 cmd)
617 {
618 unsigned int addr = cmd >> 28;
619
620 if (addr >= AZX_MAX_CODECS) {
621 snd_BUG();
622 addr = 0;
623 }
624
625 return addr;
626 }
627
628 static unsigned int azx_response_addr(u32 res)
629 {
630 unsigned int addr = res & 0xf;
631
632 if (addr >= AZX_MAX_CODECS) {
633 snd_BUG();
634 addr = 0;
635 }
636
637 return addr;
638 }
639
640 /* send a command */
641 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
642 {
643 struct azx *chip = bus->private_data;
644 unsigned int addr = azx_command_addr(val);
645 unsigned int wp;
646
647 spin_lock_irq(&chip->reg_lock);
648
649 /* add command to corb */
650 wp = azx_readb(chip, CORBWP);
651 wp++;
652 wp %= ICH6_MAX_CORB_ENTRIES;
653
654 chip->rirb.cmds[addr]++;
655 chip->corb.buf[wp] = cpu_to_le32(val);
656 azx_writel(chip, CORBWP, wp);
657
658 spin_unlock_irq(&chip->reg_lock);
659
660 return 0;
661 }
662
663 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
664
665 /* retrieve RIRB entry - called from interrupt handler */
666 static void azx_update_rirb(struct azx *chip)
667 {
668 unsigned int rp, wp;
669 unsigned int addr;
670 u32 res, res_ex;
671
672 wp = azx_readb(chip, RIRBWP);
673 if (wp == chip->rirb.wp)
674 return;
675 chip->rirb.wp = wp;
676
677 while (chip->rirb.rp != wp) {
678 chip->rirb.rp++;
679 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
680
681 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
682 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
683 res = le32_to_cpu(chip->rirb.buf[rp]);
684 addr = azx_response_addr(res_ex);
685 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
686 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
687 else if (chip->rirb.cmds[addr]) {
688 chip->rirb.res[addr] = res;
689 smp_wmb();
690 chip->rirb.cmds[addr]--;
691 } else
692 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
693 "last cmd=%#08x\n",
694 res, res_ex,
695 chip->last_cmd[addr]);
696 }
697 }
698
699 /* receive a response */
700 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
701 unsigned int addr)
702 {
703 struct azx *chip = bus->private_data;
704 unsigned long timeout;
705 int do_poll = 0;
706
707 again:
708 timeout = jiffies + msecs_to_jiffies(1000);
709 for (;;) {
710 if (chip->polling_mode || do_poll) {
711 spin_lock_irq(&chip->reg_lock);
712 azx_update_rirb(chip);
713 spin_unlock_irq(&chip->reg_lock);
714 }
715 if (!chip->rirb.cmds[addr]) {
716 smp_rmb();
717 bus->rirb_error = 0;
718
719 if (!do_poll)
720 chip->poll_count = 0;
721 return chip->rirb.res[addr]; /* the last value */
722 }
723 if (time_after(jiffies, timeout))
724 break;
725 if (bus->needs_damn_long_delay)
726 msleep(2); /* temporary workaround */
727 else {
728 udelay(10);
729 cond_resched();
730 }
731 }
732
733 if (!chip->polling_mode && chip->poll_count < 2) {
734 snd_printdd(SFX "azx_get_response timeout, "
735 "polling the codec once: last cmd=0x%08x\n",
736 chip->last_cmd[addr]);
737 do_poll = 1;
738 chip->poll_count++;
739 goto again;
740 }
741
742
743 if (!chip->polling_mode) {
744 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
745 "switching to polling mode: last cmd=0x%08x\n",
746 chip->last_cmd[addr]);
747 chip->polling_mode = 1;
748 goto again;
749 }
750
751 if (chip->msi) {
752 snd_printk(KERN_WARNING SFX "No response from codec, "
753 "disabling MSI: last cmd=0x%08x\n",
754 chip->last_cmd[addr]);
755 free_irq(chip->irq, chip);
756 chip->irq = -1;
757 pci_disable_msi(chip->pci);
758 chip->msi = 0;
759 if (azx_acquire_irq(chip, 1) < 0) {
760 bus->rirb_error = 1;
761 return -1;
762 }
763 goto again;
764 }
765
766 if (chip->probing) {
767 /* If this critical timeout happens during the codec probing
768 * phase, this is likely an access to a non-existing codec
769 * slot. Better to return an error and reset the system.
770 */
771 return -1;
772 }
773
774 /* a fatal communication error; need either to reset or to fallback
775 * to the single_cmd mode
776 */
777 bus->rirb_error = 1;
778 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
779 bus->response_reset = 1;
780 return -1; /* give a chance to retry */
781 }
782
783 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
784 "switching to single_cmd mode: last cmd=0x%08x\n",
785 chip->last_cmd[addr]);
786 chip->single_cmd = 1;
787 bus->response_reset = 0;
788 /* release CORB/RIRB */
789 azx_free_cmd_io(chip);
790 /* disable unsolicited responses */
791 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
792 return -1;
793 }
794
795 /*
796 * Use the single immediate command instead of CORB/RIRB for simplicity
797 *
798 * Note: according to Intel, this is not preferred use. The command was
799 * intended for the BIOS only, and may get confused with unsolicited
800 * responses. So, we shouldn't use it for normal operation from the
801 * driver.
802 * I left the codes, however, for debugging/testing purposes.
803 */
804
805 /* receive a response */
806 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
807 {
808 int timeout = 50;
809
810 while (timeout--) {
811 /* check IRV busy bit */
812 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
813 /* reuse rirb.res as the response return value */
814 chip->rirb.res[addr] = azx_readl(chip, IR);
815 return 0;
816 }
817 udelay(1);
818 }
819 if (printk_ratelimit())
820 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
821 azx_readw(chip, IRS));
822 chip->rirb.res[addr] = -1;
823 return -EIO;
824 }
825
826 /* send a command */
827 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
828 {
829 struct azx *chip = bus->private_data;
830 unsigned int addr = azx_command_addr(val);
831 int timeout = 50;
832
833 bus->rirb_error = 0;
834 while (timeout--) {
835 /* check ICB busy bit */
836 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
837 /* Clear IRV valid bit */
838 azx_writew(chip, IRS, azx_readw(chip, IRS) |
839 ICH6_IRS_VALID);
840 azx_writel(chip, IC, val);
841 azx_writew(chip, IRS, azx_readw(chip, IRS) |
842 ICH6_IRS_BUSY);
843 return azx_single_wait_for_response(chip, addr);
844 }
845 udelay(1);
846 }
847 if (printk_ratelimit())
848 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
849 azx_readw(chip, IRS), val);
850 return -EIO;
851 }
852
853 /* receive a response */
854 static unsigned int azx_single_get_response(struct hda_bus *bus,
855 unsigned int addr)
856 {
857 struct azx *chip = bus->private_data;
858 return chip->rirb.res[addr];
859 }
860
861 /*
862 * The below are the main callbacks from hda_codec.
863 *
864 * They are just the skeleton to call sub-callbacks according to the
865 * current setting of chip->single_cmd.
866 */
867
868 /* send a command */
869 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
870 {
871 struct azx *chip = bus->private_data;
872
873 chip->last_cmd[azx_command_addr(val)] = val;
874 if (chip->single_cmd)
875 return azx_single_send_cmd(bus, val);
876 else
877 return azx_corb_send_cmd(bus, val);
878 }
879
880 /* get a response */
881 static unsigned int azx_get_response(struct hda_bus *bus,
882 unsigned int addr)
883 {
884 struct azx *chip = bus->private_data;
885 if (chip->single_cmd)
886 return azx_single_get_response(bus, addr);
887 else
888 return azx_rirb_get_response(bus, addr);
889 }
890
891 #ifdef CONFIG_SND_HDA_POWER_SAVE
892 static void azx_power_notify(struct hda_bus *bus);
893 #endif
894
895 /* reset codec link */
896 static int azx_reset(struct azx *chip, int full_reset)
897 {
898 int count;
899
900 if (!full_reset)
901 goto __skip;
902
903 /* clear STATESTS */
904 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
905
906 /* reset controller */
907 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
908
909 count = 50;
910 while (azx_readb(chip, GCTL) && --count)
911 msleep(1);
912
913 /* delay for >= 100us for codec PLL to settle per spec
914 * Rev 0.9 section 5.5.1
915 */
916 msleep(1);
917
918 /* Bring controller out of reset */
919 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
920
921 count = 50;
922 while (!azx_readb(chip, GCTL) && --count)
923 msleep(1);
924
925 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
926 msleep(1);
927
928 __skip:
929 /* check to see if controller is ready */
930 if (!azx_readb(chip, GCTL)) {
931 snd_printd(SFX "azx_reset: controller not ready!\n");
932 return -EBUSY;
933 }
934
935 /* Accept unsolicited responses */
936 if (!chip->single_cmd)
937 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
938 ICH6_GCTL_UNSOL);
939
940 /* detect codecs */
941 if (!chip->codec_mask) {
942 chip->codec_mask = azx_readw(chip, STATESTS);
943 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
944 }
945
946 return 0;
947 }
948
949
950 /*
951 * Lowlevel interface
952 */
953
954 /* enable interrupts */
955 static void azx_int_enable(struct azx *chip)
956 {
957 /* enable controller CIE and GIE */
958 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
959 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
960 }
961
962 /* disable interrupts */
963 static void azx_int_disable(struct azx *chip)
964 {
965 int i;
966
967 /* disable interrupts in stream descriptor */
968 for (i = 0; i < chip->num_streams; i++) {
969 struct azx_dev *azx_dev = &chip->azx_dev[i];
970 azx_sd_writeb(azx_dev, SD_CTL,
971 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
972 }
973
974 /* disable SIE for all streams */
975 azx_writeb(chip, INTCTL, 0);
976
977 /* disable controller CIE and GIE */
978 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
979 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
980 }
981
982 /* clear interrupts */
983 static void azx_int_clear(struct azx *chip)
984 {
985 int i;
986
987 /* clear stream status */
988 for (i = 0; i < chip->num_streams; i++) {
989 struct azx_dev *azx_dev = &chip->azx_dev[i];
990 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
991 }
992
993 /* clear STATESTS */
994 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
995
996 /* clear rirb status */
997 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
998
999 /* clear int status */
1000 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1001 }
1002
1003 /* start a stream */
1004 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1005 {
1006 /*
1007 * Before stream start, initialize parameter
1008 */
1009 azx_dev->insufficient = 1;
1010
1011 /* enable SIE */
1012 azx_writel(chip, INTCTL,
1013 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1014 /* set DMA start and interrupt mask */
1015 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1016 SD_CTL_DMA_START | SD_INT_MASK);
1017 }
1018
1019 /* stop DMA */
1020 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1021 {
1022 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1023 ~(SD_CTL_DMA_START | SD_INT_MASK));
1024 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1025 }
1026
1027 /* stop a stream */
1028 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1029 {
1030 azx_stream_clear(chip, azx_dev);
1031 /* disable SIE */
1032 azx_writel(chip, INTCTL,
1033 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1034 }
1035
1036
1037 /*
1038 * reset and start the controller registers
1039 */
1040 static void azx_init_chip(struct azx *chip, int full_reset)
1041 {
1042 if (chip->initialized)
1043 return;
1044
1045 /* reset controller */
1046 azx_reset(chip, full_reset);
1047
1048 /* initialize interrupts */
1049 azx_int_clear(chip);
1050 azx_int_enable(chip);
1051
1052 /* initialize the codec command I/O */
1053 if (!chip->single_cmd)
1054 azx_init_cmd_io(chip);
1055
1056 /* program the position buffer */
1057 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1058 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1059
1060 chip->initialized = 1;
1061 }
1062
1063 /*
1064 * initialize the PCI registers
1065 */
1066 /* update bits in a PCI register byte */
1067 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1068 unsigned char mask, unsigned char val)
1069 {
1070 unsigned char data;
1071
1072 pci_read_config_byte(pci, reg, &data);
1073 data &= ~mask;
1074 data |= (val & mask);
1075 pci_write_config_byte(pci, reg, data);
1076 }
1077
1078 static void azx_init_pci(struct azx *chip)
1079 {
1080 unsigned short snoop;
1081
1082 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1083 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1084 * Ensuring these bits are 0 clears playback static on some HD Audio
1085 * codecs.
1086 * The PCI register TCSEL is defined in the Intel manuals.
1087 */
1088 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1089 snd_printdd(SFX "Clearing TCSEL\n");
1090 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1091 }
1092
1093 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1094 * we need to enable snoop.
1095 */
1096 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1097 snd_printdd(SFX "Enabling ATI snoop\n");
1098 update_pci_byte(chip->pci,
1099 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1100 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1101 }
1102
1103 /* For NVIDIA HDA, enable snoop */
1104 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1105 snd_printdd(SFX "Enabling Nvidia snoop\n");
1106 update_pci_byte(chip->pci,
1107 NVIDIA_HDA_TRANSREG_ADDR,
1108 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1109 update_pci_byte(chip->pci,
1110 NVIDIA_HDA_ISTRM_COH,
1111 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1112 update_pci_byte(chip->pci,
1113 NVIDIA_HDA_OSTRM_COH,
1114 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1115 }
1116
1117 /* Enable SCH/PCH snoop if needed */
1118 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1119 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1120 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1121 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1122 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1123 pci_read_config_word(chip->pci,
1124 INTEL_SCH_HDA_DEVC, &snoop);
1125 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1126 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1127 ? "Failed" : "OK");
1128 }
1129 }
1130 }
1131
1132
1133 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1134
1135 /*
1136 * interrupt handler
1137 */
1138 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1139 {
1140 struct azx *chip = dev_id;
1141 struct azx_dev *azx_dev;
1142 u32 status;
1143 u8 sd_status;
1144 int i, ok;
1145
1146 spin_lock(&chip->reg_lock);
1147
1148 status = azx_readl(chip, INTSTS);
1149 if (status == 0) {
1150 spin_unlock(&chip->reg_lock);
1151 return IRQ_NONE;
1152 }
1153
1154 for (i = 0; i < chip->num_streams; i++) {
1155 azx_dev = &chip->azx_dev[i];
1156 if (status & azx_dev->sd_int_sta_mask) {
1157 sd_status = azx_sd_readb(azx_dev, SD_STS);
1158 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1159 if (!azx_dev->substream || !azx_dev->running ||
1160 !(sd_status & SD_INT_COMPLETE))
1161 continue;
1162 /* check whether this IRQ is really acceptable */
1163 ok = azx_position_ok(chip, azx_dev);
1164 if (ok == 1) {
1165 azx_dev->irq_pending = 0;
1166 spin_unlock(&chip->reg_lock);
1167 snd_pcm_period_elapsed(azx_dev->substream);
1168 spin_lock(&chip->reg_lock);
1169 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1170 /* bogus IRQ, process it later */
1171 azx_dev->irq_pending = 1;
1172 queue_work(chip->bus->workq,
1173 &chip->irq_pending_work);
1174 }
1175 }
1176 }
1177
1178 /* clear rirb int */
1179 status = azx_readb(chip, RIRBSTS);
1180 if (status & RIRB_INT_MASK) {
1181 if (status & RIRB_INT_RESPONSE) {
1182 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1183 udelay(80);
1184 azx_update_rirb(chip);
1185 }
1186 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1187 }
1188
1189 #if 0
1190 /* clear state status int */
1191 if (azx_readb(chip, STATESTS) & 0x04)
1192 azx_writeb(chip, STATESTS, 0x04);
1193 #endif
1194 spin_unlock(&chip->reg_lock);
1195
1196 return IRQ_HANDLED;
1197 }
1198
1199
1200 /*
1201 * set up a BDL entry
1202 */
1203 static int setup_bdle(struct snd_pcm_substream *substream,
1204 struct azx_dev *azx_dev, u32 **bdlp,
1205 int ofs, int size, int with_ioc)
1206 {
1207 u32 *bdl = *bdlp;
1208
1209 while (size > 0) {
1210 dma_addr_t addr;
1211 int chunk;
1212
1213 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1214 return -EINVAL;
1215
1216 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1217 /* program the address field of the BDL entry */
1218 bdl[0] = cpu_to_le32((u32)addr);
1219 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1220 /* program the size field of the BDL entry */
1221 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1222 bdl[2] = cpu_to_le32(chunk);
1223 /* program the IOC to enable interrupt
1224 * only when the whole fragment is processed
1225 */
1226 size -= chunk;
1227 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1228 bdl += 4;
1229 azx_dev->frags++;
1230 ofs += chunk;
1231 }
1232 *bdlp = bdl;
1233 return ofs;
1234 }
1235
1236 /*
1237 * set up BDL entries
1238 */
1239 static int azx_setup_periods(struct azx *chip,
1240 struct snd_pcm_substream *substream,
1241 struct azx_dev *azx_dev)
1242 {
1243 u32 *bdl;
1244 int i, ofs, periods, period_bytes;
1245 int pos_adj;
1246
1247 /* reset BDL address */
1248 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1249 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1250
1251 period_bytes = azx_dev->period_bytes;
1252 periods = azx_dev->bufsize / period_bytes;
1253
1254 /* program the initial BDL entries */
1255 bdl = (u32 *)azx_dev->bdl.area;
1256 ofs = 0;
1257 azx_dev->frags = 0;
1258 pos_adj = bdl_pos_adj[chip->dev_index];
1259 if (pos_adj > 0) {
1260 struct snd_pcm_runtime *runtime = substream->runtime;
1261 int pos_align = pos_adj;
1262 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1263 if (!pos_adj)
1264 pos_adj = pos_align;
1265 else
1266 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1267 pos_align;
1268 pos_adj = frames_to_bytes(runtime, pos_adj);
1269 if (pos_adj >= period_bytes) {
1270 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1271 bdl_pos_adj[chip->dev_index]);
1272 pos_adj = 0;
1273 } else {
1274 ofs = setup_bdle(substream, azx_dev,
1275 &bdl, ofs, pos_adj,
1276 !substream->runtime->no_period_wakeup);
1277 if (ofs < 0)
1278 goto error;
1279 }
1280 } else
1281 pos_adj = 0;
1282 for (i = 0; i < periods; i++) {
1283 if (i == periods - 1 && pos_adj)
1284 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1285 period_bytes - pos_adj, 0);
1286 else
1287 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1288 period_bytes,
1289 !substream->runtime->no_period_wakeup);
1290 if (ofs < 0)
1291 goto error;
1292 }
1293 return 0;
1294
1295 error:
1296 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1297 azx_dev->bufsize, period_bytes);
1298 return -EINVAL;
1299 }
1300
1301 /* reset stream */
1302 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1303 {
1304 unsigned char val;
1305 int timeout;
1306
1307 azx_stream_clear(chip, azx_dev);
1308
1309 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1310 SD_CTL_STREAM_RESET);
1311 udelay(3);
1312 timeout = 300;
1313 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1314 --timeout)
1315 ;
1316 val &= ~SD_CTL_STREAM_RESET;
1317 azx_sd_writeb(azx_dev, SD_CTL, val);
1318 udelay(3);
1319
1320 timeout = 300;
1321 /* waiting for hardware to report that the stream is out of reset */
1322 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1323 --timeout)
1324 ;
1325
1326 /* reset first position - may not be synced with hw at this time */
1327 *azx_dev->posbuf = 0;
1328 }
1329
1330 /*
1331 * set up the SD for streaming
1332 */
1333 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1334 {
1335 /* make sure the run bit is zero for SD */
1336 azx_stream_clear(chip, azx_dev);
1337 /* program the stream_tag */
1338 azx_sd_writel(azx_dev, SD_CTL,
1339 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1340 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1341
1342 /* program the length of samples in cyclic buffer */
1343 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1344
1345 /* program the stream format */
1346 /* this value needs to be the same as the one programmed */
1347 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1348
1349 /* program the stream LVI (last valid index) of the BDL */
1350 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1351
1352 /* program the BDL address */
1353 /* lower BDL address */
1354 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1355 /* upper BDL address */
1356 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1357
1358 /* enable the position buffer */
1359 if (chip->position_fix[0] != POS_FIX_LPIB ||
1360 chip->position_fix[1] != POS_FIX_LPIB) {
1361 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1362 azx_writel(chip, DPLBASE,
1363 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1364 }
1365
1366 /* set the interrupt enable bits in the descriptor control register */
1367 azx_sd_writel(azx_dev, SD_CTL,
1368 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1369
1370 return 0;
1371 }
1372
1373 /*
1374 * Probe the given codec address
1375 */
1376 static int probe_codec(struct azx *chip, int addr)
1377 {
1378 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1379 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1380 unsigned int res;
1381
1382 mutex_lock(&chip->bus->cmd_mutex);
1383 chip->probing = 1;
1384 azx_send_cmd(chip->bus, cmd);
1385 res = azx_get_response(chip->bus, addr);
1386 chip->probing = 0;
1387 mutex_unlock(&chip->bus->cmd_mutex);
1388 if (res == -1)
1389 return -EIO;
1390 snd_printdd(SFX "codec #%d probed OK\n", addr);
1391 return 0;
1392 }
1393
1394 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1395 struct hda_pcm *cpcm);
1396 static void azx_stop_chip(struct azx *chip);
1397
1398 static void azx_bus_reset(struct hda_bus *bus)
1399 {
1400 struct azx *chip = bus->private_data;
1401
1402 bus->in_reset = 1;
1403 azx_stop_chip(chip);
1404 azx_init_chip(chip, 1);
1405 #ifdef CONFIG_PM
1406 if (chip->initialized) {
1407 int i;
1408
1409 for (i = 0; i < HDA_MAX_PCMS; i++)
1410 snd_pcm_suspend_all(chip->pcm[i]);
1411 snd_hda_suspend(chip->bus);
1412 snd_hda_resume(chip->bus);
1413 }
1414 #endif
1415 bus->in_reset = 0;
1416 }
1417
1418 /*
1419 * Codec initialization
1420 */
1421
1422 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1423 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1424 [AZX_DRIVER_NVIDIA] = 8,
1425 [AZX_DRIVER_TERA] = 1,
1426 };
1427
1428 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1429 {
1430 struct hda_bus_template bus_temp;
1431 int c, codecs, err;
1432 int max_slots;
1433
1434 memset(&bus_temp, 0, sizeof(bus_temp));
1435 bus_temp.private_data = chip;
1436 bus_temp.modelname = model;
1437 bus_temp.pci = chip->pci;
1438 bus_temp.ops.command = azx_send_cmd;
1439 bus_temp.ops.get_response = azx_get_response;
1440 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1441 bus_temp.ops.bus_reset = azx_bus_reset;
1442 #ifdef CONFIG_SND_HDA_POWER_SAVE
1443 bus_temp.power_save = &power_save;
1444 bus_temp.ops.pm_notify = azx_power_notify;
1445 #endif
1446
1447 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1448 if (err < 0)
1449 return err;
1450
1451 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1452 snd_printd(SFX "Enable delay in RIRB handling\n");
1453 chip->bus->needs_damn_long_delay = 1;
1454 }
1455
1456 codecs = 0;
1457 max_slots = azx_max_codecs[chip->driver_type];
1458 if (!max_slots)
1459 max_slots = AZX_DEFAULT_CODECS;
1460
1461 /* First try to probe all given codec slots */
1462 for (c = 0; c < max_slots; c++) {
1463 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1464 if (probe_codec(chip, c) < 0) {
1465 /* Some BIOSen give you wrong codec addresses
1466 * that don't exist
1467 */
1468 snd_printk(KERN_WARNING SFX
1469 "Codec #%d probe error; "
1470 "disabling it...\n", c);
1471 chip->codec_mask &= ~(1 << c);
1472 /* More badly, accessing to a non-existing
1473 * codec often screws up the controller chip,
1474 * and disturbs the further communications.
1475 * Thus if an error occurs during probing,
1476 * better to reset the controller chip to
1477 * get back to the sanity state.
1478 */
1479 azx_stop_chip(chip);
1480 azx_init_chip(chip, 1);
1481 }
1482 }
1483 }
1484
1485 /* AMD chipsets often cause the communication stalls upon certain
1486 * sequence like the pin-detection. It seems that forcing the synced
1487 * access works around the stall. Grrr...
1488 */
1489 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1490 snd_printd(SFX "Enable sync_write for stable communication\n");
1491 chip->bus->sync_write = 1;
1492 chip->bus->allow_bus_reset = 1;
1493 }
1494
1495 /* Then create codec instances */
1496 for (c = 0; c < max_slots; c++) {
1497 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1498 struct hda_codec *codec;
1499 err = snd_hda_codec_new(chip->bus, c, &codec);
1500 if (err < 0)
1501 continue;
1502 codec->beep_mode = chip->beep_mode;
1503 codecs++;
1504 }
1505 }
1506 if (!codecs) {
1507 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1508 return -ENXIO;
1509 }
1510 return 0;
1511 }
1512
1513 /* configure each codec instance */
1514 static int __devinit azx_codec_configure(struct azx *chip)
1515 {
1516 struct hda_codec *codec;
1517 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1518 snd_hda_codec_configure(codec);
1519 }
1520 return 0;
1521 }
1522
1523
1524 /*
1525 * PCM support
1526 */
1527
1528 /* assign a stream for the PCM */
1529 static inline struct azx_dev *
1530 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1531 {
1532 int dev, i, nums;
1533 struct azx_dev *res = NULL;
1534
1535 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1536 dev = chip->playback_index_offset;
1537 nums = chip->playback_streams;
1538 } else {
1539 dev = chip->capture_index_offset;
1540 nums = chip->capture_streams;
1541 }
1542 for (i = 0; i < nums; i++, dev++)
1543 if (!chip->azx_dev[dev].opened) {
1544 res = &chip->azx_dev[dev];
1545 if (res->device == substream->pcm->device)
1546 break;
1547 }
1548 if (res) {
1549 res->opened = 1;
1550 res->device = substream->pcm->device;
1551 }
1552 return res;
1553 }
1554
1555 /* release the assigned stream */
1556 static inline void azx_release_device(struct azx_dev *azx_dev)
1557 {
1558 azx_dev->opened = 0;
1559 }
1560
1561 static struct snd_pcm_hardware azx_pcm_hw = {
1562 .info = (SNDRV_PCM_INFO_MMAP |
1563 SNDRV_PCM_INFO_INTERLEAVED |
1564 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1565 SNDRV_PCM_INFO_MMAP_VALID |
1566 /* No full-resume yet implemented */
1567 /* SNDRV_PCM_INFO_RESUME |*/
1568 SNDRV_PCM_INFO_PAUSE |
1569 SNDRV_PCM_INFO_SYNC_START |
1570 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1571 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1572 .rates = SNDRV_PCM_RATE_48000,
1573 .rate_min = 48000,
1574 .rate_max = 48000,
1575 .channels_min = 2,
1576 .channels_max = 2,
1577 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1578 .period_bytes_min = 128,
1579 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1580 .periods_min = 2,
1581 .periods_max = AZX_MAX_FRAG,
1582 .fifo_size = 0,
1583 };
1584
1585 struct azx_pcm {
1586 struct azx *chip;
1587 struct hda_codec *codec;
1588 struct hda_pcm_stream *hinfo[2];
1589 };
1590
1591 static int azx_pcm_open(struct snd_pcm_substream *substream)
1592 {
1593 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1594 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1595 struct azx *chip = apcm->chip;
1596 struct azx_dev *azx_dev;
1597 struct snd_pcm_runtime *runtime = substream->runtime;
1598 unsigned long flags;
1599 int err;
1600
1601 mutex_lock(&chip->open_mutex);
1602 azx_dev = azx_assign_device(chip, substream);
1603 if (azx_dev == NULL) {
1604 mutex_unlock(&chip->open_mutex);
1605 return -EBUSY;
1606 }
1607 runtime->hw = azx_pcm_hw;
1608 runtime->hw.channels_min = hinfo->channels_min;
1609 runtime->hw.channels_max = hinfo->channels_max;
1610 runtime->hw.formats = hinfo->formats;
1611 runtime->hw.rates = hinfo->rates;
1612 snd_pcm_limit_hw_rates(runtime);
1613 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1614 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1615 128);
1616 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1617 128);
1618 snd_hda_power_up(apcm->codec);
1619 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1620 if (err < 0) {
1621 azx_release_device(azx_dev);
1622 snd_hda_power_down(apcm->codec);
1623 mutex_unlock(&chip->open_mutex);
1624 return err;
1625 }
1626 snd_pcm_limit_hw_rates(runtime);
1627 /* sanity check */
1628 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1629 snd_BUG_ON(!runtime->hw.channels_max) ||
1630 snd_BUG_ON(!runtime->hw.formats) ||
1631 snd_BUG_ON(!runtime->hw.rates)) {
1632 azx_release_device(azx_dev);
1633 hinfo->ops.close(hinfo, apcm->codec, substream);
1634 snd_hda_power_down(apcm->codec);
1635 mutex_unlock(&chip->open_mutex);
1636 return -EINVAL;
1637 }
1638 spin_lock_irqsave(&chip->reg_lock, flags);
1639 azx_dev->substream = substream;
1640 azx_dev->running = 0;
1641 spin_unlock_irqrestore(&chip->reg_lock, flags);
1642
1643 runtime->private_data = azx_dev;
1644 snd_pcm_set_sync(substream);
1645 mutex_unlock(&chip->open_mutex);
1646 return 0;
1647 }
1648
1649 static int azx_pcm_close(struct snd_pcm_substream *substream)
1650 {
1651 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1652 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1653 struct azx *chip = apcm->chip;
1654 struct azx_dev *azx_dev = get_azx_dev(substream);
1655 unsigned long flags;
1656
1657 mutex_lock(&chip->open_mutex);
1658 spin_lock_irqsave(&chip->reg_lock, flags);
1659 azx_dev->substream = NULL;
1660 azx_dev->running = 0;
1661 spin_unlock_irqrestore(&chip->reg_lock, flags);
1662 azx_release_device(azx_dev);
1663 hinfo->ops.close(hinfo, apcm->codec, substream);
1664 snd_hda_power_down(apcm->codec);
1665 mutex_unlock(&chip->open_mutex);
1666 return 0;
1667 }
1668
1669 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1670 struct snd_pcm_hw_params *hw_params)
1671 {
1672 struct azx_dev *azx_dev = get_azx_dev(substream);
1673
1674 azx_dev->bufsize = 0;
1675 azx_dev->period_bytes = 0;
1676 azx_dev->format_val = 0;
1677 return snd_pcm_lib_malloc_pages(substream,
1678 params_buffer_bytes(hw_params));
1679 }
1680
1681 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1682 {
1683 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1684 struct azx_dev *azx_dev = get_azx_dev(substream);
1685 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1686
1687 /* reset BDL address */
1688 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1689 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1690 azx_sd_writel(azx_dev, SD_CTL, 0);
1691 azx_dev->bufsize = 0;
1692 azx_dev->period_bytes = 0;
1693 azx_dev->format_val = 0;
1694
1695 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1696
1697 return snd_pcm_lib_free_pages(substream);
1698 }
1699
1700 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1701 {
1702 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1703 struct azx *chip = apcm->chip;
1704 struct azx_dev *azx_dev = get_azx_dev(substream);
1705 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1706 struct snd_pcm_runtime *runtime = substream->runtime;
1707 unsigned int bufsize, period_bytes, format_val, stream_tag;
1708 int err;
1709
1710 azx_stream_reset(chip, azx_dev);
1711 format_val = snd_hda_calc_stream_format(runtime->rate,
1712 runtime->channels,
1713 runtime->format,
1714 hinfo->maxbps,
1715 apcm->codec->spdif_ctls);
1716 if (!format_val) {
1717 snd_printk(KERN_ERR SFX
1718 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1719 runtime->rate, runtime->channels, runtime->format);
1720 return -EINVAL;
1721 }
1722
1723 bufsize = snd_pcm_lib_buffer_bytes(substream);
1724 period_bytes = snd_pcm_lib_period_bytes(substream);
1725
1726 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1727 bufsize, format_val);
1728
1729 if (bufsize != azx_dev->bufsize ||
1730 period_bytes != azx_dev->period_bytes ||
1731 format_val != azx_dev->format_val) {
1732 azx_dev->bufsize = bufsize;
1733 azx_dev->period_bytes = period_bytes;
1734 azx_dev->format_val = format_val;
1735 err = azx_setup_periods(chip, substream, azx_dev);
1736 if (err < 0)
1737 return err;
1738 }
1739
1740 /* wallclk has 24Mhz clock source */
1741 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1742 runtime->rate) * 1000);
1743 azx_setup_controller(chip, azx_dev);
1744 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1745 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1746 else
1747 azx_dev->fifo_size = 0;
1748
1749 stream_tag = azx_dev->stream_tag;
1750 /* CA-IBG chips need the playback stream starting from 1 */
1751 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1752 stream_tag > chip->capture_streams)
1753 stream_tag -= chip->capture_streams;
1754 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1755 azx_dev->format_val, substream);
1756 }
1757
1758 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1759 {
1760 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1761 struct azx *chip = apcm->chip;
1762 struct azx_dev *azx_dev;
1763 struct snd_pcm_substream *s;
1764 int rstart = 0, start, nsync = 0, sbits = 0;
1765 int nwait, timeout;
1766
1767 switch (cmd) {
1768 case SNDRV_PCM_TRIGGER_START:
1769 rstart = 1;
1770 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1771 case SNDRV_PCM_TRIGGER_RESUME:
1772 start = 1;
1773 break;
1774 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1775 case SNDRV_PCM_TRIGGER_SUSPEND:
1776 case SNDRV_PCM_TRIGGER_STOP:
1777 start = 0;
1778 break;
1779 default:
1780 return -EINVAL;
1781 }
1782
1783 snd_pcm_group_for_each_entry(s, substream) {
1784 if (s->pcm->card != substream->pcm->card)
1785 continue;
1786 azx_dev = get_azx_dev(s);
1787 sbits |= 1 << azx_dev->index;
1788 nsync++;
1789 snd_pcm_trigger_done(s, substream);
1790 }
1791
1792 spin_lock(&chip->reg_lock);
1793 if (nsync > 1) {
1794 /* first, set SYNC bits of corresponding streams */
1795 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1796 }
1797 snd_pcm_group_for_each_entry(s, substream) {
1798 if (s->pcm->card != substream->pcm->card)
1799 continue;
1800 azx_dev = get_azx_dev(s);
1801 if (start) {
1802 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1803 if (!rstart)
1804 azx_dev->start_wallclk -=
1805 azx_dev->period_wallclk;
1806 azx_stream_start(chip, azx_dev);
1807 } else {
1808 azx_stream_stop(chip, azx_dev);
1809 }
1810 azx_dev->running = start;
1811 }
1812 spin_unlock(&chip->reg_lock);
1813 if (start) {
1814 if (nsync == 1)
1815 return 0;
1816 /* wait until all FIFOs get ready */
1817 for (timeout = 5000; timeout; timeout--) {
1818 nwait = 0;
1819 snd_pcm_group_for_each_entry(s, substream) {
1820 if (s->pcm->card != substream->pcm->card)
1821 continue;
1822 azx_dev = get_azx_dev(s);
1823 if (!(azx_sd_readb(azx_dev, SD_STS) &
1824 SD_STS_FIFO_READY))
1825 nwait++;
1826 }
1827 if (!nwait)
1828 break;
1829 cpu_relax();
1830 }
1831 } else {
1832 /* wait until all RUN bits are cleared */
1833 for (timeout = 5000; timeout; timeout--) {
1834 nwait = 0;
1835 snd_pcm_group_for_each_entry(s, substream) {
1836 if (s->pcm->card != substream->pcm->card)
1837 continue;
1838 azx_dev = get_azx_dev(s);
1839 if (azx_sd_readb(azx_dev, SD_CTL) &
1840 SD_CTL_DMA_START)
1841 nwait++;
1842 }
1843 if (!nwait)
1844 break;
1845 cpu_relax();
1846 }
1847 }
1848 if (nsync > 1) {
1849 spin_lock(&chip->reg_lock);
1850 /* reset SYNC bits */
1851 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1852 spin_unlock(&chip->reg_lock);
1853 }
1854 return 0;
1855 }
1856
1857 /* get the current DMA position with correction on VIA chips */
1858 static unsigned int azx_via_get_position(struct azx *chip,
1859 struct azx_dev *azx_dev)
1860 {
1861 unsigned int link_pos, mini_pos, bound_pos;
1862 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1863 unsigned int fifo_size;
1864
1865 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1866 if (azx_dev->index >= 4) {
1867 /* Playback, no problem using link position */
1868 return link_pos;
1869 }
1870
1871 /* Capture */
1872 /* For new chipset,
1873 * use mod to get the DMA position just like old chipset
1874 */
1875 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1876 mod_dma_pos %= azx_dev->period_bytes;
1877
1878 /* azx_dev->fifo_size can't get FIFO size of in stream.
1879 * Get from base address + offset.
1880 */
1881 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1882
1883 if (azx_dev->insufficient) {
1884 /* Link position never gather than FIFO size */
1885 if (link_pos <= fifo_size)
1886 return 0;
1887
1888 azx_dev->insufficient = 0;
1889 }
1890
1891 if (link_pos <= fifo_size)
1892 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1893 else
1894 mini_pos = link_pos - fifo_size;
1895
1896 /* Find nearest previous boudary */
1897 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1898 mod_link_pos = link_pos % azx_dev->period_bytes;
1899 if (mod_link_pos >= fifo_size)
1900 bound_pos = link_pos - mod_link_pos;
1901 else if (mod_dma_pos >= mod_mini_pos)
1902 bound_pos = mini_pos - mod_mini_pos;
1903 else {
1904 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1905 if (bound_pos >= azx_dev->bufsize)
1906 bound_pos = 0;
1907 }
1908
1909 /* Calculate real DMA position we want */
1910 return bound_pos + mod_dma_pos;
1911 }
1912
1913 static unsigned int azx_get_position(struct azx *chip,
1914 struct azx_dev *azx_dev)
1915 {
1916 unsigned int pos;
1917 int stream = azx_dev->substream->stream;
1918
1919 switch (chip->position_fix[stream]) {
1920 case POS_FIX_LPIB:
1921 /* read LPIB */
1922 pos = azx_sd_readl(azx_dev, SD_LPIB);
1923 break;
1924 case POS_FIX_VIACOMBO:
1925 pos = azx_via_get_position(chip, azx_dev);
1926 break;
1927 default:
1928 /* use the position buffer */
1929 pos = le32_to_cpu(*azx_dev->posbuf);
1930 }
1931
1932 if (pos >= azx_dev->bufsize)
1933 pos = 0;
1934 return pos;
1935 }
1936
1937 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1938 {
1939 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1940 struct azx *chip = apcm->chip;
1941 struct azx_dev *azx_dev = get_azx_dev(substream);
1942 return bytes_to_frames(substream->runtime,
1943 azx_get_position(chip, azx_dev));
1944 }
1945
1946 /*
1947 * Check whether the current DMA position is acceptable for updating
1948 * periods. Returns non-zero if it's OK.
1949 *
1950 * Many HD-audio controllers appear pretty inaccurate about
1951 * the update-IRQ timing. The IRQ is issued before actually the
1952 * data is processed. So, we need to process it afterwords in a
1953 * workqueue.
1954 */
1955 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1956 {
1957 u32 wallclk;
1958 unsigned int pos;
1959 int stream;
1960
1961 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1962 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1963 return -1; /* bogus (too early) interrupt */
1964
1965 stream = azx_dev->substream->stream;
1966 pos = azx_get_position(chip, azx_dev);
1967 if (chip->position_fix[stream] == POS_FIX_AUTO) {
1968 if (!pos) {
1969 printk(KERN_WARNING
1970 "hda-intel: Invalid position buffer, "
1971 "using LPIB read method instead.\n");
1972 chip->position_fix[stream] = POS_FIX_LPIB;
1973 pos = azx_get_position(chip, azx_dev);
1974 } else
1975 chip->position_fix[stream] = POS_FIX_POSBUF;
1976 }
1977
1978 if (WARN_ONCE(!azx_dev->period_bytes,
1979 "hda-intel: zero azx_dev->period_bytes"))
1980 return -1; /* this shouldn't happen! */
1981 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1982 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1983 /* NG - it's below the first next period boundary */
1984 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
1985 azx_dev->start_wallclk += wallclk;
1986 return 1; /* OK, it's fine */
1987 }
1988
1989 /*
1990 * The work for pending PCM period updates.
1991 */
1992 static void azx_irq_pending_work(struct work_struct *work)
1993 {
1994 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1995 int i, pending, ok;
1996
1997 if (!chip->irq_pending_warned) {
1998 printk(KERN_WARNING
1999 "hda-intel: IRQ timing workaround is activated "
2000 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2001 chip->card->number);
2002 chip->irq_pending_warned = 1;
2003 }
2004
2005 for (;;) {
2006 pending = 0;
2007 spin_lock_irq(&chip->reg_lock);
2008 for (i = 0; i < chip->num_streams; i++) {
2009 struct azx_dev *azx_dev = &chip->azx_dev[i];
2010 if (!azx_dev->irq_pending ||
2011 !azx_dev->substream ||
2012 !azx_dev->running)
2013 continue;
2014 ok = azx_position_ok(chip, azx_dev);
2015 if (ok > 0) {
2016 azx_dev->irq_pending = 0;
2017 spin_unlock(&chip->reg_lock);
2018 snd_pcm_period_elapsed(azx_dev->substream);
2019 spin_lock(&chip->reg_lock);
2020 } else if (ok < 0) {
2021 pending = 0; /* too early */
2022 } else
2023 pending++;
2024 }
2025 spin_unlock_irq(&chip->reg_lock);
2026 if (!pending)
2027 return;
2028 msleep(1);
2029 }
2030 }
2031
2032 /* clear irq_pending flags and assure no on-going workq */
2033 static void azx_clear_irq_pending(struct azx *chip)
2034 {
2035 int i;
2036
2037 spin_lock_irq(&chip->reg_lock);
2038 for (i = 0; i < chip->num_streams; i++)
2039 chip->azx_dev[i].irq_pending = 0;
2040 spin_unlock_irq(&chip->reg_lock);
2041 }
2042
2043 static struct snd_pcm_ops azx_pcm_ops = {
2044 .open = azx_pcm_open,
2045 .close = azx_pcm_close,
2046 .ioctl = snd_pcm_lib_ioctl,
2047 .hw_params = azx_pcm_hw_params,
2048 .hw_free = azx_pcm_hw_free,
2049 .prepare = azx_pcm_prepare,
2050 .trigger = azx_pcm_trigger,
2051 .pointer = azx_pcm_pointer,
2052 .page = snd_pcm_sgbuf_ops_page,
2053 };
2054
2055 static void azx_pcm_free(struct snd_pcm *pcm)
2056 {
2057 struct azx_pcm *apcm = pcm->private_data;
2058 if (apcm) {
2059 apcm->chip->pcm[pcm->device] = NULL;
2060 kfree(apcm);
2061 }
2062 }
2063
2064 static int
2065 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2066 struct hda_pcm *cpcm)
2067 {
2068 struct azx *chip = bus->private_data;
2069 struct snd_pcm *pcm;
2070 struct azx_pcm *apcm;
2071 int pcm_dev = cpcm->device;
2072 int s, err;
2073
2074 if (pcm_dev >= HDA_MAX_PCMS) {
2075 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2076 pcm_dev);
2077 return -EINVAL;
2078 }
2079 if (chip->pcm[pcm_dev]) {
2080 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2081 return -EBUSY;
2082 }
2083 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2084 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2085 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2086 &pcm);
2087 if (err < 0)
2088 return err;
2089 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2090 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2091 if (apcm == NULL)
2092 return -ENOMEM;
2093 apcm->chip = chip;
2094 apcm->codec = codec;
2095 pcm->private_data = apcm;
2096 pcm->private_free = azx_pcm_free;
2097 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2098 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2099 chip->pcm[pcm_dev] = pcm;
2100 cpcm->pcm = pcm;
2101 for (s = 0; s < 2; s++) {
2102 apcm->hinfo[s] = &cpcm->stream[s];
2103 if (cpcm->stream[s].substreams)
2104 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2105 }
2106 /* buffer pre-allocation */
2107 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2108 snd_dma_pci_data(chip->pci),
2109 1024 * 64, 32 * 1024 * 1024);
2110 return 0;
2111 }
2112
2113 /*
2114 * mixer creation - all stuff is implemented in hda module
2115 */
2116 static int __devinit azx_mixer_create(struct azx *chip)
2117 {
2118 return snd_hda_build_controls(chip->bus);
2119 }
2120
2121
2122 /*
2123 * initialize SD streams
2124 */
2125 static int __devinit azx_init_stream(struct azx *chip)
2126 {
2127 int i;
2128
2129 /* initialize each stream (aka device)
2130 * assign the starting bdl address to each stream (device)
2131 * and initialize
2132 */
2133 for (i = 0; i < chip->num_streams; i++) {
2134 struct azx_dev *azx_dev = &chip->azx_dev[i];
2135 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2136 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2137 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2138 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2139 azx_dev->sd_int_sta_mask = 1 << i;
2140 /* stream tag: must be non-zero and unique */
2141 azx_dev->index = i;
2142 azx_dev->stream_tag = i + 1;
2143 }
2144
2145 return 0;
2146 }
2147
2148 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2149 {
2150 if (request_irq(chip->pci->irq, azx_interrupt,
2151 chip->msi ? 0 : IRQF_SHARED,
2152 "hda_intel", chip)) {
2153 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2154 "disabling device\n", chip->pci->irq);
2155 if (do_disconnect)
2156 snd_card_disconnect(chip->card);
2157 return -1;
2158 }
2159 chip->irq = chip->pci->irq;
2160 pci_intx(chip->pci, !chip->msi);
2161 return 0;
2162 }
2163
2164
2165 static void azx_stop_chip(struct azx *chip)
2166 {
2167 if (!chip->initialized)
2168 return;
2169
2170 /* disable interrupts */
2171 azx_int_disable(chip);
2172 azx_int_clear(chip);
2173
2174 /* disable CORB/RIRB */
2175 azx_free_cmd_io(chip);
2176
2177 /* disable position buffer */
2178 azx_writel(chip, DPLBASE, 0);
2179 azx_writel(chip, DPUBASE, 0);
2180
2181 chip->initialized = 0;
2182 }
2183
2184 #ifdef CONFIG_SND_HDA_POWER_SAVE
2185 /* power-up/down the controller */
2186 static void azx_power_notify(struct hda_bus *bus)
2187 {
2188 struct azx *chip = bus->private_data;
2189 struct hda_codec *c;
2190 int power_on = 0;
2191
2192 list_for_each_entry(c, &bus->codec_list, list) {
2193 if (c->power_on) {
2194 power_on = 1;
2195 break;
2196 }
2197 }
2198 if (power_on)
2199 azx_init_chip(chip, 1);
2200 else if (chip->running && power_save_controller &&
2201 !bus->power_keep_link_on)
2202 azx_stop_chip(chip);
2203 }
2204 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2205
2206 #ifdef CONFIG_PM
2207 /*
2208 * power management
2209 */
2210
2211 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2212 {
2213 struct hda_codec *codec;
2214
2215 list_for_each_entry(codec, &bus->codec_list, list) {
2216 if (snd_hda_codec_needs_resume(codec))
2217 return 1;
2218 }
2219 return 0;
2220 }
2221
2222 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2223 {
2224 struct snd_card *card = pci_get_drvdata(pci);
2225 struct azx *chip = card->private_data;
2226 int i;
2227
2228 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2229 azx_clear_irq_pending(chip);
2230 for (i = 0; i < HDA_MAX_PCMS; i++)
2231 snd_pcm_suspend_all(chip->pcm[i]);
2232 if (chip->initialized)
2233 snd_hda_suspend(chip->bus);
2234 azx_stop_chip(chip);
2235 if (chip->irq >= 0) {
2236 free_irq(chip->irq, chip);
2237 chip->irq = -1;
2238 }
2239 if (chip->msi)
2240 pci_disable_msi(chip->pci);
2241 pci_disable_device(pci);
2242 pci_save_state(pci);
2243 pci_set_power_state(pci, pci_choose_state(pci, state));
2244 return 0;
2245 }
2246
2247 static int azx_resume(struct pci_dev *pci)
2248 {
2249 struct snd_card *card = pci_get_drvdata(pci);
2250 struct azx *chip = card->private_data;
2251
2252 pci_set_power_state(pci, PCI_D0);
2253 pci_restore_state(pci);
2254 if (pci_enable_device(pci) < 0) {
2255 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2256 "disabling device\n");
2257 snd_card_disconnect(card);
2258 return -EIO;
2259 }
2260 pci_set_master(pci);
2261 if (chip->msi)
2262 if (pci_enable_msi(pci) < 0)
2263 chip->msi = 0;
2264 if (azx_acquire_irq(chip, 1) < 0)
2265 return -EIO;
2266 azx_init_pci(chip);
2267
2268 if (snd_hda_codecs_inuse(chip->bus))
2269 azx_init_chip(chip, 1);
2270
2271 snd_hda_resume(chip->bus);
2272 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2273 return 0;
2274 }
2275 #endif /* CONFIG_PM */
2276
2277
2278 /*
2279 * reboot notifier for hang-up problem at power-down
2280 */
2281 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2282 {
2283 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2284 snd_hda_bus_reboot_notify(chip->bus);
2285 azx_stop_chip(chip);
2286 return NOTIFY_OK;
2287 }
2288
2289 static void azx_notifier_register(struct azx *chip)
2290 {
2291 chip->reboot_notifier.notifier_call = azx_halt;
2292 register_reboot_notifier(&chip->reboot_notifier);
2293 }
2294
2295 static void azx_notifier_unregister(struct azx *chip)
2296 {
2297 if (chip->reboot_notifier.notifier_call)
2298 unregister_reboot_notifier(&chip->reboot_notifier);
2299 }
2300
2301 /*
2302 * destructor
2303 */
2304 static int azx_free(struct azx *chip)
2305 {
2306 int i;
2307
2308 azx_notifier_unregister(chip);
2309
2310 if (chip->initialized) {
2311 azx_clear_irq_pending(chip);
2312 for (i = 0; i < chip->num_streams; i++)
2313 azx_stream_stop(chip, &chip->azx_dev[i]);
2314 azx_stop_chip(chip);
2315 }
2316
2317 if (chip->irq >= 0)
2318 free_irq(chip->irq, (void*)chip);
2319 if (chip->msi)
2320 pci_disable_msi(chip->pci);
2321 if (chip->remap_addr)
2322 iounmap(chip->remap_addr);
2323
2324 if (chip->azx_dev) {
2325 for (i = 0; i < chip->num_streams; i++)
2326 if (chip->azx_dev[i].bdl.area)
2327 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2328 }
2329 if (chip->rb.area)
2330 snd_dma_free_pages(&chip->rb);
2331 if (chip->posbuf.area)
2332 snd_dma_free_pages(&chip->posbuf);
2333 pci_release_regions(chip->pci);
2334 pci_disable_device(chip->pci);
2335 kfree(chip->azx_dev);
2336 kfree(chip);
2337
2338 return 0;
2339 }
2340
2341 static int azx_dev_free(struct snd_device *device)
2342 {
2343 return azx_free(device->device_data);
2344 }
2345
2346 /*
2347 * white/black-listing for position_fix
2348 */
2349 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2350 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB),
2351 SND_PCI_QUIRK(0x1025, 0x026f, "Acer Aspire 5538", POS_FIX_LPIB),
2352 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2353 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2354 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2355 SND_PCI_QUIRK(0x1028, 0x0470, "Dell Inspiron 1120", POS_FIX_LPIB),
2356 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2357 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2358 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2359 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2360 SND_PCI_QUIRK(0x1043, 0x8410, "ASUS", POS_FIX_LPIB),
2361 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2362 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2363 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2364 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2365 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2366 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2367 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2368 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2369 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2370 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2371 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2372 {}
2373 };
2374
2375 static int __devinit check_position_fix(struct azx *chip, int fix)
2376 {
2377 const struct snd_pci_quirk *q;
2378
2379 switch (fix) {
2380 case POS_FIX_LPIB:
2381 case POS_FIX_POSBUF:
2382 case POS_FIX_VIACOMBO:
2383 return fix;
2384 }
2385
2386 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2387 if (q) {
2388 printk(KERN_INFO
2389 "hda_intel: position_fix set to %d "
2390 "for device %04x:%04x\n",
2391 q->value, q->subvendor, q->subdevice);
2392 return q->value;
2393 }
2394
2395 /* Check VIA/ATI HD Audio Controller exist */
2396 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2397 snd_printd(SFX "Using VIACOMBO position fix\n");
2398 return POS_FIX_VIACOMBO;
2399 }
2400 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2401 snd_printd(SFX "Using LPIB position fix\n");
2402 return POS_FIX_LPIB;
2403 }
2404 return POS_FIX_AUTO;
2405 }
2406
2407 /*
2408 * black-lists for probe_mask
2409 */
2410 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2411 /* Thinkpad often breaks the controller communication when accessing
2412 * to the non-working (or non-existing) modem codec slot.
2413 */
2414 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2415 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2416 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2417 /* broken BIOS */
2418 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2419 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2420 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2421 /* forced codec slots */
2422 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2423 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2424 {}
2425 };
2426
2427 #define AZX_FORCE_CODEC_MASK 0x100
2428
2429 static void __devinit check_probe_mask(struct azx *chip, int dev)
2430 {
2431 const struct snd_pci_quirk *q;
2432
2433 chip->codec_probe_mask = probe_mask[dev];
2434 if (chip->codec_probe_mask == -1) {
2435 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2436 if (q) {
2437 printk(KERN_INFO
2438 "hda_intel: probe_mask set to 0x%x "
2439 "for device %04x:%04x\n",
2440 q->value, q->subvendor, q->subdevice);
2441 chip->codec_probe_mask = q->value;
2442 }
2443 }
2444
2445 /* check forced option */
2446 if (chip->codec_probe_mask != -1 &&
2447 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2448 chip->codec_mask = chip->codec_probe_mask & 0xff;
2449 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2450 chip->codec_mask);
2451 }
2452 }
2453
2454 /*
2455 * white/black-list for enable_msi
2456 */
2457 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2458 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2459 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2460 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2461 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2462 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2463 {}
2464 };
2465
2466 static void __devinit check_msi(struct azx *chip)
2467 {
2468 const struct snd_pci_quirk *q;
2469
2470 if (enable_msi >= 0) {
2471 chip->msi = !!enable_msi;
2472 return;
2473 }
2474 chip->msi = 1; /* enable MSI as default */
2475 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2476 if (q) {
2477 printk(KERN_INFO
2478 "hda_intel: msi for device %04x:%04x set to %d\n",
2479 q->subvendor, q->subdevice, q->value);
2480 chip->msi = q->value;
2481 return;
2482 }
2483
2484 /* NVidia chipsets seem to cause troubles with MSI */
2485 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2486 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2487 chip->msi = 0;
2488 }
2489 }
2490
2491
2492 /*
2493 * constructor
2494 */
2495 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2496 int dev, unsigned int driver_caps,
2497 struct azx **rchip)
2498 {
2499 struct azx *chip;
2500 int i, err;
2501 unsigned short gcap;
2502 static struct snd_device_ops ops = {
2503 .dev_free = azx_dev_free,
2504 };
2505
2506 *rchip = NULL;
2507
2508 err = pci_enable_device(pci);
2509 if (err < 0)
2510 return err;
2511
2512 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2513 if (!chip) {
2514 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2515 pci_disable_device(pci);
2516 return -ENOMEM;
2517 }
2518
2519 spin_lock_init(&chip->reg_lock);
2520 mutex_init(&chip->open_mutex);
2521 chip->card = card;
2522 chip->pci = pci;
2523 chip->irq = -1;
2524 chip->driver_caps = driver_caps;
2525 chip->driver_type = driver_caps & 0xff;
2526 check_msi(chip);
2527 chip->dev_index = dev;
2528 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2529
2530 chip->position_fix[0] = chip->position_fix[1] =
2531 check_position_fix(chip, position_fix[dev]);
2532 check_probe_mask(chip, dev);
2533
2534 chip->single_cmd = single_cmd;
2535
2536 if (bdl_pos_adj[dev] < 0) {
2537 switch (chip->driver_type) {
2538 case AZX_DRIVER_ICH:
2539 case AZX_DRIVER_PCH:
2540 bdl_pos_adj[dev] = 1;
2541 break;
2542 default:
2543 bdl_pos_adj[dev] = 32;
2544 break;
2545 }
2546 }
2547
2548 #if BITS_PER_LONG != 64
2549 /* Fix up base address on ULI M5461 */
2550 if (chip->driver_type == AZX_DRIVER_ULI) {
2551 u16 tmp3;
2552 pci_read_config_word(pci, 0x40, &tmp3);
2553 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2554 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2555 }
2556 #endif
2557
2558 err = pci_request_regions(pci, "ICH HD audio");
2559 if (err < 0) {
2560 kfree(chip);
2561 pci_disable_device(pci);
2562 return err;
2563 }
2564
2565 chip->addr = pci_resource_start(pci, 0);
2566 chip->remap_addr = pci_ioremap_bar(pci, 0);
2567 if (chip->remap_addr == NULL) {
2568 snd_printk(KERN_ERR SFX "ioremap error\n");
2569 err = -ENXIO;
2570 goto errout;
2571 }
2572
2573 if (chip->msi)
2574 if (pci_enable_msi(pci) < 0)
2575 chip->msi = 0;
2576
2577 if (azx_acquire_irq(chip, 0) < 0) {
2578 err = -EBUSY;
2579 goto errout;
2580 }
2581
2582 pci_set_master(pci);
2583 synchronize_irq(chip->irq);
2584
2585 gcap = azx_readw(chip, GCAP);
2586 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2587
2588 /* disable SB600 64bit support for safety */
2589 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2590 struct pci_dev *p_smbus;
2591 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2592 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2593 NULL);
2594 if (p_smbus) {
2595 if (p_smbus->revision < 0x30)
2596 gcap &= ~ICH6_GCAP_64OK;
2597 pci_dev_put(p_smbus);
2598 }
2599 }
2600
2601 /* disable 64bit DMA address on some devices */
2602 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2603 snd_printd(SFX "Disabling 64bit DMA\n");
2604 gcap &= ~ICH6_GCAP_64OK;
2605 }
2606
2607 /* allow 64bit DMA address if supported by H/W */
2608 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2609 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2610 else {
2611 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2612 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2613 }
2614
2615 /* read number of streams from GCAP register instead of using
2616 * hardcoded value
2617 */
2618 chip->capture_streams = (gcap >> 8) & 0x0f;
2619 chip->playback_streams = (gcap >> 12) & 0x0f;
2620 if (!chip->playback_streams && !chip->capture_streams) {
2621 /* gcap didn't give any info, switching to old method */
2622
2623 switch (chip->driver_type) {
2624 case AZX_DRIVER_ULI:
2625 chip->playback_streams = ULI_NUM_PLAYBACK;
2626 chip->capture_streams = ULI_NUM_CAPTURE;
2627 break;
2628 case AZX_DRIVER_ATIHDMI:
2629 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2630 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2631 break;
2632 case AZX_DRIVER_GENERIC:
2633 default:
2634 chip->playback_streams = ICH6_NUM_PLAYBACK;
2635 chip->capture_streams = ICH6_NUM_CAPTURE;
2636 break;
2637 }
2638 }
2639 chip->capture_index_offset = 0;
2640 chip->playback_index_offset = chip->capture_streams;
2641 chip->num_streams = chip->playback_streams + chip->capture_streams;
2642 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2643 GFP_KERNEL);
2644 if (!chip->azx_dev) {
2645 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2646 goto errout;
2647 }
2648
2649 for (i = 0; i < chip->num_streams; i++) {
2650 /* allocate memory for the BDL for each stream */
2651 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2652 snd_dma_pci_data(chip->pci),
2653 BDL_SIZE, &chip->azx_dev[i].bdl);
2654 if (err < 0) {
2655 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2656 goto errout;
2657 }
2658 }
2659 /* allocate memory for the position buffer */
2660 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2661 snd_dma_pci_data(chip->pci),
2662 chip->num_streams * 8, &chip->posbuf);
2663 if (err < 0) {
2664 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2665 goto errout;
2666 }
2667 /* allocate CORB/RIRB */
2668 err = azx_alloc_cmd_io(chip);
2669 if (err < 0)
2670 goto errout;
2671
2672 /* initialize streams */
2673 azx_init_stream(chip);
2674
2675 /* initialize chip */
2676 azx_init_pci(chip);
2677 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2678
2679 /* codec detection */
2680 if (!chip->codec_mask) {
2681 snd_printk(KERN_ERR SFX "no codecs found!\n");
2682 err = -ENODEV;
2683 goto errout;
2684 }
2685
2686 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2687 if (err <0) {
2688 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2689 goto errout;
2690 }
2691
2692 strcpy(card->driver, "HDA-Intel");
2693 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2694 sizeof(card->shortname));
2695 snprintf(card->longname, sizeof(card->longname),
2696 "%s at 0x%lx irq %i",
2697 card->shortname, chip->addr, chip->irq);
2698
2699 *rchip = chip;
2700 return 0;
2701
2702 errout:
2703 azx_free(chip);
2704 return err;
2705 }
2706
2707 static void power_down_all_codecs(struct azx *chip)
2708 {
2709 #ifdef CONFIG_SND_HDA_POWER_SAVE
2710 /* The codecs were powered up in snd_hda_codec_new().
2711 * Now all initialization done, so turn them down if possible
2712 */
2713 struct hda_codec *codec;
2714 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2715 snd_hda_power_down(codec);
2716 }
2717 #endif
2718 }
2719
2720 static int __devinit azx_probe(struct pci_dev *pci,
2721 const struct pci_device_id *pci_id)
2722 {
2723 static int dev;
2724 struct snd_card *card;
2725 struct azx *chip;
2726 int err;
2727
2728 if (dev >= SNDRV_CARDS)
2729 return -ENODEV;
2730 if (!enable[dev]) {
2731 dev++;
2732 return -ENOENT;
2733 }
2734
2735 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2736 if (err < 0) {
2737 snd_printk(KERN_ERR SFX "Error creating card!\n");
2738 return err;
2739 }
2740
2741 /* set this here since it's referred in snd_hda_load_patch() */
2742 snd_card_set_dev(card, &pci->dev);
2743
2744 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2745 if (err < 0)
2746 goto out_free;
2747 card->private_data = chip;
2748
2749 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2750 chip->beep_mode = beep_mode[dev];
2751 #endif
2752
2753 /* create codec instances */
2754 err = azx_codec_create(chip, model[dev]);
2755 if (err < 0)
2756 goto out_free;
2757 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2758 if (patch[dev] && *patch[dev]) {
2759 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2760 patch[dev]);
2761 err = snd_hda_load_patch(chip->bus, patch[dev]);
2762 if (err < 0)
2763 goto out_free;
2764 }
2765 #endif
2766 if ((probe_only[dev] & 1) == 0) {
2767 err = azx_codec_configure(chip);
2768 if (err < 0)
2769 goto out_free;
2770 }
2771
2772 /* create PCM streams */
2773 err = snd_hda_build_pcms(chip->bus);
2774 if (err < 0)
2775 goto out_free;
2776
2777 /* create mixer controls */
2778 err = azx_mixer_create(chip);
2779 if (err < 0)
2780 goto out_free;
2781
2782 err = snd_card_register(card);
2783 if (err < 0)
2784 goto out_free;
2785
2786 pci_set_drvdata(pci, card);
2787 chip->running = 1;
2788 power_down_all_codecs(chip);
2789 azx_notifier_register(chip);
2790
2791 dev++;
2792 return err;
2793 out_free:
2794 snd_card_free(card);
2795 return err;
2796 }
2797
2798 static void __devexit azx_remove(struct pci_dev *pci)
2799 {
2800 snd_card_free(pci_get_drvdata(pci));
2801 pci_set_drvdata(pci, NULL);
2802 }
2803
2804 /* PCI IDs */
2805 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2806 /* CPT */
2807 { PCI_DEVICE(0x8086, 0x1c20),
2808 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2809 /* PBG */
2810 { PCI_DEVICE(0x8086, 0x1d20),
2811 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2812 /* Panther Point */
2813 { PCI_DEVICE(0x8086, 0x1e20),
2814 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
2815 /* SCH */
2816 { PCI_DEVICE(0x8086, 0x811b),
2817 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP },
2818 /* Generic Intel */
2819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2820 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2821 .class_mask = 0xffffff,
2822 .driver_data = AZX_DRIVER_ICH },
2823 /* ATI SB 450/600/700/800/900 */
2824 { PCI_DEVICE(0x1002, 0x437b),
2825 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2826 { PCI_DEVICE(0x1002, 0x4383),
2827 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2828 /* AMD Hudson */
2829 { PCI_DEVICE(0x1022, 0x780d),
2830 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2831 /* ATI HDMI */
2832 { PCI_DEVICE(0x1002, 0x793b),
2833 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2834 { PCI_DEVICE(0x1002, 0x7919),
2835 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2836 { PCI_DEVICE(0x1002, 0x960f),
2837 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2838 { PCI_DEVICE(0x1002, 0x970f),
2839 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2840 { PCI_DEVICE(0x1002, 0xaa00),
2841 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2842 { PCI_DEVICE(0x1002, 0xaa08),
2843 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2844 { PCI_DEVICE(0x1002, 0xaa10),
2845 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2846 { PCI_DEVICE(0x1002, 0xaa18),
2847 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2848 { PCI_DEVICE(0x1002, 0xaa20),
2849 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2850 { PCI_DEVICE(0x1002, 0xaa28),
2851 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2852 { PCI_DEVICE(0x1002, 0xaa30),
2853 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2854 { PCI_DEVICE(0x1002, 0xaa38),
2855 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2856 { PCI_DEVICE(0x1002, 0xaa40),
2857 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2858 { PCI_DEVICE(0x1002, 0xaa48),
2859 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2860 /* VIA VT8251/VT8237A */
2861 { PCI_DEVICE(0x1106, 0x3288),
2862 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2863 /* SIS966 */
2864 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2865 /* ULI M5461 */
2866 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2867 /* NVIDIA MCP */
2868 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2869 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2870 .class_mask = 0xffffff,
2871 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2872 /* Teradici */
2873 { PCI_DEVICE(0x6549, 0x1200),
2874 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2875 /* Creative X-Fi (CA0110-IBG) */
2876 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2877 /* the following entry conflicts with snd-ctxfi driver,
2878 * as ctxfi driver mutates from HD-audio to native mode with
2879 * a special command sequence.
2880 */
2881 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2882 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2883 .class_mask = 0xffffff,
2884 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2885 AZX_DCAPS_RIRB_PRE_DELAY },
2886 #else
2887 /* this entry seems still valid -- i.e. without emu20kx chip */
2888 { PCI_DEVICE(0x1102, 0x0009),
2889 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2890 AZX_DCAPS_RIRB_PRE_DELAY },
2891 #endif
2892 /* Vortex86MX */
2893 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2894 /* VMware HDAudio */
2895 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2896 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2897 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2898 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2899 .class_mask = 0xffffff,
2900 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2901 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2902 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2903 .class_mask = 0xffffff,
2904 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2905 { 0, }
2906 };
2907 MODULE_DEVICE_TABLE(pci, azx_ids);
2908
2909 /* pci_driver definition */
2910 static struct pci_driver driver = {
2911 .name = "HDA Intel",
2912 .id_table = azx_ids,
2913 .probe = azx_probe,
2914 .remove = __devexit_p(azx_remove),
2915 #ifdef CONFIG_PM
2916 .suspend = azx_suspend,
2917 .resume = azx_resume,
2918 #endif
2919 };
2920
2921 static int __init alsa_card_azx_init(void)
2922 {
2923 return pci_register_driver(&driver);
2924 }
2925
2926 static void __exit alsa_card_azx_exit(void)
2927 {
2928 pci_unregister_driver(&driver);
2929 }
2930
2931 module_init(alsa_card_azx_init)
2932 module_exit(alsa_card_azx_exit)
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