arch/arm/mach-davinci/board-sffsdr.c

   1 /*
   2  * Lyrtech SFFSDR board support.
   3  *
   4  * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
   5  * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
   6  *
   7  * Based on DV-EVM platform, original copyright follows:
   8  *   Copyright (C) 2007 MontaVista Software, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/gpio.h>
  31 #include <linux/i2c.h>
  32 #include <linux/i2c/at24.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/mtd/mtd.h>
  35 #include <linux/mtd/nand.h>
  36 #include <linux/mtd/partitions.h>
  37 #include <linux/mtd/physmap.h>
  38 #include <linux/io.h>
  39 #include <linux/phy.h>
  40 #include <linux/fpgadl.h>
  41
  42 #include <asm/setup.h>
  43 #include <asm/mach-types.h>
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/map.h>
  46 #include <asm/mach/flash.h>
  47
  48 #include <mach/dm644x.h>
  49 #include <mach/common.h>
  50 #include <mach/emac.h>
  51 #include <mach/i2c.h>
  52 #include <mach/serial.h>
  53 #include <mach/mmc.h>
  54 #include <mach/psc.h>
  55 #include <mach/mux.h>
  56 #include <mach/nand.h>
  57 #include <mach/mmc.h>
  58 #include <mach/sffsdr-lyrvpfe.h>
  59
  60 #define XC4VSX35_PAYLOAD_SIZE   (1707240)
  61
  62 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x01e00000
  63 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x02000000
  64
  65 #define DAVINCI_VPSS_REGS_BASE                  0x01C70000
  66
  67 #define LXT971_PHY_ID                           0x001378e2
  68 #define LXT971_PHY_MASK                         0xfffffff0
  69
  70 #define FPGA_SELECTMAP_BASE                     0x04000000
  71 #define FPGA_SFFSDR_REGS_BASE                   0x04008000
  72
  73 /* DDR2 memory is 256 Mbytes */
  74 #define DDR2_BASE               0x80000000
  75
  76 #define SFFSDR_MMC_CD_PIN       GPIO(51)
  77 #define SFFSDR_MMC_RO_PIN       GPIO(50)
  78
  79 struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
  80         /* U-Boot Environment: Block 0
  81          * UBL:                Block 1
  82          * U-Boot:             Blocks 6-7 (256 kb)
  83          * Integrity Kernel:   Blocks 8-31 (3 Mb)
  84          * Integrity Data:     Blocks 100-END
  85          */
  86         {
  87                 .name           = "Linux Kernel",
  88                 .offset         = 32 * SZ_128K,
  89                 .size           = 16 * SZ_128K, /* 2 Mb */
  90                 .mask_flags     = MTD_WRITEABLE, /* Force read-only */
  91         },
  92         {
  93                 .name           = "Linux ROOT",
  94                 .offset         = MTDPART_OFS_APPEND,
  95                 .size           = 256 * SZ_128K, /* 32 Mb */
  96                 .mask_flags     = 0, /* R/W */
  97         },
  98 };
  99
 100 static struct davinci_nand_pdata davinci_sffsdr_nandflash_data = {
 101         .parts          = davinci_sffsdr_nandflash_partition,
 102         .nr_parts       = ARRAY_SIZE(davinci_sffsdr_nandflash_partition),
 103         .ecc_mode       = NAND_ECC_HW,
 104 };
 105
 106 static struct resource davinci_sffsdr_nandflash_resource[] = {
 107         {
 108                 .start          = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
 109                 .end            = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
 110                 .flags          = IORESOURCE_MEM,
 111         }, {
 112                 .start          = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
 113                 .end            = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 114                 .flags          = IORESOURCE_MEM,
 115         },
 116 };
 117
 118 static struct platform_device davinci_sffsdr_nandflash_device = {
 119         .name           = "davinci_nand", /* Name of driver */
 120         .id             = 0,
 121         .dev            = {
 122                 .platform_data  = &davinci_sffsdr_nandflash_data,
 123         },
 124         .num_resources  = ARRAY_SIZE(davinci_sffsdr_nandflash_resource),
 125         .resource       = davinci_sffsdr_nandflash_resource,
 126 };
 127
 128 static struct at24_platform_data eeprom_info = {
 129         .byte_len       = (64*1024) / 8,
 130         .page_size      = 32,
 131         .flags          = AT24_FLAG_ADDR16,
 132 };
 133
 134 static struct i2c_board_info __initdata i2c_info[] =  {
 135         {
 136                 I2C_BOARD_INFO("24lc64", 0x50),
 137                 .platform_data  = &eeprom_info,
 138         },
 139         /* Other I2C devices:
 140          * MSP430,  addr 0x23 (not used)
 141          * PCA9543, addr 0x70 (setup done by U-Boot)
 142          * ADS7828, addr 0x48 (ADC for voltage monitoring.)
 143          */
 144 };
 145
 146 static struct davinci_i2c_platform_data i2c_pdata = {
 147         .bus_freq       = 20 /* kHz */,
 148         .bus_delay      = 100 /* usec */,
 149 };
 150
 151 static void __init sffsdr_init_i2c(void)
 152 {
 153         davinci_init_i2c(&i2c_pdata);
 154         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 155 }
 156
 157 static int sffsdr_mmc_get_cd(int module)
 158 {
 159         return gpio_get_value(SFFSDR_MMC_CD_PIN);
 160 }
 161
 162 static int sffsdr_mmc_get_ro(int module)
 163 {
 164         return gpio_get_value(SFFSDR_MMC_RO_PIN);
 165 }
 166
 167 static struct davinci_mmc_config sffsdr_mmc_config = {
 168         .get_cd         = sffsdr_mmc_get_cd,
 169         .get_ro         = sffsdr_mmc_get_ro,
 170         .wires          = 4
 171 };
 172
 173 /*
 174  * The FPGA is loaded using the SelectMAP mode through
 175  * the EMIF interface and some dedicated control signals:
 176  *
 177  *   FPGA          DM6446
 178  *   --------------------
 179  *   PROGRAM_B     GPIO37
 180  *   DONE          GPIO39
 181  *   INIT          GPIO40
 182  *   DOUT_BUSY     GPIO42 (Not used)
 183  *   CS_B          EMIF_A13 OR CS3n
 184  */
 185 static struct fpgadl_pdata_t fpgadl_par_pdata = {
 186         .fpga_family            = FPGA_FAMILY_XILINX_XC4V,
 187         .payload_full_size      = XC4VSX35_PAYLOAD_SIZE,
 188         .program_b              = GPIO(37),
 189         .done                   = GPIO(39),
 190         .init_b                 = GPIO(40),
 191         .bitstream_name         = "fpga.bit",
 192         .check_init_low         = 0,
 193 };
 194
 195 /* FPGA physical EMIF register resources. */
 196 static struct resource davinci_fpgadl_par_resources[] = {
 197         {
 198                 .name           = "selectmap",
 199                 .start          = FPGA_SELECTMAP_BASE,
 200                 .end            = FPGA_SELECTMAP_BASE + 4 - 1,
 201                 .flags          = IORESOURCE_MEM,
 202         },
 203 };
 204
 205 static struct platform_device davinci_fpgadl_par_device = {
 206         .name           = "fpgadl_par", /* Name of driver */
 207         .id             = 0,
 208         .dev            = {
 209                 .platform_data  = &fpgadl_par_pdata,
 210         },
 211         .num_resources  = ARRAY_SIZE(davinci_fpgadl_par_resources),
 212         .resource       = davinci_fpgadl_par_resources,
 213 };
 214
 215 /* SFFSDR specific FPGA registers. */
 216 static struct resource davinci_sffsdr_fpga_resources[] = {
 217         {
 218                 .name           = "sffsdr_regs",
 219                 .start          = FPGA_SFFSDR_REGS_BASE,
 220                 .end            = FPGA_SFFSDR_REGS_BASE + SZ_1K - 1,
 221                 .flags          = IORESOURCE_MEM,
 222         },
 223 };
 224
 225 static struct platform_device davinci_sffsdr_fpga_device = {
 226         .name           = "sffsdr_fpga", /* Name of driver */
 227         .id             = -1, /* Only one instance = -1 */
 228         .num_resources  = ARRAY_SIZE(davinci_sffsdr_fpga_resources),
 229         .resource       = davinci_sffsdr_fpga_resources,
 230 };
 231
 232 static struct lyrvpfe_platform_data lyrvpfe_pdata = {
 233         /*
 234          * GPIO(1) for DSP  to FPGA (VPBE)
 235          * GPIO(0) for FPGA to DSP  (VPFE)
 236          */
 237         .ready_gpio = GPIO(0), /* DSP to FPGA (VPFE) */
 238 };
 239
 240 static struct resource lyrvpfe_resources[] = {
 241         {
 242                 .name           = "regs",
 243                 .start          = DAVINCI_VPSS_REGS_BASE,
 244                 .end            = DAVINCI_VPSS_REGS_BASE + SZ_16K - 1,
 245                 .flags          = IORESOURCE_MEM,
 246         },
 247         {
 248                 .name           = "irq",
 249                 .start          = IRQ_VDINT0,
 250                 .end            = IRQ_VDINT0,
 251                 .flags          = IORESOURCE_IRQ,
 252         },
 253 };
 254
 255 static struct platform_device lyrvpfe_pdev = {
 256         .name           = "lyrvpfe",
 257         .id             = 0,
 258         .dev            = {
 259                 .platform_data  = &lyrvpfe_pdata,
 260         },
 261         .resource       = lyrvpfe_resources,
 262         .num_resources  = ARRAY_SIZE(lyrvpfe_resources),
 263 };
 264
 265 static struct platform_device *davinci_sffsdr_devices[] __initdata = {
 266         &davinci_fpgadl_par_device, /* Bitstream loading - parallel */
 267         &davinci_sffsdr_fpga_device, /* Application functionality */
 268         &lyrvpfe_pdev,
 269 };
 270
 271 /*
 272  * UART0: console
 273  * UART1: FPGA
 274  */
 275 static struct davinci_uart_config uart_config __initdata = {
 276         .enabled_uarts = DAVINCI_UART0_ENA | DAVINCI_UART1_ENA,
 277 };
 278
 279 static void __init davinci_sffsdr_map_io(void)
 280 {
 281         davinci_map_common_io();
 282         dm644x_init();
 283 }
 284
 285 static int davinci_phy_fixup(struct phy_device *phydev)
 286 {
 287         unsigned int control;
 288         /* CRITICAL: Fix for increasing PHY signal drive strength for
 289          * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
 290          * signal strength was low causing  TX to fail randomly. The
 291          * fix is to Set bit 11 (Increased MII drive strength) of PHY
 292          * register 26 (Digital Config register) on this phy. */
 293         control = phy_read(phydev, 26);
 294         phy_write(phydev, 26, (control | 0x800));
 295         return 0;
 296 }
 297
 298 static void __init davinci_sffsdr_init(void)
 299 {
 300         gpio_request(SFFSDR_MMC_CD_PIN, "MMC CD");
 301         gpio_direction_input(SFFSDR_MMC_CD_PIN);
 302         gpio_request(SFFSDR_MMC_RO_PIN, "MMC RO");
 303         gpio_direction_input(SFFSDR_MMC_RO_PIN);
 304
 305         /* Turn UART1 MUX ON. */
 306         davinci_cfg_reg(DM644X_UART1);
 307
 308         platform_add_devices(davinci_sffsdr_devices,
 309                              ARRAY_SIZE(davinci_sffsdr_devices));
 310         sffsdr_init_i2c();
 311
 312         davinci_serial_init(&uart_config);
 313
 314 #if defined(CONFIG_MTD_NAND_DAVINCI) || \
 315     defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
 316         davinci_cfg_reg(DM644X_HPIEN_DISABLE);
 317         davinci_cfg_reg(DM644X_ATAEN_DISABLE);
 318         platform_device_register(&davinci_sffsdr_nandflash_device);
 319 #endif
 320
 321         davinci_setup_mmc(0, &sffsdr_mmc_config);
 322
 323         /* Register the fixup for PHY on DaVinci */
 324         phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
 325                                         davinci_phy_fixup);
 326
 327         davinci_init_emac(NULL);
 328
 329         setup_usb(0, 0); /* We support only peripheral mode. */
 330 }
 331
 332 static void __init davinci_sffsdr_irq_init(void)
 333 {
 334         davinci_irq_init();
 335 }
 336
 337 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
 338         /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
 339         .phys_io      = IO_PHYS,
 340         .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 341         .boot_params  = (DAVINCI_DDR_BASE + 0x100),
 342         .map_io       = davinci_sffsdr_map_io,
 343         .init_irq     = davinci_sffsdr_irq_init,
 344         .init_machine = davinci_sffsdr_init,
 345         .timer        = &davinci_timer,
 346 MACHINE_END