arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <mach/dm646x.h>
  17 #include <mach/clock.h>
  18 #include <mach/cpu.h>
  19 #include <mach/edma.h>
  20 #include <mach/irqs.h>
  21 #include <mach/psc.h>
  22 #include <mach/mux.h>
  23
  24 #include "clock.h"
  25 #include "mux.h"
  26
  27 /*
  28  * Device specific clocks
  29  */
  30 #define DM646X_REF_FREQ         27000000
  31 #define DM646X_AUX_FREQ         24000000
  32
  33 static struct pll_data pll1_data = {
  34         .num       = 1,
  35         .phys_base = DAVINCI_PLL1_BASE,
  36 };
  37
  38 static struct pll_data pll2_data = {
  39         .num       = 2,
  40         .phys_base = DAVINCI_PLL2_BASE,
  41 };
  42
  43 static struct clk ref_clk = {
  44         .name = "ref_clk",
  45         .rate = DM646X_REF_FREQ,
  46 };
  47
  48 static struct clk aux_clkin = {
  49         .name = "aux_clkin",
  50         .rate = DM646X_AUX_FREQ,
  51 };
  52
  53 static struct clk pll1_clk = {
  54         .name = "pll1",
  55         .parent = &ref_clk,
  56         .pll_data = &pll1_data,
  57         .flags = CLK_PLL,
  58 };
  59
  60 static struct clk pll1_sysclk1 = {
  61         .name = "pll1_sysclk1",
  62         .parent = &pll1_clk,
  63         .flags = CLK_PLL,
  64         .div_reg = PLLDIV1,
  65 };
  66
  67 static struct clk pll1_sysclk2 = {
  68         .name = "pll1_sysclk2",
  69         .parent = &pll1_clk,
  70         .flags = CLK_PLL,
  71         .div_reg = PLLDIV2,
  72 };
  73
  74 static struct clk pll1_sysclk3 = {
  75         .name = "pll1_sysclk3",
  76         .parent = &pll1_clk,
  77         .flags = CLK_PLL,
  78         .div_reg = PLLDIV3,
  79 };
  80
  81 static struct clk pll1_sysclk4 = {
  82         .name = "pll1_sysclk4",
  83         .parent = &pll1_clk,
  84         .flags = CLK_PLL,
  85         .div_reg = PLLDIV4,
  86 };
  87
  88 static struct clk pll1_sysclk5 = {
  89         .name = "pll1_sysclk5",
  90         .parent = &pll1_clk,
  91         .flags = CLK_PLL,
  92         .div_reg = PLLDIV5,
  93 };
  94
  95 static struct clk pll1_sysclk6 = {
  96         .name = "pll1_sysclk6",
  97         .parent = &pll1_clk,
  98         .flags = CLK_PLL,
  99         .div_reg = PLLDIV6,
 100 };
 101
 102 static struct clk pll1_sysclk8 = {
 103         .name = "pll1_sysclk8",
 104         .parent = &pll1_clk,
 105         .flags = CLK_PLL,
 106         .div_reg = PLLDIV8,
 107 };
 108
 109 static struct clk pll1_sysclk9 = {
 110         .name = "pll1_sysclk9",
 111         .parent = &pll1_clk,
 112         .flags = CLK_PLL,
 113         .div_reg = PLLDIV9,
 114 };
 115
 116 static struct clk pll1_sysclkbp = {
 117         .name = "pll1_sysclkbp",
 118         .parent = &pll1_clk,
 119         .flags = CLK_PLL | PRE_PLL,
 120         .div_reg = BPDIV,
 121 };
 122
 123 static struct clk pll1_aux_clk = {
 124         .name = "pll1_aux_clk",
 125         .parent = &pll1_clk,
 126         .flags = CLK_PLL | PRE_PLL,
 127 };
 128
 129 static struct clk pll2_clk = {
 130         .name = "pll2_clk",
 131         .parent = &ref_clk,
 132         .pll_data = &pll2_data,
 133         .flags = CLK_PLL,
 134 };
 135
 136 static struct clk pll2_sysclk1 = {
 137         .name = "pll2_sysclk1",
 138         .parent = &pll2_clk,
 139         .flags = CLK_PLL,
 140         .div_reg = PLLDIV1,
 141 };
 142
 143 static struct clk dsp_clk = {
 144         .name = "dsp",
 145         .parent = &pll1_sysclk1,
 146         .lpsc = DM646X_LPSC_C64X_CPU,
 147         .flags = PSC_DSP,
 148         .usecount = 1,                  /* REVISIT how to disable? */
 149 };
 150
 151 static struct clk arm_clk = {
 152         .name = "arm",
 153         .parent = &pll1_sysclk2,
 154         .lpsc = DM646X_LPSC_ARM,
 155         .flags = ALWAYS_ENABLED,
 156 };
 157
 158 static struct clk uart0_clk = {
 159         .name = "uart0",
 160         .parent = &aux_clkin,
 161         .lpsc = DM646X_LPSC_UART0,
 162 };
 163
 164 static struct clk uart1_clk = {
 165         .name = "uart1",
 166         .parent = &aux_clkin,
 167         .lpsc = DM646X_LPSC_UART1,
 168 };
 169
 170 static struct clk uart2_clk = {
 171         .name = "uart2",
 172         .parent = &aux_clkin,
 173         .lpsc = DM646X_LPSC_UART2,
 174 };
 175
 176 static struct clk i2c_clk = {
 177         .name = "I2CCLK",
 178         .parent = &pll1_sysclk3,
 179         .lpsc = DM646X_LPSC_I2C,
 180 };
 181
 182 static struct clk gpio_clk = {
 183         .name = "gpio",
 184         .parent = &pll1_sysclk3,
 185         .lpsc = DM646X_LPSC_GPIO,
 186 };
 187
 188 static struct clk aemif_clk = {
 189         .name = "aemif",
 190         .parent = &pll1_sysclk3,
 191         .lpsc = DM646X_LPSC_AEMIF,
 192         .flags = ALWAYS_ENABLED,
 193 };
 194
 195 static struct clk emac_clk = {
 196         .name = "emac",
 197         .parent = &pll1_sysclk3,
 198         .lpsc = DM646X_LPSC_EMAC,
 199 };
 200
 201 static struct clk pwm0_clk = {
 202         .name = "pwm0",
 203         .parent = &pll1_sysclk3,
 204         .lpsc = DM646X_LPSC_PWM0,
 205         .usecount = 1,            /* REVIST: disabling hangs system */
 206 };
 207
 208 static struct clk pwm1_clk = {
 209         .name = "pwm1",
 210         .parent = &pll1_sysclk3,
 211         .lpsc = DM646X_LPSC_PWM1,
 212         .usecount = 1,            /* REVIST: disabling hangs system */
 213 };
 214
 215 static struct clk timer0_clk = {
 216         .name = "timer0",
 217         .parent = &pll1_sysclk3,
 218         .lpsc = DM646X_LPSC_TIMER0,
 219 };
 220
 221 static struct clk timer1_clk = {
 222         .name = "timer1",
 223         .parent = &pll1_sysclk3,
 224         .lpsc = DM646X_LPSC_TIMER1,
 225 };
 226
 227 static struct clk timer2_clk = {
 228         .name = "timer2",
 229         .parent = &pll1_sysclk3,
 230         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 231 };
 232
 233 struct davinci_clk dm646x_clks[] = {
 234         CLK(NULL, "ref", &ref_clk),
 235         CLK(NULL, "aux", &aux_clkin),
 236         CLK(NULL, "pll1", &pll1_clk),
 237         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 238         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 239         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 240         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 241         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 242         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 243         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 244         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 245         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 246         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 247         CLK(NULL, "pll2", &pll2_clk),
 248         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 249         CLK(NULL, "dsp", &dsp_clk),
 250         CLK(NULL, "arm", &arm_clk),
 251         CLK(NULL, "uart0", &uart0_clk),
 252         CLK(NULL, "uart1", &uart1_clk),
 253         CLK(NULL, "uart2", &uart2_clk),
 254         CLK("i2c_davinci.1", NULL, &i2c_clk),
 255         CLK(NULL, "gpio", &gpio_clk),
 256         CLK(NULL, "aemif", &aemif_clk),
 257         CLK("davinci_emac.1", NULL, &emac_clk),
 258         CLK(NULL, "pwm0", &pwm0_clk),
 259         CLK(NULL, "pwm1", &pwm1_clk),
 260         CLK(NULL, "timer0", &timer0_clk),
 261         CLK(NULL, "timer1", &timer1_clk),
 262         CLK("watchdog", NULL, &timer2_clk),
 263         CLK(NULL, NULL, NULL),
 264 };
 265
 266 /*
 267  * Device specific mux setup
 268  *
 269  *      soc     description     mux  mode   mode  mux    dbg
 270  *                              reg  offset mask  mode
 271  */
 272 static const struct mux_config dm646x_pins[] = {
 273 MUX_CFG(DM646X, ATAEN,          0,   0,     1,    1,     true)
 274
 275 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 276
 277 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 278 };
 279
 280 /*----------------------------------------------------------------------*/
 281
 282 static const s8 dma_chan_dm646x_no_event[] = {
 283          0,  1,  2,  3, 13,
 284         14, 15, 24, 25, 26,
 285         27, 30, 31, 54, 55,
 286         56,
 287         -1
 288 };
 289
 290 static struct edma_soc_info dm646x_edma_info = {
 291         .n_channel      = 64,
 292         .n_region       = 6,    /* 0-1, 4-7 */
 293         .n_slot         = 512,
 294         .n_tc           = 4,
 295         .noevent        = dma_chan_dm646x_no_event,
 296 };
 297
 298 static struct resource edma_resources[] = {
 299         {
 300                 .name   = "edma_cc",
 301                 .start  = 0x01c00000,
 302                 .end    = 0x01c00000 + SZ_64K - 1,
 303                 .flags  = IORESOURCE_MEM,
 304         },
 305         {
 306                 .name   = "edma_tc0",
 307                 .start  = 0x01c10000,
 308                 .end    = 0x01c10000 + SZ_1K - 1,
 309                 .flags  = IORESOURCE_MEM,
 310         },
 311         {
 312                 .name   = "edma_tc1",
 313                 .start  = 0x01c10400,
 314                 .end    = 0x01c10400 + SZ_1K - 1,
 315                 .flags  = IORESOURCE_MEM,
 316         },
 317         {
 318                 .name   = "edma_tc2",
 319                 .start  = 0x01c10800,
 320                 .end    = 0x01c10800 + SZ_1K - 1,
 321                 .flags  = IORESOURCE_MEM,
 322         },
 323         {
 324                 .name   = "edma_tc3",
 325                 .start  = 0x01c10c00,
 326                 .end    = 0x01c10c00 + SZ_1K - 1,
 327                 .flags  = IORESOURCE_MEM,
 328         },
 329         {
 330                 .start  = IRQ_CCINT0,
 331                 .flags  = IORESOURCE_IRQ,
 332         },
 333         {
 334                 .start  = IRQ_CCERRINT,
 335                 .flags  = IORESOURCE_IRQ,
 336         },
 337         /* not using TC*_ERR */
 338 };
 339
 340 static struct platform_device dm646x_edma_device = {
 341         .name                   = "edma",
 342         .id                     = -1,
 343         .dev.platform_data      = &dm646x_edma_info,
 344         .num_resources          = ARRAY_SIZE(edma_resources),
 345         .resource               = edma_resources,
 346 };
 347
 348 /*----------------------------------------------------------------------*/
 349
 350
 351 void __init dm646x_init(void)
 352 {
 353         davinci_clk_init(dm646x_clks);
 354         davinci_mux_register(dm646x_pins, ARRAY_SIZE(dm646x_pins));
 355 }
 356
 357 static int __init dm646x_init_devices(void)
 358 {
 359         if (!cpu_is_davinci_dm646x())
 360                 return 0;
 361
 362         platform_device_register(&dm646x_edma_device);
 363         return 0;
 364 }
 365 postcore_initcall(dm646x_init_devices);