arch/arm/mach-davinci/psc.c

   1 /*
   2  * TI DaVinci Power and Sleep Controller (PSC)
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  *
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25
  26 #include <mach/cpu.h>
  27 #include <mach/hardware.h>
  28 #include <mach/psc.h>
  29 #include <mach/mux.h>
  30
  31 #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
  32
  33 /* PSC register offsets */
  34 #define EPCPR           0x070
  35 #define PTCMD           0x120
  36 #define PTSTAT          0x128
  37 #define PDSTAT          0x200
  38 #define PDCTL1          0x304
  39 #define MDSTAT          0x800
  40 #define MDCTL           0xA00
  41
  42 /* Enable or disable a PSC domain */
  43 void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
  44 {
  45         u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
  46         void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
  47
  48         mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
  49         if (enable)
  50                 mdctl |= 0x00000003;    /* Enable Module */
  51         else
  52                 mdctl &= 0xFFFFFFF2;    /* Disable Module */
  53         __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
  54
  55         pdstat = __raw_readl(psc_base + PDSTAT);
  56         if ((pdstat & 0x00000001) == 0) {
  57                 pdctl1 = __raw_readl(psc_base + PDCTL1);
  58                 pdctl1 |= 0x1;
  59                 __raw_writel(pdctl1, psc_base + PDCTL1);
  60
  61                 ptcmd = 1 << domain;
  62                 __raw_writel(ptcmd, psc_base + PTCMD);
  63
  64                 do {
  65                         epcpr = __raw_readl(psc_base + EPCPR);
  66                 } while ((((epcpr >> domain) & 1) == 0));
  67
  68                 pdctl1 = __raw_readl(psc_base + PDCTL1);
  69                 pdctl1 |= 0x100;
  70                 __raw_writel(pdctl1, psc_base + PDCTL1);
  71
  72                 do {
  73                         ptstat = __raw_readl(psc_base +
  74                                                PTSTAT);
  75                 } while (!(((ptstat >> domain) & 1) == 0));
  76         } else {
  77                 ptcmd = 1 << domain;
  78                 __raw_writel(ptcmd, psc_base + PTCMD);
  79
  80                 do {
  81                         ptstat = __raw_readl(psc_base + PTSTAT);
  82                 } while (!(((ptstat >> domain) & 1) == 0));
  83         }
  84
  85         if (enable)
  86                 mdstat_mask = 0x3;
  87         else
  88                 mdstat_mask = 0x2;
  89
  90         do {
  91                 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
  92         } while (!((mdstat & 0x0000001F) == mdstat_mask));
  93 }