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SFFSDR: Update to board code to support FPGA and lyrvpss drivers
[linux-davinci-sffsdr.git] / arch / arm / mach-orion5x / common.c
blob0a623379789f03c4603cc43f33ebabcb2a8759b4
1 /*
2 * arch/arm/mach-orion5x/common.c
3 *
4 * Core functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/serial_8250.h>
17 #include <linux/mbus.h>
18 #include <linux/mv643xx_eth.h>
19 #include <linux/mv643xx_i2c.h>
20 #include <linux/ata_platform.h>
21 #include <linux/spi/orion_spi.h>
22 #include <net/dsa.h>
23 #include <asm/page.h>
24 #include <asm/setup.h>
25 #include <asm/timex.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/time.h>
29 #include <mach/hardware.h>
30 #include <mach/orion5x.h>
31 #include <plat/ehci-orion.h>
32 #include <plat/mv_xor.h>
33 #include <plat/orion_nand.h>
34 #include <plat/time.h>
35 #include "common.h"
36
37 /*****************************************************************************
38 * I/O Address Mapping
39 ****************************************************************************/
40 static struct map_desc orion5x_io_desc[] __initdata = {
41 {
42 .virtual = ORION5X_REGS_VIRT_BASE,
43 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
44 .length = ORION5X_REGS_SIZE,
45 .type = MT_DEVICE,
46 }, {
47 .virtual = ORION5X_PCIE_IO_VIRT_BASE,
48 .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
49 .length = ORION5X_PCIE_IO_SIZE,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = ORION5X_PCI_IO_VIRT_BASE,
53 .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
54 .length = ORION5X_PCI_IO_SIZE,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = ORION5X_PCIE_WA_VIRT_BASE,
58 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
59 .length = ORION5X_PCIE_WA_SIZE,
60 .type = MT_DEVICE,
61 },
62 };
63
64 void __init orion5x_map_io(void)
65 {
66 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
67 }
68
69
70 /*****************************************************************************
71 * EHCI
72 ****************************************************************************/
73 static struct orion_ehci_data orion5x_ehci_data = {
74 .dram = &orion5x_mbus_dram_info,
75 .phy_version = EHCI_PHY_ORION,
76 };
77
78 static u64 ehci_dmamask = 0xffffffffUL;
79
80
81 /*****************************************************************************
82 * EHCI0
83 ****************************************************************************/
84 static struct resource orion5x_ehci0_resources[] = {
85 {
86 .start = ORION5X_USB0_PHYS_BASE,
87 .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
88 .flags = IORESOURCE_MEM,
89 }, {
90 .start = IRQ_ORION5X_USB0_CTRL,
91 .end = IRQ_ORION5X_USB0_CTRL,
92 .flags = IORESOURCE_IRQ,
93 },
94 };
95
96 static struct platform_device orion5x_ehci0 = {
97 .name = "orion-ehci",
98 .id = 0,
99 .dev = {
100 .dma_mask = &ehci_dmamask,
101 .coherent_dma_mask = 0xffffffff,
102 .platform_data = &orion5x_ehci_data,
103 },
104 .resource = orion5x_ehci0_resources,
105 .num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
106 };
107
108 void __init orion5x_ehci0_init(void)
109 {
110 platform_device_register(&orion5x_ehci0);
111 }
112
113
114 /*****************************************************************************
115 * EHCI1
116 ****************************************************************************/
117 static struct resource orion5x_ehci1_resources[] = {
118 {
119 .start = ORION5X_USB1_PHYS_BASE,
120 .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
121 .flags = IORESOURCE_MEM,
122 }, {
123 .start = IRQ_ORION5X_USB1_CTRL,
124 .end = IRQ_ORION5X_USB1_CTRL,
125 .flags = IORESOURCE_IRQ,
126 },
127 };
128
129 static struct platform_device orion5x_ehci1 = {
130 .name = "orion-ehci",
131 .id = 1,
132 .dev = {
133 .dma_mask = &ehci_dmamask,
134 .coherent_dma_mask = 0xffffffff,
135 .platform_data = &orion5x_ehci_data,
136 },
137 .resource = orion5x_ehci1_resources,
138 .num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
139 };
140
141 void __init orion5x_ehci1_init(void)
142 {
143 platform_device_register(&orion5x_ehci1);
144 }
145
146
147 /*****************************************************************************
148 * GigE
149 ****************************************************************************/
150 struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
151 .dram = &orion5x_mbus_dram_info,
152 };
153
154 static struct resource orion5x_eth_shared_resources[] = {
155 {
156 .start = ORION5X_ETH_PHYS_BASE + 0x2000,
157 .end = ORION5X_ETH_PHYS_BASE + 0x3fff,
158 .flags = IORESOURCE_MEM,
159 }, {
160 .start = IRQ_ORION5X_ETH_ERR,
161 .end = IRQ_ORION5X_ETH_ERR,
162 .flags = IORESOURCE_IRQ,
163 },
164 };
165
166 static struct platform_device orion5x_eth_shared = {
167 .name = MV643XX_ETH_SHARED_NAME,
168 .id = 0,
169 .dev = {
170 .platform_data = &orion5x_eth_shared_data,
171 },
172 .num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
173 .resource = orion5x_eth_shared_resources,
174 };
175
176 static struct resource orion5x_eth_resources[] = {
177 {
178 .name = "eth irq",
179 .start = IRQ_ORION5X_ETH_SUM,
180 .end = IRQ_ORION5X_ETH_SUM,
181 .flags = IORESOURCE_IRQ,
182 },
183 };
184
185 static struct platform_device orion5x_eth = {
186 .name = MV643XX_ETH_NAME,
187 .id = 0,
188 .num_resources = 1,
189 .resource = orion5x_eth_resources,
190 };
191
192 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
193 {
194 eth_data->shared = &orion5x_eth_shared;
195 orion5x_eth.dev.platform_data = eth_data;
196
197 platform_device_register(&orion5x_eth_shared);
198 platform_device_register(&orion5x_eth);
199 }
200
201
202 /*****************************************************************************
203 * Ethernet switch
204 ****************************************************************************/
205 static struct resource orion5x_switch_resources[] = {
206 {
207 .start = 0,
208 .end = 0,
209 .flags = IORESOURCE_IRQ,
210 },
211 };
212
213 static struct platform_device orion5x_switch_device = {
214 .name = "dsa",
215 .id = 0,
216 .num_resources = 0,
217 .resource = orion5x_switch_resources,
218 };
219
220 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
221 {
222 if (irq != NO_IRQ) {
223 orion5x_switch_resources[0].start = irq;
224 orion5x_switch_resources[0].end = irq;
225 orion5x_switch_device.num_resources = 1;
226 }
227
228 d->mii_bus = &orion5x_eth_shared.dev;
229 d->netdev = &orion5x_eth.dev;
230 orion5x_switch_device.dev.platform_data = d;
231
232 platform_device_register(&orion5x_switch_device);
233 }
234
235
236 /*****************************************************************************
237 * I2C
238 ****************************************************************************/
239 static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
240 .freq_m = 8, /* assumes 166 MHz TCLK */
241 .freq_n = 3,
242 .timeout = 1000, /* Default timeout of 1 second */
243 };
244
245 static struct resource orion5x_i2c_resources[] = {
246 {
247 .name = "i2c base",
248 .start = I2C_PHYS_BASE,
249 .end = I2C_PHYS_BASE + 0x1f,
250 .flags = IORESOURCE_MEM,
251 }, {
252 .name = "i2c irq",
253 .start = IRQ_ORION5X_I2C,
254 .end = IRQ_ORION5X_I2C,
255 .flags = IORESOURCE_IRQ,
256 },
257 };
258
259 static struct platform_device orion5x_i2c = {
260 .name = MV64XXX_I2C_CTLR_NAME,
261 .id = 0,
262 .num_resources = ARRAY_SIZE(orion5x_i2c_resources),
263 .resource = orion5x_i2c_resources,
264 .dev = {
265 .platform_data = &orion5x_i2c_pdata,
266 },
267 };
268
269 void __init orion5x_i2c_init(void)
270 {
271 platform_device_register(&orion5x_i2c);
272 }
273
274
275 /*****************************************************************************
276 * SATA
277 ****************************************************************************/
278 static struct resource orion5x_sata_resources[] = {
279 {
280 .name = "sata base",
281 .start = ORION5X_SATA_PHYS_BASE,
282 .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
283 .flags = IORESOURCE_MEM,
284 }, {
285 .name = "sata irq",
286 .start = IRQ_ORION5X_SATA,
287 .end = IRQ_ORION5X_SATA,
288 .flags = IORESOURCE_IRQ,
289 },
290 };
291
292 static struct platform_device orion5x_sata = {
293 .name = "sata_mv",
294 .id = 0,
295 .dev = {
296 .coherent_dma_mask = 0xffffffff,
297 },
298 .num_resources = ARRAY_SIZE(orion5x_sata_resources),
299 .resource = orion5x_sata_resources,
300 };
301
302 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
303 {
304 sata_data->dram = &orion5x_mbus_dram_info;
305 orion5x_sata.dev.platform_data = sata_data;
306 platform_device_register(&orion5x_sata);
307 }
308
309
310 /*****************************************************************************
311 * SPI
312 ****************************************************************************/
313 static struct orion_spi_info orion5x_spi_plat_data = {
314 .tclk = 0,
315 .enable_clock_fix = 1,
316 };
317
318 static struct resource orion5x_spi_resources[] = {
319 {
320 .name = "spi base",
321 .start = SPI_PHYS_BASE,
322 .end = SPI_PHYS_BASE + 0x1f,
323 .flags = IORESOURCE_MEM,
324 },
325 };
326
327 static struct platform_device orion5x_spi = {
328 .name = "orion_spi",
329 .id = 0,
330 .dev = {
331 .platform_data = &orion5x_spi_plat_data,
332 },
333 .num_resources = ARRAY_SIZE(orion5x_spi_resources),
334 .resource = orion5x_spi_resources,
335 };
336
337 void __init orion5x_spi_init()
338 {
339 platform_device_register(&orion5x_spi);
340 }
341
342
343 /*****************************************************************************
344 * UART0
345 ****************************************************************************/
346 static struct plat_serial8250_port orion5x_uart0_data[] = {
347 {
348 .mapbase = UART0_PHYS_BASE,
349 .membase = (char *)UART0_VIRT_BASE,
350 .irq = IRQ_ORION5X_UART0,
351 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
352 .iotype = UPIO_MEM,
353 .regshift = 2,
354 .uartclk = 0,
355 }, {
356 },
357 };
358
359 static struct resource orion5x_uart0_resources[] = {
360 {
361 .start = UART0_PHYS_BASE,
362 .end = UART0_PHYS_BASE + 0xff,
363 .flags = IORESOURCE_MEM,
364 }, {
365 .start = IRQ_ORION5X_UART0,
366 .end = IRQ_ORION5X_UART0,
367 .flags = IORESOURCE_IRQ,
368 },
369 };
370
371 static struct platform_device orion5x_uart0 = {
372 .name = "serial8250",
373 .id = PLAT8250_DEV_PLATFORM,
374 .dev = {
375 .platform_data = orion5x_uart0_data,
376 },
377 .resource = orion5x_uart0_resources,
378 .num_resources = ARRAY_SIZE(orion5x_uart0_resources),
379 };
380
381 void __init orion5x_uart0_init(void)
382 {
383 platform_device_register(&orion5x_uart0);
384 }
385
386
387 /*****************************************************************************
388 * UART1
389 ****************************************************************************/
390 static struct plat_serial8250_port orion5x_uart1_data[] = {
391 {
392 .mapbase = UART1_PHYS_BASE,
393 .membase = (char *)UART1_VIRT_BASE,
394 .irq = IRQ_ORION5X_UART1,
395 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
396 .iotype = UPIO_MEM,
397 .regshift = 2,
398 .uartclk = 0,
399 }, {
400 },
401 };
402
403 static struct resource orion5x_uart1_resources[] = {
404 {
405 .start = UART1_PHYS_BASE,
406 .end = UART1_PHYS_BASE + 0xff,
407 .flags = IORESOURCE_MEM,
408 }, {
409 .start = IRQ_ORION5X_UART1,
410 .end = IRQ_ORION5X_UART1,
411 .flags = IORESOURCE_IRQ,
412 },
413 };
414
415 static struct platform_device orion5x_uart1 = {
416 .name = "serial8250",
417 .id = PLAT8250_DEV_PLATFORM1,
418 .dev = {
419 .platform_data = orion5x_uart1_data,
420 },
421 .resource = orion5x_uart1_resources,
422 .num_resources = ARRAY_SIZE(orion5x_uart1_resources),
423 };
424
425 void __init orion5x_uart1_init(void)
426 {
427 platform_device_register(&orion5x_uart1);
428 }
429
430
431 /*****************************************************************************
432 * XOR engine
433 ****************************************************************************/
434 static struct resource orion5x_xor_shared_resources[] = {
435 {
436 .name = "xor low",
437 .start = ORION5X_XOR_PHYS_BASE,
438 .end = ORION5X_XOR_PHYS_BASE + 0xff,
439 .flags = IORESOURCE_MEM,
440 }, {
441 .name = "xor high",
442 .start = ORION5X_XOR_PHYS_BASE + 0x200,
443 .end = ORION5X_XOR_PHYS_BASE + 0x2ff,
444 .flags = IORESOURCE_MEM,
445 },
446 };
447
448 static struct platform_device orion5x_xor_shared = {
449 .name = MV_XOR_SHARED_NAME,
450 .id = 0,
451 .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
452 .resource = orion5x_xor_shared_resources,
453 };
454
455 static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;
456
457 static struct resource orion5x_xor0_resources[] = {
458 [0] = {
459 .start = IRQ_ORION5X_XOR0,
460 .end = IRQ_ORION5X_XOR0,
461 .flags = IORESOURCE_IRQ,
462 },
463 };
464
465 static struct mv_xor_platform_data orion5x_xor0_data = {
466 .shared = &orion5x_xor_shared,
467 .hw_id = 0,
468 .pool_size = PAGE_SIZE,
469 };
470
471 static struct platform_device orion5x_xor0_channel = {
472 .name = MV_XOR_NAME,
473 .id = 0,
474 .num_resources = ARRAY_SIZE(orion5x_xor0_resources),
475 .resource = orion5x_xor0_resources,
476 .dev = {
477 .dma_mask = &orion5x_xor_dmamask,
478 .coherent_dma_mask = DMA_64BIT_MASK,
479 .platform_data = (void *)&orion5x_xor0_data,
480 },
481 };
482
483 static struct resource orion5x_xor1_resources[] = {
484 [0] = {
485 .start = IRQ_ORION5X_XOR1,
486 .end = IRQ_ORION5X_XOR1,
487 .flags = IORESOURCE_IRQ,
488 },
489 };
490
491 static struct mv_xor_platform_data orion5x_xor1_data = {
492 .shared = &orion5x_xor_shared,
493 .hw_id = 1,
494 .pool_size = PAGE_SIZE,
495 };
496
497 static struct platform_device orion5x_xor1_channel = {
498 .name = MV_XOR_NAME,
499 .id = 1,
500 .num_resources = ARRAY_SIZE(orion5x_xor1_resources),
501 .resource = orion5x_xor1_resources,
502 .dev = {
503 .dma_mask = &orion5x_xor_dmamask,
504 .coherent_dma_mask = DMA_64BIT_MASK,
505 .platform_data = (void *)&orion5x_xor1_data,
506 },
507 };
508
509 void __init orion5x_xor_init(void)
510 {
511 platform_device_register(&orion5x_xor_shared);
512
513 /*
514 * two engines can't do memset simultaneously, this limitation
515 * satisfied by removing memset support from one of the engines.
516 */
517 dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
518 dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
519 platform_device_register(&orion5x_xor0_channel);
520
521 dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
522 dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
523 dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
524 platform_device_register(&orion5x_xor1_channel);
525 }
526
527
528 /*****************************************************************************
529 * Time handling
530 ****************************************************************************/
531 int orion5x_tclk;
532
533 int __init orion5x_find_tclk(void)
534 {
535 u32 dev, rev;
536
537 orion5x_pcie_id(&dev, &rev);
538 if (dev == MV88F6183_DEV_ID &&
539 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
540 return 133333333;
541
542 return 166666667;
543 }
544
545 static void orion5x_timer_init(void)
546 {
547 orion5x_tclk = orion5x_find_tclk();
548 orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
549 }
550
551 struct sys_timer orion5x_timer = {
552 .init = orion5x_timer_init,
553 };
554
555
556 /*****************************************************************************
557 * General
558 ****************************************************************************/
559 /*
560 * Identify device ID and rev from PCIe configuration header space '0'.
561 */
562 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
563 {
564 orion5x_pcie_id(dev, rev);
565
566 if (*dev == MV88F5281_DEV_ID) {
567 if (*rev == MV88F5281_REV_D2) {
568 *dev_name = "MV88F5281-D2";
569 } else if (*rev == MV88F5281_REV_D1) {
570 *dev_name = "MV88F5281-D1";
571 } else if (*rev == MV88F5281_REV_D0) {
572 *dev_name = "MV88F5281-D0";
573 } else {
574 *dev_name = "MV88F5281-Rev-Unsupported";
575 }
576 } else if (*dev == MV88F5182_DEV_ID) {
577 if (*rev == MV88F5182_REV_A2) {
578 *dev_name = "MV88F5182-A2";
579 } else {
580 *dev_name = "MV88F5182-Rev-Unsupported";
581 }
582 } else if (*dev == MV88F5181_DEV_ID) {
583 if (*rev == MV88F5181_REV_B1) {
584 *dev_name = "MV88F5181-Rev-B1";
585 } else if (*rev == MV88F5181L_REV_A1) {
586 *dev_name = "MV88F5181L-Rev-A1";
587 } else {
588 *dev_name = "MV88F5181(L)-Rev-Unsupported";
589 }
590 } else if (*dev == MV88F6183_DEV_ID) {
591 if (*rev == MV88F6183_REV_B0) {
592 *dev_name = "MV88F6183-Rev-B0";
593 } else {
594 *dev_name = "MV88F6183-Rev-Unsupported";
595 }
596 } else {
597 *dev_name = "Device-Unknown";
598 }
599 }
600
601 void __init orion5x_init(void)
602 {
603 char *dev_name;
604 u32 dev, rev;
605
606 orion5x_id(&dev, &rev, &dev_name);
607 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
608
609 orion5x_eth_shared_data.t_clk = orion5x_tclk;
610 orion5x_spi_plat_data.tclk = orion5x_tclk;
611 orion5x_uart0_data[0].uartclk = orion5x_tclk;
612 orion5x_uart1_data[0].uartclk = orion5x_tclk;
613
614 /*
615 * Setup Orion address map
616 */
617 orion5x_setup_cpu_mbus_bridge();
618
619 /*
620 * Don't issue "Wait for Interrupt" instruction if we are
621 * running on D0 5281 silicon.
622 */
623 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
624 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
625 disable_hlt();
626 }
627 }
628
629 /*
630 * Many orion-based systems have buggy bootloader implementations.
631 * This is a common fixup for bogus memory tags.
632 */
633 void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
634 char **from, struct meminfo *meminfo)
635 {
636 for (; t->hdr.size; t = tag_next(t))
637 if (t->hdr.tag == ATAG_MEM &&
638 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
639 t->u.mem.start & ~PAGE_MASK)) {
640 printk(KERN_WARNING
641 "Clearing invalid memory bank %dKB@0x%08x\n",
642 t->u.mem.size / 1024, t->u.mem.start);
643 t->hdr.tag = 0;
644 }
645 }
Linux for the Lyrtech SFFSDR board